Revision afa88c3a target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 1006 | 1006 |
} |
| 1007 | 1007 |
|
| 1008 | 1008 |
/* Load */ |
| 1009 |
static void gen_ld (DisasContext *ctx, uint32_t opc, int rt,
|
|
| 1010 |
int base, int16_t offset)
|
|
| 1009 |
static void gen_ld (CPUState *env, DisasContext *ctx, uint32_t opc,
|
|
| 1010 |
int rt, int base, int16_t offset)
|
|
| 1011 | 1011 |
{
|
| 1012 | 1012 |
const char *opn = "ld"; |
| 1013 |
TCGv t0 = tcg_temp_new(); |
|
| 1014 |
TCGv t1 = tcg_temp_new(); |
|
| 1013 |
TCGv t0, t1; |
|
| 1014 |
|
|
| 1015 |
if (rt == 0 && env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
|
|
| 1016 |
/* Loongson CPU uses a load to zero register for prefetch. |
|
| 1017 |
We emulate it as a NOP. On other CPU we must perform the |
|
| 1018 |
actual memory access. */ |
|
| 1019 |
MIPS_DEBUG("NOP");
|
|
| 1020 |
return; |
|
| 1021 |
} |
|
| 1015 | 1022 |
|
| 1023 |
t0 = tcg_temp_new(); |
|
| 1024 |
t1 = tcg_temp_new(); |
|
| 1016 | 1025 |
gen_base_offset_addr(ctx, t0, base, offset); |
| 1017 |
/* Don't do NOP if destination is zero: we must perform the actual |
|
| 1018 |
memory access. */ |
|
| 1026 |
|
|
| 1019 | 1027 |
switch (opc) {
|
| 1020 | 1028 |
#if defined(TARGET_MIPS64) |
| 1021 | 1029 |
case OPC_LWU: |
| ... | ... | |
| 8258 | 8266 |
case I64_LDSP: |
| 8259 | 8267 |
check_mips_64(ctx); |
| 8260 | 8268 |
offset = extended ? offset : offset << 3; |
| 8261 |
gen_ld(ctx, OPC_LD, ry, 29, offset); |
|
| 8269 |
gen_ld(env, ctx, OPC_LD, ry, 29, offset);
|
|
| 8262 | 8270 |
break; |
| 8263 | 8271 |
case I64_SDSP: |
| 8264 | 8272 |
check_mips_64(ctx); |
| ... | ... | |
| 8280 | 8288 |
generate_exception(ctx, EXCP_RI); |
| 8281 | 8289 |
} else {
|
| 8282 | 8290 |
offset = extended ? offset : offset << 3; |
| 8283 |
gen_ld(ctx, OPC_LDPC, ry, 0, offset); |
|
| 8291 |
gen_ld(env, ctx, OPC_LDPC, ry, 0, offset);
|
|
| 8284 | 8292 |
} |
| 8285 | 8293 |
break; |
| 8286 | 8294 |
case I64_DADDIU5: |
| ... | ... | |
| 8364 | 8372 |
#if defined(TARGET_MIPS64) |
| 8365 | 8373 |
case M16_OPC_LD: |
| 8366 | 8374 |
check_mips_64(ctx); |
| 8367 |
gen_ld(ctx, OPC_LD, ry, rx, offset); |
|
| 8375 |
gen_ld(env, ctx, OPC_LD, ry, rx, offset);
|
|
| 8368 | 8376 |
break; |
| 8369 | 8377 |
#endif |
| 8370 | 8378 |
case M16_OPC_RRIA: |
| ... | ... | |
| 8444 | 8452 |
break; |
| 8445 | 8453 |
#endif |
| 8446 | 8454 |
case M16_OPC_LB: |
| 8447 |
gen_ld(ctx, OPC_LB, ry, rx, offset); |
|
| 8455 |
gen_ld(env, ctx, OPC_LB, ry, rx, offset);
|
|
| 8448 | 8456 |
break; |
| 8449 | 8457 |
case M16_OPC_LH: |
| 8450 |
gen_ld(ctx, OPC_LH, ry, rx, offset); |
|
| 8458 |
gen_ld(env, ctx, OPC_LH, ry, rx, offset);
|
|
| 8451 | 8459 |
break; |
| 8452 | 8460 |
case M16_OPC_LWSP: |
| 8453 |
gen_ld(ctx, OPC_LW, rx, 29, offset); |
|
| 8461 |
gen_ld(env, ctx, OPC_LW, rx, 29, offset);
|
|
| 8454 | 8462 |
break; |
| 8455 | 8463 |
case M16_OPC_LW: |
| 8456 |
gen_ld(ctx, OPC_LW, ry, rx, offset); |
|
| 8464 |
gen_ld(env, ctx, OPC_LW, ry, rx, offset);
|
|
| 8457 | 8465 |
break; |
| 8458 | 8466 |
case M16_OPC_LBU: |
| 8459 |
gen_ld(ctx, OPC_LBU, ry, rx, offset); |
|
| 8467 |
gen_ld(env, ctx, OPC_LBU, ry, rx, offset);
|
|
| 8460 | 8468 |
break; |
| 8461 | 8469 |
case M16_OPC_LHU: |
| 8462 |
gen_ld(ctx, OPC_LHU, ry, rx, offset); |
|
| 8470 |
gen_ld(env, ctx, OPC_LHU, ry, rx, offset);
|
|
| 8463 | 8471 |
break; |
| 8464 | 8472 |
case M16_OPC_LWPC: |
| 8465 |
gen_ld(ctx, OPC_LWPC, rx, 0, offset); |
|
| 8473 |
gen_ld(env, ctx, OPC_LWPC, rx, 0, offset);
|
|
| 8466 | 8474 |
break; |
| 8467 | 8475 |
#if defined(TARGET_MIPS64) |
| 8468 | 8476 |
case M16_OPC_LWU: |
| 8469 |
gen_ld(ctx, OPC_LWU, ry, rx, offset); |
|
| 8477 |
gen_ld(env, ctx, OPC_LWU, ry, rx, offset);
|
|
| 8470 | 8478 |
break; |
| 8471 | 8479 |
#endif |
| 8472 | 8480 |
case M16_OPC_SB: |
| ... | ... | |
| 8572 | 8580 |
#if defined(TARGET_MIPS64) |
| 8573 | 8581 |
case M16_OPC_LD: |
| 8574 | 8582 |
check_mips_64(ctx); |
| 8575 |
gen_ld(ctx, OPC_LD, ry, rx, offset << 3); |
|
| 8583 |
gen_ld(env, ctx, OPC_LD, ry, rx, offset << 3);
|
|
| 8576 | 8584 |
break; |
| 8577 | 8585 |
#endif |
| 8578 | 8586 |
case M16_OPC_RRIA: |
| ... | ... | |
| 8695 | 8703 |
break; |
| 8696 | 8704 |
#endif |
| 8697 | 8705 |
case M16_OPC_LB: |
| 8698 |
gen_ld(ctx, OPC_LB, ry, rx, offset); |
|
| 8706 |
gen_ld(env, ctx, OPC_LB, ry, rx, offset);
|
|
| 8699 | 8707 |
break; |
| 8700 | 8708 |
case M16_OPC_LH: |
| 8701 |
gen_ld(ctx, OPC_LH, ry, rx, offset << 1); |
|
| 8709 |
gen_ld(env, ctx, OPC_LH, ry, rx, offset << 1);
|
|
| 8702 | 8710 |
break; |
| 8703 | 8711 |
case M16_OPC_LWSP: |
| 8704 |
gen_ld(ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2); |
|
| 8712 |
gen_ld(env, ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2);
|
|
| 8705 | 8713 |
break; |
| 8706 | 8714 |
case M16_OPC_LW: |
| 8707 |
gen_ld(ctx, OPC_LW, ry, rx, offset << 2); |
|
| 8715 |
gen_ld(env, ctx, OPC_LW, ry, rx, offset << 2);
|
|
| 8708 | 8716 |
break; |
| 8709 | 8717 |
case M16_OPC_LBU: |
| 8710 |
gen_ld(ctx, OPC_LBU, ry, rx, offset); |
|
| 8718 |
gen_ld(env, ctx, OPC_LBU, ry, rx, offset);
|
|
| 8711 | 8719 |
break; |
| 8712 | 8720 |
case M16_OPC_LHU: |
| 8713 |
gen_ld(ctx, OPC_LHU, ry, rx, offset << 1); |
|
| 8721 |
gen_ld(env, ctx, OPC_LHU, ry, rx, offset << 1);
|
|
| 8714 | 8722 |
break; |
| 8715 | 8723 |
case M16_OPC_LWPC: |
| 8716 |
gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2); |
|
| 8724 |
gen_ld(env, ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2);
|
|
| 8717 | 8725 |
break; |
| 8718 | 8726 |
#if defined (TARGET_MIPS64) |
| 8719 | 8727 |
case M16_OPC_LWU: |
| 8720 | 8728 |
check_mips_64(ctx); |
| 8721 |
gen_ld(ctx, OPC_LWU, ry, rx, offset << 2); |
|
| 8729 |
gen_ld(env, ctx, OPC_LWU, ry, rx, offset << 2);
|
|
| 8722 | 8730 |
break; |
| 8723 | 8731 |
#endif |
| 8724 | 8732 |
case M16_OPC_SB: |
| ... | ... | |
| 10846 | 10854 |
mips32_op = OPC_LL; |
| 10847 | 10855 |
goto do_ld_lr; |
| 10848 | 10856 |
do_ld_lr: |
| 10849 |
gen_ld(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); |
|
| 10857 |
gen_ld(env, ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12));
|
|
| 10850 | 10858 |
break; |
| 10851 | 10859 |
do_st_lr: |
| 10852 | 10860 |
gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); |
| ... | ... | |
| 10984 | 10992 |
mips32_op = OPC_SW; |
| 10985 | 10993 |
goto do_st; |
| 10986 | 10994 |
do_ld: |
| 10987 |
gen_ld(ctx, mips32_op, rt, rs, imm); |
|
| 10995 |
gen_ld(env, ctx, mips32_op, rt, rs, imm);
|
|
| 10988 | 10996 |
break; |
| 10989 | 10997 |
do_st: |
| 10990 | 10998 |
gen_st(ctx, mips32_op, rt, rs, imm); |
| ... | ... | |
| 11137 | 11145 |
int rb = 28; /* GP */ |
| 11138 | 11146 |
int16_t offset = SIMM(ctx->opcode, 0, 7) << 2; |
| 11139 | 11147 |
|
| 11140 |
gen_ld(ctx, OPC_LW, rd, rb, offset); |
|
| 11148 |
gen_ld(env, ctx, OPC_LW, rd, rb, offset);
|
|
| 11141 | 11149 |
} |
| 11142 | 11150 |
break; |
| 11143 | 11151 |
case POOL16F: |
| ... | ... | |
| 11169 | 11177 |
int16_t offset = ZIMM(ctx->opcode, 0, 4); |
| 11170 | 11178 |
offset = (offset == 0xf ? -1 : offset); |
| 11171 | 11179 |
|
| 11172 |
gen_ld(ctx, OPC_LBU, rd, rb, offset); |
|
| 11180 |
gen_ld(env, ctx, OPC_LBU, rd, rb, offset);
|
|
| 11173 | 11181 |
} |
| 11174 | 11182 |
break; |
| 11175 | 11183 |
case LHU16: |
| ... | ... | |
| 11178 | 11186 |
int rb = mmreg(uMIPS_RS(ctx->opcode)); |
| 11179 | 11187 |
int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1; |
| 11180 | 11188 |
|
| 11181 |
gen_ld(ctx, OPC_LHU, rd, rb, offset); |
|
| 11189 |
gen_ld(env, ctx, OPC_LHU, rd, rb, offset);
|
|
| 11182 | 11190 |
} |
| 11183 | 11191 |
break; |
| 11184 | 11192 |
case LWSP16: |
| ... | ... | |
| 11187 | 11195 |
int rb = 29; /* SP */ |
| 11188 | 11196 |
int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2; |
| 11189 | 11197 |
|
| 11190 |
gen_ld(ctx, OPC_LW, rd, rb, offset); |
|
| 11198 |
gen_ld(env, ctx, OPC_LW, rd, rb, offset);
|
|
| 11191 | 11199 |
} |
| 11192 | 11200 |
break; |
| 11193 | 11201 |
case LW16: |
| ... | ... | |
| 11196 | 11204 |
int rb = mmreg(uMIPS_RS(ctx->opcode)); |
| 11197 | 11205 |
int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2; |
| 11198 | 11206 |
|
| 11199 |
gen_ld(ctx, OPC_LW, rd, rb, offset); |
|
| 11207 |
gen_ld(env, ctx, OPC_LW, rd, rb, offset);
|
|
| 11200 | 11208 |
} |
| 11201 | 11209 |
break; |
| 11202 | 11210 |
case SB16: |
| ... | ... | |
| 11798 | 11806 |
break; |
| 11799 | 11807 |
case OPC_LB ... OPC_LWR: /* Load and stores */ |
| 11800 | 11808 |
case OPC_LL: |
| 11801 |
gen_ld(ctx, op, rt, rs, imm); |
|
| 11809 |
gen_ld(env, ctx, op, rt, rs, imm);
|
|
| 11802 | 11810 |
break; |
| 11803 | 11811 |
case OPC_SB ... OPC_SW: |
| 11804 | 11812 |
case OPC_SWR: |
| ... | ... | |
| 11932 | 11940 |
case OPC_LD: |
| 11933 | 11941 |
check_insn(env, ctx, ISA_MIPS3); |
| 11934 | 11942 |
check_mips_64(ctx); |
| 11935 |
gen_ld(ctx, op, rt, rs, imm); |
|
| 11943 |
gen_ld(env, ctx, op, rt, rs, imm);
|
|
| 11936 | 11944 |
break; |
| 11937 | 11945 |
case OPC_SDL ... OPC_SDR: |
| 11938 | 11946 |
case OPC_SD: |
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