Revision afcb7375
| b/target-sparc/helper.h | ||
|---|---|---|
| 148 | 148 |
VIS_HELPER(padd); |
| 149 | 149 |
VIS_HELPER(psub); |
| 150 | 150 |
#define VIS_CMPHELPER(name) \ |
| 151 |
F_HELPER_0_0(name##16); \
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|
| 152 |
F_HELPER_0_0(name##32)
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|
| 151 |
DEF_HELPER_0(f##name##16, i64); \
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| 152 |
DEF_HELPER_0(f##name##32, i64)
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|
| 153 | 153 |
VIS_CMPHELPER(cmpgt); |
| 154 | 154 |
VIS_CMPHELPER(cmpeq); |
| 155 | 155 |
VIS_CMPHELPER(cmple); |
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 525 | 525 |
uint16_t w[4]; |
| 526 | 526 |
int16_t sw[4]; |
| 527 | 527 |
uint32_t l[2]; |
| 528 |
uint64_t ll; |
|
| 528 | 529 |
float64 d; |
| 529 | 530 |
} vis64; |
| 530 | 531 |
|
| ... | ... | |
| 789 | 790 |
VIS_HELPER(helper_fpsub, FSUB) |
| 790 | 791 |
|
| 791 | 792 |
#define VIS_CMPHELPER(name, F) \ |
| 792 |
void name##16(void) \
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| 793 |
uint64_t name##16(void) \
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|
| 793 | 794 |
{ \
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| 794 | 795 |
vis64 s, d; \ |
| 795 | 796 |
\ |
| 796 | 797 |
s.d = DT0; \ |
| 797 | 798 |
d.d = DT1; \ |
| 798 | 799 |
\ |
| 799 |
d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \ |
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| 800 |
d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \ |
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| 801 |
d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \ |
|
| 802 |
d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \ |
|
| 800 |
d.VIS_W64(0) = F(s.VIS_W64(0), d.VIS_W64(0)) ? 1 : 0; \ |
|
| 801 |
d.VIS_W64(0) |= F(s.VIS_W64(1), d.VIS_W64(1)) ? 2 : 0; \ |
|
| 802 |
d.VIS_W64(0) |= F(s.VIS_W64(2), d.VIS_W64(2)) ? 4 : 0; \ |
|
| 803 |
d.VIS_W64(0) |= F(s.VIS_W64(3), d.VIS_W64(3)) ? 8 : 0; \ |
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| 804 |
d.VIS_W64(1) = d.VIS_W64(2) = d.VIS_W64(3) = 0; \ |
|
| 803 | 805 |
\ |
| 804 |
DT0 = d.d; \
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| 806 |
return d.ll; \
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| 805 | 807 |
} \ |
| 806 | 808 |
\ |
| 807 |
void name##32(void) \
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| 809 |
uint64_t name##32(void) \
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| 808 | 810 |
{ \
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| 809 | 811 |
vis64 s, d; \ |
| 810 | 812 |
\ |
| 811 | 813 |
s.d = DT0; \ |
| 812 | 814 |
d.d = DT1; \ |
| 813 | 815 |
\ |
| 814 |
d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \ |
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| 815 |
d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \ |
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| 816 |
d.VIS_L64(0) = F(s.VIS_L64(0), d.VIS_L64(0)) ? 1 : 0; \ |
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| 817 |
d.VIS_L64(0) |= F(s.VIS_L64(1), d.VIS_L64(1)) ? 2 : 0; \ |
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| 818 |
d.VIS_L64(1) = 0; \ |
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| 816 | 819 |
\ |
| 817 |
DT0 = d.d; \
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| 820 |
return d.ll; \
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| 818 | 821 |
} |
| 819 | 822 |
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| 820 | 823 |
#define FCMPGT(a, b) ((a) > (b)) |
| b/target-sparc/translate.c | ||
|---|---|---|
| 3789 | 3789 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3790 | 3790 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3791 | 3791 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3792 |
gen_helper_fcmple16(); |
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| 3793 |
gen_op_store_DT0_fpr(DFPREG(rd));
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|
| 3792 |
gen_helper_fcmple16(cpu_dst);
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| 3793 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3794 | 3794 |
break; |
| 3795 | 3795 |
case 0x022: /* VIS I fcmpne16 */ |
| 3796 | 3796 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3797 | 3797 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3798 | 3798 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3799 |
gen_helper_fcmpne16(); |
|
| 3800 |
gen_op_store_DT0_fpr(DFPREG(rd));
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|
| 3799 |
gen_helper_fcmpne16(cpu_dst);
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|
| 3800 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3801 | 3801 |
break; |
| 3802 | 3802 |
case 0x024: /* VIS I fcmple32 */ |
| 3803 | 3803 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3804 | 3804 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3805 | 3805 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3806 |
gen_helper_fcmple32(); |
|
| 3807 |
gen_op_store_DT0_fpr(DFPREG(rd));
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|
| 3806 |
gen_helper_fcmple32(cpu_dst);
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|
| 3807 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3808 | 3808 |
break; |
| 3809 | 3809 |
case 0x026: /* VIS I fcmpne32 */ |
| 3810 | 3810 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3811 | 3811 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3812 | 3812 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3813 |
gen_helper_fcmpne32(); |
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| 3814 |
gen_op_store_DT0_fpr(DFPREG(rd));
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| 3813 |
gen_helper_fcmpne32(cpu_dst);
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| 3814 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3815 | 3815 |
break; |
| 3816 | 3816 |
case 0x028: /* VIS I fcmpgt16 */ |
| 3817 | 3817 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3818 | 3818 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3819 | 3819 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3820 |
gen_helper_fcmpgt16(); |
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| 3821 |
gen_op_store_DT0_fpr(DFPREG(rd));
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| 3820 |
gen_helper_fcmpgt16(cpu_dst);
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| 3821 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3822 | 3822 |
break; |
| 3823 | 3823 |
case 0x02a: /* VIS I fcmpeq16 */ |
| 3824 | 3824 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3825 | 3825 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3826 | 3826 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3827 |
gen_helper_fcmpeq16(); |
|
| 3828 |
gen_op_store_DT0_fpr(DFPREG(rd));
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|
| 3827 |
gen_helper_fcmpeq16(cpu_dst);
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| 3828 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3829 | 3829 |
break; |
| 3830 | 3830 |
case 0x02c: /* VIS I fcmpgt32 */ |
| 3831 | 3831 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3832 | 3832 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3833 | 3833 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3834 |
gen_helper_fcmpgt32(); |
|
| 3835 |
gen_op_store_DT0_fpr(DFPREG(rd));
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|
| 3834 |
gen_helper_fcmpgt32(cpu_dst);
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|
| 3835 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3836 | 3836 |
break; |
| 3837 | 3837 |
case 0x02e: /* VIS I fcmpeq32 */ |
| 3838 | 3838 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3839 | 3839 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 3840 | 3840 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3841 |
gen_helper_fcmpeq32(); |
|
| 3842 |
gen_op_store_DT0_fpr(DFPREG(rd));
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|
| 3841 |
gen_helper_fcmpeq32(cpu_dst);
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|
| 3842 |
gen_movl_TN_reg(rd, cpu_dst);
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|
| 3843 | 3843 |
break; |
| 3844 | 3844 |
case 0x031: /* VIS I fmul8x16 */ |
| 3845 | 3845 |
CHECK_FPU_FEATURE(dc, VIS1); |
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