Revision afcb7375 target-sparc/translate.c
b/target-sparc/translate.c | ||
---|---|---|
3789 | 3789 |
CHECK_FPU_FEATURE(dc, VIS1); |
3790 | 3790 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3791 | 3791 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3792 |
gen_helper_fcmple16(); |
|
3793 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3792 |
gen_helper_fcmple16(cpu_dst);
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|
3793 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3794 | 3794 |
break; |
3795 | 3795 |
case 0x022: /* VIS I fcmpne16 */ |
3796 | 3796 |
CHECK_FPU_FEATURE(dc, VIS1); |
3797 | 3797 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3798 | 3798 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3799 |
gen_helper_fcmpne16(); |
|
3800 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3799 |
gen_helper_fcmpne16(cpu_dst);
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|
3800 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3801 | 3801 |
break; |
3802 | 3802 |
case 0x024: /* VIS I fcmple32 */ |
3803 | 3803 |
CHECK_FPU_FEATURE(dc, VIS1); |
3804 | 3804 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3805 | 3805 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3806 |
gen_helper_fcmple32(); |
|
3807 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3806 |
gen_helper_fcmple32(cpu_dst);
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|
3807 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3808 | 3808 |
break; |
3809 | 3809 |
case 0x026: /* VIS I fcmpne32 */ |
3810 | 3810 |
CHECK_FPU_FEATURE(dc, VIS1); |
3811 | 3811 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3812 | 3812 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3813 |
gen_helper_fcmpne32(); |
|
3814 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3813 |
gen_helper_fcmpne32(cpu_dst);
|
|
3814 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3815 | 3815 |
break; |
3816 | 3816 |
case 0x028: /* VIS I fcmpgt16 */ |
3817 | 3817 |
CHECK_FPU_FEATURE(dc, VIS1); |
3818 | 3818 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3819 | 3819 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3820 |
gen_helper_fcmpgt16(); |
|
3821 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3820 |
gen_helper_fcmpgt16(cpu_dst);
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|
3821 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3822 | 3822 |
break; |
3823 | 3823 |
case 0x02a: /* VIS I fcmpeq16 */ |
3824 | 3824 |
CHECK_FPU_FEATURE(dc, VIS1); |
3825 | 3825 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3826 | 3826 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3827 |
gen_helper_fcmpeq16(); |
|
3828 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3827 |
gen_helper_fcmpeq16(cpu_dst);
|
|
3828 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3829 | 3829 |
break; |
3830 | 3830 |
case 0x02c: /* VIS I fcmpgt32 */ |
3831 | 3831 |
CHECK_FPU_FEATURE(dc, VIS1); |
3832 | 3832 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3833 | 3833 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3834 |
gen_helper_fcmpgt32(); |
|
3835 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3834 |
gen_helper_fcmpgt32(cpu_dst);
|
|
3835 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3836 | 3836 |
break; |
3837 | 3837 |
case 0x02e: /* VIS I fcmpeq32 */ |
3838 | 3838 |
CHECK_FPU_FEATURE(dc, VIS1); |
3839 | 3839 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
3840 | 3840 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
3841 |
gen_helper_fcmpeq32(); |
|
3842 |
gen_op_store_DT0_fpr(DFPREG(rd));
|
|
3841 |
gen_helper_fcmpeq32(cpu_dst);
|
|
3842 |
gen_movl_TN_reg(rd, cpu_dst);
|
|
3843 | 3843 |
break; |
3844 | 3844 |
case 0x031: /* VIS I fmul8x16 */ |
3845 | 3845 |
CHECK_FPU_FEATURE(dc, VIS1); |
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