root / target-sparc / op_helper.c @ afcb7375
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#include "exec.h" |
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#include "host-utils.h" |
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#include "helper.h" |
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#include "sysemu.h" |
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|
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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//#define DEBUG_UNALIGNED
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//#define DEBUG_UNASSIGNED
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//#define DEBUG_ASI
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//#define DEBUG_PCALL
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//#define DEBUG_PSTATE
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//#define DEBUG_CACHE_CONTROL
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|
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, ...) \
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do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF_MMU(fmt, ...) do {} while (0) |
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#endif
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|
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#ifdef DEBUG_MXCC
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#define DPRINTF_MXCC(fmt, ...) \
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do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF_MXCC(fmt, ...) do {} while (0) |
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#endif
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|
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#ifdef DEBUG_ASI
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#define DPRINTF_ASI(fmt, ...) \
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do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) |
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#endif
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|
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#ifdef DEBUG_PSTATE
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#define DPRINTF_PSTATE(fmt, ...) \
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do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF_PSTATE(fmt, ...) do {} while (0) |
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#endif
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|
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#ifdef DEBUG_CACHE_CONTROL
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#define DPRINTF_CACHE_CONTROL(fmt, ...) \
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do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) |
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#endif
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|
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#ifdef TARGET_SPARC64
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#ifndef TARGET_ABI32
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#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
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#else
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#define AM_CHECK(env1) (1) |
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#endif
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#endif
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|
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#define DT0 (env->dt0)
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#define DT1 (env->dt1)
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#define QT0 (env->qt0)
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#define QT1 (env->qt1)
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|
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/* Leon3 cache control */
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|
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/* Cache control: emulate the behavior of cache control registers but without
|
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any effect on the emulated */
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|
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#define CACHE_STATE_MASK 0x3 |
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#define CACHE_DISABLED 0x0 |
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#define CACHE_FROZEN 0x1 |
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#define CACHE_ENABLED 0x3 |
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|
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/* Cache Control register fields */
|
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|
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#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ |
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#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ |
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#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ |
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#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ |
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#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ |
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#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ |
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#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ |
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#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ |
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|
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#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
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static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
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int is_asi, int size); |
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#endif
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|
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#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
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// Calculates TSB pointer value for fault page size 8k or 64k
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static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
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uint64_t tag_access_register, |
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int page_size)
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{ |
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uint64_t tsb_base = tsb_register & ~0x1fffULL;
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int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; |
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int tsb_size = tsb_register & 0xf; |
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|
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// discard lower 13 bits which hold tag access context
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uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
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|
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// now reorder bits
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uint64_t tsb_base_mask = ~0x1fffULL;
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uint64_t va = tag_access_va; |
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// move va bits to correct position
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if (page_size == 8*1024) { |
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va >>= 9;
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} else if (page_size == 64*1024) { |
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va >>= 12;
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} |
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if (tsb_size) {
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tsb_base_mask <<= tsb_size; |
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} |
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// calculate tsb_base mask and adjust va if split is in use
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if (tsb_split) {
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if (page_size == 8*1024) { |
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va &= ~(1ULL << (13 + tsb_size)); |
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} else if (page_size == 64*1024) { |
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va |= (1ULL << (13 + tsb_size)); |
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} |
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tsb_base_mask <<= 1;
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} |
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return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; |
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} |
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// Calculates tag target register value by reordering bits
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// in tag access register
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static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
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{ |
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return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); |
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} |
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|
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static void replace_tlb_entry(SparcTLBEntry *tlb, |
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uint64_t tlb_tag, uint64_t tlb_tte, |
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CPUState *env1) |
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{ |
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target_ulong mask, size, va, offset; |
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|
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// flush page range if translation is valid
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if (TTE_IS_VALID(tlb->tte)) {
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mask = 0xffffffffffffe000ULL;
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mask <<= 3 * ((tlb->tte >> 61) & 3); |
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size = ~mask + 1;
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va = tlb->tag & mask; |
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for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { |
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tlb_flush_page(env1, va + offset); |
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} |
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} |
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|
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tlb->tag = tlb_tag; |
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tlb->tte = tlb_tte; |
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} |
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|
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static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, |
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const char* strmmu, CPUState *env1) |
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{ |
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unsigned int i; |
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target_ulong mask; |
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uint64_t context; |
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|
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int is_demap_context = (demap_addr >> 6) & 1; |
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|
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// demap context
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switch ((demap_addr >> 4) & 3) { |
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case 0: // primary |
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context = env1->dmmu.mmu_primary_context; |
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break;
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case 1: // secondary |
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context = env1->dmmu.mmu_secondary_context; |
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break;
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case 2: // nucleus |
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context = 0;
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break;
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case 3: // reserved |
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default:
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return;
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} |
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|
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for (i = 0; i < 64; i++) { |
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if (TTE_IS_VALID(tlb[i].tte)) {
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|
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if (is_demap_context) {
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// will remove non-global entries matching context value
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if (TTE_IS_GLOBAL(tlb[i].tte) ||
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!tlb_compare_context(&tlb[i], context)) { |
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continue;
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} |
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} else {
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// demap page
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// will remove any entry matching VA
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mask = 0xffffffffffffe000ULL;
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mask <<= 3 * ((tlb[i].tte >> 61) & 3); |
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if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
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continue;
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} |
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// entry should be global or matching context value
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if (!TTE_IS_GLOBAL(tlb[i].tte) &&
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!tlb_compare_context(&tlb[i], context)) { |
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continue;
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} |
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} |
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|
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replace_tlb_entry(&tlb[i], 0, 0, env1); |
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#ifdef DEBUG_MMU
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DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
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dump_mmu(stdout, fprintf, env1); |
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#endif
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} |
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} |
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} |
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|
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static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, |
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uint64_t tlb_tag, uint64_t tlb_tte, |
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const char* strmmu, CPUState *env1) |
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{ |
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unsigned int i, replace_used; |
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|
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// Try replacing invalid entry
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for (i = 0; i < 64; i++) { |
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if (!TTE_IS_VALID(tlb[i].tte)) {
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replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
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#ifdef DEBUG_MMU
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DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
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dump_mmu(stdout, fprintf, env1); |
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#endif
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return;
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} |
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} |
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|
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// All entries are valid, try replacing unlocked entry
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|
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for (replace_used = 0; replace_used < 2; ++replace_used) { |
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|
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// Used entries are not replaced on first pass
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|
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for (i = 0; i < 64; i++) { |
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if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
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replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
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#ifdef DEBUG_MMU
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DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
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strmmu, (replace_used?"used":"unused"), i); |
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dump_mmu(stdout, fprintf, env1); |
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#endif
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return;
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} |
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} |
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|
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// Now reset used bit and search for unused entries again
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|
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for (i = 0; i < 64; i++) { |
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TTE_SET_UNUSED(tlb[i].tte); |
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} |
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} |
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|
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#ifdef DEBUG_MMU
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DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
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#endif
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// error state?
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} |
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|
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#endif
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static inline target_ulong address_mask(CPUState *env1, target_ulong addr) |
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{ |
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#ifdef TARGET_SPARC64
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if (AM_CHECK(env1))
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addr &= 0xffffffffULL;
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#endif
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return addr;
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} |
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/* returns true if access using this ASI is to have address translated by MMU
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otherwise access is to raw physical address */
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static inline int is_translating_asi(int asi) |
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{ |
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#ifdef TARGET_SPARC64
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/* Ultrasparc IIi translating asi
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- note this list is defined by cpu implementation
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*/
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switch (asi) {
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case 0x04 ... 0x11: |
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case 0x18 ... 0x19: |
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case 0x24 ... 0x2C: |
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case 0x70 ... 0x73: |
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case 0x78 ... 0x79: |
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case 0x80 ... 0xFF: |
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return 1; |
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|
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default:
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return 0; |
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} |
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#else
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/* TODO: check sparc32 bits */
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return 0; |
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#endif
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} |
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|
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static inline target_ulong asi_address_mask(CPUState *env1, |
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int asi, target_ulong addr)
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{ |
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if (is_translating_asi(asi)) {
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return address_mask(env, addr);
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} else {
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return addr;
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} |
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} |
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|
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static void raise_exception(int tt) |
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{ |
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env->exception_index = tt; |
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cpu_loop_exit(env); |
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} |
321 |
|
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void HELPER(raise_exception)(int tt) |
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{ |
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raise_exception(tt); |
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} |
326 |
|
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void helper_shutdown(void) |
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{ |
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#if !defined(CONFIG_USER_ONLY)
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qemu_system_shutdown_request(); |
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#endif
|
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} |
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|
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void helper_check_align(target_ulong addr, uint32_t align)
|
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{ |
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if (addr & align) {
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#ifdef DEBUG_UNALIGNED
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printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
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"\n", addr, env->pc);
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#endif
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raise_exception(TT_UNALIGNED); |
342 |
} |
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} |
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|
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#define F_HELPER(name, p) void helper_f##name##p(void) |
346 |
|
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#define F_BINOP(name) \
|
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float32 helper_f ## name ## s (float32 src1, float32 src2) \ |
349 |
{ \ |
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return float32_ ## name (src1, src2, &env->fp_status); \ |
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} \ |
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F_HELPER(name, d) \ |
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{ \ |
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DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \ |
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} \ |
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F_HELPER(name, q) \ |
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{ \ |
358 |
QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \ |
359 |
} |
360 |
|
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F_BINOP(add); |
362 |
F_BINOP(sub); |
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F_BINOP(mul); |
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F_BINOP(div); |
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#undef F_BINOP
|
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|
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void helper_fsmuld(float32 src1, float32 src2)
|
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{ |
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DT0 = float64_mul(float32_to_float64(src1, &env->fp_status), |
370 |
float32_to_float64(src2, &env->fp_status), |
371 |
&env->fp_status); |
372 |
} |
373 |
|
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void helper_fdmulq(void) |
375 |
{ |
376 |
QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status), |
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float64_to_float128(DT1, &env->fp_status), |
378 |
&env->fp_status); |
379 |
} |
380 |
|
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float32 helper_fnegs(float32 src) |
382 |
{ |
383 |
return float32_chs(src);
|
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} |
385 |
|
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#ifdef TARGET_SPARC64
|
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F_HELPER(neg, d) |
388 |
{ |
389 |
DT0 = float64_chs(DT1); |
390 |
} |
391 |
|
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F_HELPER(neg, q) |
393 |
{ |
394 |
QT0 = float128_chs(QT1); |
395 |
} |
396 |
#endif
|
397 |
|
398 |
/* Integer to float conversion. */
|
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float32 helper_fitos(int32_t src) |
400 |
{ |
401 |
return int32_to_float32(src, &env->fp_status);
|
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} |
403 |
|
404 |
void helper_fitod(int32_t src)
|
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{ |
406 |
DT0 = int32_to_float64(src, &env->fp_status); |
407 |
} |
408 |
|
409 |
void helper_fitoq(int32_t src)
|
410 |
{ |
411 |
QT0 = int32_to_float128(src, &env->fp_status); |
412 |
} |
413 |
|
414 |
#ifdef TARGET_SPARC64
|
415 |
float32 helper_fxtos(void)
|
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{ |
417 |
return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
|
418 |
} |
419 |
|
420 |
F_HELPER(xto, d) |
421 |
{ |
422 |
DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
423 |
} |
424 |
|
425 |
F_HELPER(xto, q) |
426 |
{ |
427 |
QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status); |
428 |
} |
429 |
#endif
|
430 |
#undef F_HELPER
|
431 |
|
432 |
/* floating point conversion */
|
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float32 helper_fdtos(void)
|
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{ |
435 |
return float64_to_float32(DT1, &env->fp_status);
|
436 |
} |
437 |
|
438 |
void helper_fstod(float32 src)
|
439 |
{ |
440 |
DT0 = float32_to_float64(src, &env->fp_status); |
441 |
} |
442 |
|
443 |
float32 helper_fqtos(void)
|
444 |
{ |
445 |
return float128_to_float32(QT1, &env->fp_status);
|
446 |
} |
447 |
|
448 |
void helper_fstoq(float32 src)
|
449 |
{ |
450 |
QT0 = float32_to_float128(src, &env->fp_status); |
451 |
} |
452 |
|
453 |
void helper_fqtod(void) |
454 |
{ |
455 |
DT0 = float128_to_float64(QT1, &env->fp_status); |
456 |
} |
457 |
|
458 |
void helper_fdtoq(void) |
459 |
{ |
460 |
QT0 = float64_to_float128(DT1, &env->fp_status); |
461 |
} |
462 |
|
463 |
/* Float to integer conversion. */
|
464 |
int32_t helper_fstoi(float32 src) |
465 |
{ |
466 |
return float32_to_int32_round_to_zero(src, &env->fp_status);
|
467 |
} |
468 |
|
469 |
int32_t helper_fdtoi(void)
|
470 |
{ |
471 |
return float64_to_int32_round_to_zero(DT1, &env->fp_status);
|
472 |
} |
473 |
|
474 |
int32_t helper_fqtoi(void)
|
475 |
{ |
476 |
return float128_to_int32_round_to_zero(QT1, &env->fp_status);
|
477 |
} |
478 |
|
479 |
#ifdef TARGET_SPARC64
|
480 |
void helper_fstox(float32 src)
|
481 |
{ |
482 |
*((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status); |
483 |
} |
484 |
|
485 |
void helper_fdtox(void) |
486 |
{ |
487 |
*((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status); |
488 |
} |
489 |
|
490 |
void helper_fqtox(void) |
491 |
{ |
492 |
*((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status); |
493 |
} |
494 |
|
495 |
void helper_faligndata(void) |
496 |
{ |
497 |
uint64_t tmp; |
498 |
|
499 |
tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8); |
500 |
/* on many architectures a shift of 64 does nothing */
|
501 |
if ((env->gsr & 7) != 0) { |
502 |
tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8); |
503 |
} |
504 |
*((uint64_t *)&DT0) = tmp; |
505 |
} |
506 |
|
507 |
#ifdef HOST_WORDS_BIGENDIAN
|
508 |
#define VIS_B64(n) b[7 - (n)] |
509 |
#define VIS_W64(n) w[3 - (n)] |
510 |
#define VIS_SW64(n) sw[3 - (n)] |
511 |
#define VIS_L64(n) l[1 - (n)] |
512 |
#define VIS_B32(n) b[3 - (n)] |
513 |
#define VIS_W32(n) w[1 - (n)] |
514 |
#else
|
515 |
#define VIS_B64(n) b[n]
|
516 |
#define VIS_W64(n) w[n]
|
517 |
#define VIS_SW64(n) sw[n]
|
518 |
#define VIS_L64(n) l[n]
|
519 |
#define VIS_B32(n) b[n]
|
520 |
#define VIS_W32(n) w[n]
|
521 |
#endif
|
522 |
|
523 |
typedef union { |
524 |
uint8_t b[8];
|
525 |
uint16_t w[4];
|
526 |
int16_t sw[4];
|
527 |
uint32_t l[2];
|
528 |
uint64_t ll; |
529 |
float64 d; |
530 |
} vis64; |
531 |
|
532 |
typedef union { |
533 |
uint8_t b[4];
|
534 |
uint16_t w[2];
|
535 |
uint32_t l; |
536 |
float32 f; |
537 |
} vis32; |
538 |
|
539 |
void helper_fpmerge(void) |
540 |
{ |
541 |
vis64 s, d; |
542 |
|
543 |
s.d = DT0; |
544 |
d.d = DT1; |
545 |
|
546 |
// Reverse calculation order to handle overlap
|
547 |
d.VIS_B64(7) = s.VIS_B64(3); |
548 |
d.VIS_B64(6) = d.VIS_B64(3); |
549 |
d.VIS_B64(5) = s.VIS_B64(2); |
550 |
d.VIS_B64(4) = d.VIS_B64(2); |
551 |
d.VIS_B64(3) = s.VIS_B64(1); |
552 |
d.VIS_B64(2) = d.VIS_B64(1); |
553 |
d.VIS_B64(1) = s.VIS_B64(0); |
554 |
//d.VIS_B64(0) = d.VIS_B64(0);
|
555 |
|
556 |
DT0 = d.d; |
557 |
} |
558 |
|
559 |
void helper_fmul8x16(void) |
560 |
{ |
561 |
vis64 s, d; |
562 |
uint32_t tmp; |
563 |
|
564 |
s.d = DT0; |
565 |
d.d = DT1; |
566 |
|
567 |
#define PMUL(r) \
|
568 |
tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ |
569 |
if ((tmp & 0xff) > 0x7f) \ |
570 |
tmp += 0x100; \
|
571 |
d.VIS_W64(r) = tmp >> 8;
|
572 |
|
573 |
PMUL(0);
|
574 |
PMUL(1);
|
575 |
PMUL(2);
|
576 |
PMUL(3);
|
577 |
#undef PMUL
|
578 |
|
579 |
DT0 = d.d; |
580 |
} |
581 |
|
582 |
void helper_fmul8x16al(void) |
583 |
{ |
584 |
vis64 s, d; |
585 |
uint32_t tmp; |
586 |
|
587 |
s.d = DT0; |
588 |
d.d = DT1; |
589 |
|
590 |
#define PMUL(r) \
|
591 |
tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
|
592 |
if ((tmp & 0xff) > 0x7f) \ |
593 |
tmp += 0x100; \
|
594 |
d.VIS_W64(r) = tmp >> 8;
|
595 |
|
596 |
PMUL(0);
|
597 |
PMUL(1);
|
598 |
PMUL(2);
|
599 |
PMUL(3);
|
600 |
#undef PMUL
|
601 |
|
602 |
DT0 = d.d; |
603 |
} |
604 |
|
605 |
void helper_fmul8x16au(void) |
606 |
{ |
607 |
vis64 s, d; |
608 |
uint32_t tmp; |
609 |
|
610 |
s.d = DT0; |
611 |
d.d = DT1; |
612 |
|
613 |
#define PMUL(r) \
|
614 |
tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
|
615 |
if ((tmp & 0xff) > 0x7f) \ |
616 |
tmp += 0x100; \
|
617 |
d.VIS_W64(r) = tmp >> 8;
|
618 |
|
619 |
PMUL(0);
|
620 |
PMUL(1);
|
621 |
PMUL(2);
|
622 |
PMUL(3);
|
623 |
#undef PMUL
|
624 |
|
625 |
DT0 = d.d; |
626 |
} |
627 |
|
628 |
void helper_fmul8sux16(void) |
629 |
{ |
630 |
vis64 s, d; |
631 |
uint32_t tmp; |
632 |
|
633 |
s.d = DT0; |
634 |
d.d = DT1; |
635 |
|
636 |
#define PMUL(r) \
|
637 |
tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
638 |
if ((tmp & 0xff) > 0x7f) \ |
639 |
tmp += 0x100; \
|
640 |
d.VIS_W64(r) = tmp >> 8;
|
641 |
|
642 |
PMUL(0);
|
643 |
PMUL(1);
|
644 |
PMUL(2);
|
645 |
PMUL(3);
|
646 |
#undef PMUL
|
647 |
|
648 |
DT0 = d.d; |
649 |
} |
650 |
|
651 |
void helper_fmul8ulx16(void) |
652 |
{ |
653 |
vis64 s, d; |
654 |
uint32_t tmp; |
655 |
|
656 |
s.d = DT0; |
657 |
d.d = DT1; |
658 |
|
659 |
#define PMUL(r) \
|
660 |
tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
661 |
if ((tmp & 0xff) > 0x7f) \ |
662 |
tmp += 0x100; \
|
663 |
d.VIS_W64(r) = tmp >> 8;
|
664 |
|
665 |
PMUL(0);
|
666 |
PMUL(1);
|
667 |
PMUL(2);
|
668 |
PMUL(3);
|
669 |
#undef PMUL
|
670 |
|
671 |
DT0 = d.d; |
672 |
} |
673 |
|
674 |
void helper_fmuld8sux16(void) |
675 |
{ |
676 |
vis64 s, d; |
677 |
uint32_t tmp; |
678 |
|
679 |
s.d = DT0; |
680 |
d.d = DT1; |
681 |
|
682 |
#define PMUL(r) \
|
683 |
tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
684 |
if ((tmp & 0xff) > 0x7f) \ |
685 |
tmp += 0x100; \
|
686 |
d.VIS_L64(r) = tmp; |
687 |
|
688 |
// Reverse calculation order to handle overlap
|
689 |
PMUL(1);
|
690 |
PMUL(0);
|
691 |
#undef PMUL
|
692 |
|
693 |
DT0 = d.d; |
694 |
} |
695 |
|
696 |
void helper_fmuld8ulx16(void) |
697 |
{ |
698 |
vis64 s, d; |
699 |
uint32_t tmp; |
700 |
|
701 |
s.d = DT0; |
702 |
d.d = DT1; |
703 |
|
704 |
#define PMUL(r) \
|
705 |
tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
706 |
if ((tmp & 0xff) > 0x7f) \ |
707 |
tmp += 0x100; \
|
708 |
d.VIS_L64(r) = tmp; |
709 |
|
710 |
// Reverse calculation order to handle overlap
|
711 |
PMUL(1);
|
712 |
PMUL(0);
|
713 |
#undef PMUL
|
714 |
|
715 |
DT0 = d.d; |
716 |
} |
717 |
|
718 |
void helper_fexpand(void) |
719 |
{ |
720 |
vis32 s; |
721 |
vis64 d; |
722 |
|
723 |
s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
|
724 |
d.d = DT1; |
725 |
d.VIS_W64(0) = s.VIS_B32(0) << 4; |
726 |
d.VIS_W64(1) = s.VIS_B32(1) << 4; |
727 |
d.VIS_W64(2) = s.VIS_B32(2) << 4; |
728 |
d.VIS_W64(3) = s.VIS_B32(3) << 4; |
729 |
|
730 |
DT0 = d.d; |
731 |
} |
732 |
|
733 |
#define VIS_HELPER(name, F) \
|
734 |
void name##16(void) \ |
735 |
{ \ |
736 |
vis64 s, d; \ |
737 |
\ |
738 |
s.d = DT0; \ |
739 |
d.d = DT1; \ |
740 |
\ |
741 |
d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ |
742 |
d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ |
743 |
d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ |
744 |
d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ |
745 |
\ |
746 |
DT0 = d.d; \ |
747 |
} \ |
748 |
\ |
749 |
uint32_t name##16s(uint32_t src1, uint32_t src2) \ |
750 |
{ \ |
751 |
vis32 s, d; \ |
752 |
\ |
753 |
s.l = src1; \ |
754 |
d.l = src2; \ |
755 |
\ |
756 |
d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ |
757 |
d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ |
758 |
\ |
759 |
return d.l; \
|
760 |
} \ |
761 |
\ |
762 |
void name##32(void) \ |
763 |
{ \ |
764 |
vis64 s, d; \ |
765 |
\ |
766 |
s.d = DT0; \ |
767 |
d.d = DT1; \ |
768 |
\ |
769 |
d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ |
770 |
d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ |
771 |
\ |
772 |
DT0 = d.d; \ |
773 |
} \ |
774 |
\ |
775 |
uint32_t name##32s(uint32_t src1, uint32_t src2) \ |
776 |
{ \ |
777 |
vis32 s, d; \ |
778 |
\ |
779 |
s.l = src1; \ |
780 |
d.l = src2; \ |
781 |
\ |
782 |
d.l = F(d.l, s.l); \ |
783 |
\ |
784 |
return d.l; \
|
785 |
} |
786 |
|
787 |
#define FADD(a, b) ((a) + (b))
|
788 |
#define FSUB(a, b) ((a) - (b))
|
789 |
VIS_HELPER(helper_fpadd, FADD) |
790 |
VIS_HELPER(helper_fpsub, FSUB) |
791 |
|
792 |
#define VIS_CMPHELPER(name, F) \
|
793 |
uint64_t name##16(void) \ |
794 |
{ \ |
795 |
vis64 s, d; \ |
796 |
\ |
797 |
s.d = DT0; \ |
798 |
d.d = DT1; \ |
799 |
\ |
800 |
d.VIS_W64(0) = F(s.VIS_W64(0), d.VIS_W64(0)) ? 1 : 0; \ |
801 |
d.VIS_W64(0) |= F(s.VIS_W64(1), d.VIS_W64(1)) ? 2 : 0; \ |
802 |
d.VIS_W64(0) |= F(s.VIS_W64(2), d.VIS_W64(2)) ? 4 : 0; \ |
803 |
d.VIS_W64(0) |= F(s.VIS_W64(3), d.VIS_W64(3)) ? 8 : 0; \ |
804 |
d.VIS_W64(1) = d.VIS_W64(2) = d.VIS_W64(3) = 0; \ |
805 |
\ |
806 |
return d.ll; \
|
807 |
} \ |
808 |
\ |
809 |
uint64_t name##32(void) \ |
810 |
{ \ |
811 |
vis64 s, d; \ |
812 |
\ |
813 |
s.d = DT0; \ |
814 |
d.d = DT1; \ |
815 |
\ |
816 |
d.VIS_L64(0) = F(s.VIS_L64(0), d.VIS_L64(0)) ? 1 : 0; \ |
817 |
d.VIS_L64(0) |= F(s.VIS_L64(1), d.VIS_L64(1)) ? 2 : 0; \ |
818 |
d.VIS_L64(1) = 0; \ |
819 |
\ |
820 |
return d.ll; \
|
821 |
} |
822 |
|
823 |
#define FCMPGT(a, b) ((a) > (b))
|
824 |
#define FCMPEQ(a, b) ((a) == (b))
|
825 |
#define FCMPLE(a, b) ((a) <= (b))
|
826 |
#define FCMPNE(a, b) ((a) != (b))
|
827 |
|
828 |
VIS_CMPHELPER(helper_fcmpgt, FCMPGT) |
829 |
VIS_CMPHELPER(helper_fcmpeq, FCMPEQ) |
830 |
VIS_CMPHELPER(helper_fcmple, FCMPLE) |
831 |
VIS_CMPHELPER(helper_fcmpne, FCMPNE) |
832 |
#endif
|
833 |
|
834 |
void helper_check_ieee_exceptions(void) |
835 |
{ |
836 |
target_ulong status; |
837 |
|
838 |
status = get_float_exception_flags(&env->fp_status); |
839 |
if (status) {
|
840 |
/* Copy IEEE 754 flags into FSR */
|
841 |
if (status & float_flag_invalid)
|
842 |
env->fsr |= FSR_NVC; |
843 |
if (status & float_flag_overflow)
|
844 |
env->fsr |= FSR_OFC; |
845 |
if (status & float_flag_underflow)
|
846 |
env->fsr |= FSR_UFC; |
847 |
if (status & float_flag_divbyzero)
|
848 |
env->fsr |= FSR_DZC; |
849 |
if (status & float_flag_inexact)
|
850 |
env->fsr |= FSR_NXC; |
851 |
|
852 |
if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { |
853 |
/* Unmasked exception, generate a trap */
|
854 |
env->fsr |= FSR_FTT_IEEE_EXCP; |
855 |
raise_exception(TT_FP_EXCP); |
856 |
} else {
|
857 |
/* Accumulate exceptions */
|
858 |
env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
|
859 |
} |
860 |
} |
861 |
} |
862 |
|
863 |
void helper_clear_float_exceptions(void) |
864 |
{ |
865 |
set_float_exception_flags(0, &env->fp_status);
|
866 |
} |
867 |
|
868 |
float32 helper_fabss(float32 src) |
869 |
{ |
870 |
return float32_abs(src);
|
871 |
} |
872 |
|
873 |
#ifdef TARGET_SPARC64
|
874 |
void helper_fabsd(void) |
875 |
{ |
876 |
DT0 = float64_abs(DT1); |
877 |
} |
878 |
|
879 |
void helper_fabsq(void) |
880 |
{ |
881 |
QT0 = float128_abs(QT1); |
882 |
} |
883 |
#endif
|
884 |
|
885 |
float32 helper_fsqrts(float32 src) |
886 |
{ |
887 |
return float32_sqrt(src, &env->fp_status);
|
888 |
} |
889 |
|
890 |
void helper_fsqrtd(void) |
891 |
{ |
892 |
DT0 = float64_sqrt(DT1, &env->fp_status); |
893 |
} |
894 |
|
895 |
void helper_fsqrtq(void) |
896 |
{ |
897 |
QT0 = float128_sqrt(QT1, &env->fp_status); |
898 |
} |
899 |
|
900 |
#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
|
901 |
void glue(helper_, name) (void) \ |
902 |
{ \ |
903 |
env->fsr &= FSR_FTT_NMASK; \ |
904 |
if (E && (glue(size, _is_any_nan)(reg1) || \
|
905 |
glue(size, _is_any_nan)(reg2)) && \ |
906 |
(env->fsr & FSR_NVM)) { \ |
907 |
env->fsr |= FSR_NVC; \ |
908 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
909 |
raise_exception(TT_FP_EXCP); \ |
910 |
} \ |
911 |
switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
|
912 |
case float_relation_unordered: \
|
913 |
if ((env->fsr & FSR_NVM)) { \
|
914 |
env->fsr |= FSR_NVC; \ |
915 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
916 |
raise_exception(TT_FP_EXCP); \ |
917 |
} else { \
|
918 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
919 |
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ |
920 |
env->fsr |= FSR_NVA; \ |
921 |
} \ |
922 |
break; \
|
923 |
case float_relation_less: \
|
924 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
925 |
env->fsr |= FSR_FCC0 << FS; \ |
926 |
break; \
|
927 |
case float_relation_greater: \
|
928 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
929 |
env->fsr |= FSR_FCC1 << FS; \ |
930 |
break; \
|
931 |
default: \
|
932 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
933 |
break; \
|
934 |
} \ |
935 |
} |
936 |
#define GEN_FCMPS(name, size, FS, E) \
|
937 |
void glue(helper_, name)(float32 src1, float32 src2) \
|
938 |
{ \ |
939 |
env->fsr &= FSR_FTT_NMASK; \ |
940 |
if (E && (glue(size, _is_any_nan)(src1) || \
|
941 |
glue(size, _is_any_nan)(src2)) && \ |
942 |
(env->fsr & FSR_NVM)) { \ |
943 |
env->fsr |= FSR_NVC; \ |
944 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
945 |
raise_exception(TT_FP_EXCP); \ |
946 |
} \ |
947 |
switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
|
948 |
case float_relation_unordered: \
|
949 |
if ((env->fsr & FSR_NVM)) { \
|
950 |
env->fsr |= FSR_NVC; \ |
951 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
952 |
raise_exception(TT_FP_EXCP); \ |
953 |
} else { \
|
954 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
955 |
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ |
956 |
env->fsr |= FSR_NVA; \ |
957 |
} \ |
958 |
break; \
|
959 |
case float_relation_less: \
|
960 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
961 |
env->fsr |= FSR_FCC0 << FS; \ |
962 |
break; \
|
963 |
case float_relation_greater: \
|
964 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
965 |
env->fsr |= FSR_FCC1 << FS; \ |
966 |
break; \
|
967 |
default: \
|
968 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
969 |
break; \
|
970 |
} \ |
971 |
} |
972 |
|
973 |
GEN_FCMPS(fcmps, float32, 0, 0); |
974 |
GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
975 |
|
976 |
GEN_FCMPS(fcmpes, float32, 0, 1); |
977 |
GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
978 |
|
979 |
GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); |
980 |
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); |
981 |
|
982 |
static uint32_t compute_all_flags(void) |
983 |
{ |
984 |
return env->psr & PSR_ICC;
|
985 |
} |
986 |
|
987 |
static uint32_t compute_C_flags(void) |
988 |
{ |
989 |
return env->psr & PSR_CARRY;
|
990 |
} |
991 |
|
992 |
static inline uint32_t get_NZ_icc(int32_t dst) |
993 |
{ |
994 |
uint32_t ret = 0;
|
995 |
|
996 |
if (dst == 0) { |
997 |
ret = PSR_ZERO; |
998 |
} else if (dst < 0) { |
999 |
ret = PSR_NEG; |
1000 |
} |
1001 |
return ret;
|
1002 |
} |
1003 |
|
1004 |
#ifdef TARGET_SPARC64
|
1005 |
static uint32_t compute_all_flags_xcc(void) |
1006 |
{ |
1007 |
return env->xcc & PSR_ICC;
|
1008 |
} |
1009 |
|
1010 |
static uint32_t compute_C_flags_xcc(void) |
1011 |
{ |
1012 |
return env->xcc & PSR_CARRY;
|
1013 |
} |
1014 |
|
1015 |
static inline uint32_t get_NZ_xcc(target_long dst) |
1016 |
{ |
1017 |
uint32_t ret = 0;
|
1018 |
|
1019 |
if (!dst) {
|
1020 |
ret = PSR_ZERO; |
1021 |
} else if (dst < 0) { |
1022 |
ret = PSR_NEG; |
1023 |
} |
1024 |
return ret;
|
1025 |
} |
1026 |
#endif
|
1027 |
|
1028 |
static inline uint32_t get_V_div_icc(target_ulong src2) |
1029 |
{ |
1030 |
uint32_t ret = 0;
|
1031 |
|
1032 |
if (src2 != 0) { |
1033 |
ret = PSR_OVF; |
1034 |
} |
1035 |
return ret;
|
1036 |
} |
1037 |
|
1038 |
static uint32_t compute_all_div(void) |
1039 |
{ |
1040 |
uint32_t ret; |
1041 |
|
1042 |
ret = get_NZ_icc(CC_DST); |
1043 |
ret |= get_V_div_icc(CC_SRC2); |
1044 |
return ret;
|
1045 |
} |
1046 |
|
1047 |
static uint32_t compute_C_div(void) |
1048 |
{ |
1049 |
return 0; |
1050 |
} |
1051 |
|
1052 |
static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1) |
1053 |
{ |
1054 |
uint32_t ret = 0;
|
1055 |
|
1056 |
if (dst < src1) {
|
1057 |
ret = PSR_CARRY; |
1058 |
} |
1059 |
return ret;
|
1060 |
} |
1061 |
|
1062 |
static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1, |
1063 |
uint32_t src2) |
1064 |
{ |
1065 |
uint32_t ret = 0;
|
1066 |
|
1067 |
if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) { |
1068 |
ret = PSR_CARRY; |
1069 |
} |
1070 |
return ret;
|
1071 |
} |
1072 |
|
1073 |
static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1, |
1074 |
uint32_t src2) |
1075 |
{ |
1076 |
uint32_t ret = 0;
|
1077 |
|
1078 |
if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) { |
1079 |
ret = PSR_OVF; |
1080 |
} |
1081 |
return ret;
|
1082 |
} |
1083 |
|
1084 |
#ifdef TARGET_SPARC64
|
1085 |
static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1) |
1086 |
{ |
1087 |
uint32_t ret = 0;
|
1088 |
|
1089 |
if (dst < src1) {
|
1090 |
ret = PSR_CARRY; |
1091 |
} |
1092 |
return ret;
|
1093 |
} |
1094 |
|
1095 |
static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1, |
1096 |
target_ulong src2) |
1097 |
{ |
1098 |
uint32_t ret = 0;
|
1099 |
|
1100 |
if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) { |
1101 |
ret = PSR_CARRY; |
1102 |
} |
1103 |
return ret;
|
1104 |
} |
1105 |
|
1106 |
static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1, |
1107 |
target_ulong src2) |
1108 |
{ |
1109 |
uint32_t ret = 0;
|
1110 |
|
1111 |
if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) { |
1112 |
ret = PSR_OVF; |
1113 |
} |
1114 |
return ret;
|
1115 |
} |
1116 |
|
1117 |
static uint32_t compute_all_add_xcc(void) |
1118 |
{ |
1119 |
uint32_t ret; |
1120 |
|
1121 |
ret = get_NZ_xcc(CC_DST); |
1122 |
ret |= get_C_add_xcc(CC_DST, CC_SRC); |
1123 |
ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); |
1124 |
return ret;
|
1125 |
} |
1126 |
|
1127 |
static uint32_t compute_C_add_xcc(void) |
1128 |
{ |
1129 |
return get_C_add_xcc(CC_DST, CC_SRC);
|
1130 |
} |
1131 |
#endif
|
1132 |
|
1133 |
static uint32_t compute_all_add(void) |
1134 |
{ |
1135 |
uint32_t ret; |
1136 |
|
1137 |
ret = get_NZ_icc(CC_DST); |
1138 |
ret |= get_C_add_icc(CC_DST, CC_SRC); |
1139 |
ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1140 |
return ret;
|
1141 |
} |
1142 |
|
1143 |
static uint32_t compute_C_add(void) |
1144 |
{ |
1145 |
return get_C_add_icc(CC_DST, CC_SRC);
|
1146 |
} |
1147 |
|
1148 |
#ifdef TARGET_SPARC64
|
1149 |
static uint32_t compute_all_addx_xcc(void) |
1150 |
{ |
1151 |
uint32_t ret; |
1152 |
|
1153 |
ret = get_NZ_xcc(CC_DST); |
1154 |
ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1155 |
ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); |
1156 |
return ret;
|
1157 |
} |
1158 |
|
1159 |
static uint32_t compute_C_addx_xcc(void) |
1160 |
{ |
1161 |
uint32_t ret; |
1162 |
|
1163 |
ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1164 |
return ret;
|
1165 |
} |
1166 |
#endif
|
1167 |
|
1168 |
static uint32_t compute_all_addx(void) |
1169 |
{ |
1170 |
uint32_t ret; |
1171 |
|
1172 |
ret = get_NZ_icc(CC_DST); |
1173 |
ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); |
1174 |
ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1175 |
return ret;
|
1176 |
} |
1177 |
|
1178 |
static uint32_t compute_C_addx(void) |
1179 |
{ |
1180 |
uint32_t ret; |
1181 |
|
1182 |
ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); |
1183 |
return ret;
|
1184 |
} |
1185 |
|
1186 |
static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2) |
1187 |
{ |
1188 |
uint32_t ret = 0;
|
1189 |
|
1190 |
if ((src1 | src2) & 0x3) { |
1191 |
ret = PSR_OVF; |
1192 |
} |
1193 |
return ret;
|
1194 |
} |
1195 |
|
1196 |
static uint32_t compute_all_tadd(void) |
1197 |
{ |
1198 |
uint32_t ret; |
1199 |
|
1200 |
ret = get_NZ_icc(CC_DST); |
1201 |
ret |= get_C_add_icc(CC_DST, CC_SRC); |
1202 |
ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1203 |
ret |= get_V_tag_icc(CC_SRC, CC_SRC2); |
1204 |
return ret;
|
1205 |
} |
1206 |
|
1207 |
static uint32_t compute_all_taddtv(void) |
1208 |
{ |
1209 |
uint32_t ret; |
1210 |
|
1211 |
ret = get_NZ_icc(CC_DST); |
1212 |
ret |= get_C_add_icc(CC_DST, CC_SRC); |
1213 |
return ret;
|
1214 |
} |
1215 |
|
1216 |
static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2) |
1217 |
{ |
1218 |
uint32_t ret = 0;
|
1219 |
|
1220 |
if (src1 < src2) {
|
1221 |
ret = PSR_CARRY; |
1222 |
} |
1223 |
return ret;
|
1224 |
} |
1225 |
|
1226 |
static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1, |
1227 |
uint32_t src2) |
1228 |
{ |
1229 |
uint32_t ret = 0;
|
1230 |
|
1231 |
if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) { |
1232 |
ret = PSR_CARRY; |
1233 |
} |
1234 |
return ret;
|
1235 |
} |
1236 |
|
1237 |
static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1, |
1238 |
uint32_t src2) |
1239 |
{ |
1240 |
uint32_t ret = 0;
|
1241 |
|
1242 |
if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) { |
1243 |
ret = PSR_OVF; |
1244 |
} |
1245 |
return ret;
|
1246 |
} |
1247 |
|
1248 |
|
1249 |
#ifdef TARGET_SPARC64
|
1250 |
static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2) |
1251 |
{ |
1252 |
uint32_t ret = 0;
|
1253 |
|
1254 |
if (src1 < src2) {
|
1255 |
ret = PSR_CARRY; |
1256 |
} |
1257 |
return ret;
|
1258 |
} |
1259 |
|
1260 |
static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1, |
1261 |
target_ulong src2) |
1262 |
{ |
1263 |
uint32_t ret = 0;
|
1264 |
|
1265 |
if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) { |
1266 |
ret = PSR_CARRY; |
1267 |
} |
1268 |
return ret;
|
1269 |
} |
1270 |
|
1271 |
static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1, |
1272 |
target_ulong src2) |
1273 |
{ |
1274 |
uint32_t ret = 0;
|
1275 |
|
1276 |
if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) { |
1277 |
ret = PSR_OVF; |
1278 |
} |
1279 |
return ret;
|
1280 |
} |
1281 |
|
1282 |
static uint32_t compute_all_sub_xcc(void) |
1283 |
{ |
1284 |
uint32_t ret; |
1285 |
|
1286 |
ret = get_NZ_xcc(CC_DST); |
1287 |
ret |= get_C_sub_xcc(CC_SRC, CC_SRC2); |
1288 |
ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
1289 |
return ret;
|
1290 |
} |
1291 |
|
1292 |
static uint32_t compute_C_sub_xcc(void) |
1293 |
{ |
1294 |
return get_C_sub_xcc(CC_SRC, CC_SRC2);
|
1295 |
} |
1296 |
#endif
|
1297 |
|
1298 |
static uint32_t compute_all_sub(void) |
1299 |
{ |
1300 |
uint32_t ret; |
1301 |
|
1302 |
ret = get_NZ_icc(CC_DST); |
1303 |
ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1304 |
ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1305 |
return ret;
|
1306 |
} |
1307 |
|
1308 |
static uint32_t compute_C_sub(void) |
1309 |
{ |
1310 |
return get_C_sub_icc(CC_SRC, CC_SRC2);
|
1311 |
} |
1312 |
|
1313 |
#ifdef TARGET_SPARC64
|
1314 |
static uint32_t compute_all_subx_xcc(void) |
1315 |
{ |
1316 |
uint32_t ret; |
1317 |
|
1318 |
ret = get_NZ_xcc(CC_DST); |
1319 |
ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1320 |
ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
1321 |
return ret;
|
1322 |
} |
1323 |
|
1324 |
static uint32_t compute_C_subx_xcc(void) |
1325 |
{ |
1326 |
uint32_t ret; |
1327 |
|
1328 |
ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1329 |
return ret;
|
1330 |
} |
1331 |
#endif
|
1332 |
|
1333 |
static uint32_t compute_all_subx(void) |
1334 |
{ |
1335 |
uint32_t ret; |
1336 |
|
1337 |
ret = get_NZ_icc(CC_DST); |
1338 |
ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); |
1339 |
ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1340 |
return ret;
|
1341 |
} |
1342 |
|
1343 |
static uint32_t compute_C_subx(void) |
1344 |
{ |
1345 |
uint32_t ret; |
1346 |
|
1347 |
ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); |
1348 |
return ret;
|
1349 |
} |
1350 |
|
1351 |
static uint32_t compute_all_tsub(void) |
1352 |
{ |
1353 |
uint32_t ret; |
1354 |
|
1355 |
ret = get_NZ_icc(CC_DST); |
1356 |
ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1357 |
ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1358 |
ret |= get_V_tag_icc(CC_SRC, CC_SRC2); |
1359 |
return ret;
|
1360 |
} |
1361 |
|
1362 |
static uint32_t compute_all_tsubtv(void) |
1363 |
{ |
1364 |
uint32_t ret; |
1365 |
|
1366 |
ret = get_NZ_icc(CC_DST); |
1367 |
ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1368 |
return ret;
|
1369 |
} |
1370 |
|
1371 |
static uint32_t compute_all_logic(void) |
1372 |
{ |
1373 |
return get_NZ_icc(CC_DST);
|
1374 |
} |
1375 |
|
1376 |
static uint32_t compute_C_logic(void) |
1377 |
{ |
1378 |
return 0; |
1379 |
} |
1380 |
|
1381 |
#ifdef TARGET_SPARC64
|
1382 |
static uint32_t compute_all_logic_xcc(void) |
1383 |
{ |
1384 |
return get_NZ_xcc(CC_DST);
|
1385 |
} |
1386 |
#endif
|
1387 |
|
1388 |
typedef struct CCTable { |
1389 |
uint32_t (*compute_all)(void); /* return all the flags */ |
1390 |
uint32_t (*compute_c)(void); /* return the C flag */ |
1391 |
} CCTable; |
1392 |
|
1393 |
static const CCTable icc_table[CC_OP_NB] = { |
1394 |
/* CC_OP_DYNAMIC should never happen */
|
1395 |
[CC_OP_FLAGS] = { compute_all_flags, compute_C_flags }, |
1396 |
[CC_OP_DIV] = { compute_all_div, compute_C_div }, |
1397 |
[CC_OP_ADD] = { compute_all_add, compute_C_add }, |
1398 |
[CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, |
1399 |
[CC_OP_TADD] = { compute_all_tadd, compute_C_add }, |
1400 |
[CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add }, |
1401 |
[CC_OP_SUB] = { compute_all_sub, compute_C_sub }, |
1402 |
[CC_OP_SUBX] = { compute_all_subx, compute_C_subx }, |
1403 |
[CC_OP_TSUB] = { compute_all_tsub, compute_C_sub }, |
1404 |
[CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub }, |
1405 |
[CC_OP_LOGIC] = { compute_all_logic, compute_C_logic }, |
1406 |
}; |
1407 |
|
1408 |
#ifdef TARGET_SPARC64
|
1409 |
static const CCTable xcc_table[CC_OP_NB] = { |
1410 |
/* CC_OP_DYNAMIC should never happen */
|
1411 |
[CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc }, |
1412 |
[CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic }, |
1413 |
[CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1414 |
[CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, |
1415 |
[CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1416 |
[CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc }, |
1417 |
[CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1418 |
[CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc }, |
1419 |
[CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1420 |
[CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1421 |
[CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic }, |
1422 |
}; |
1423 |
#endif
|
1424 |
|
1425 |
void helper_compute_psr(void) |
1426 |
{ |
1427 |
uint32_t new_psr; |
1428 |
|
1429 |
new_psr = icc_table[CC_OP].compute_all(); |
1430 |
env->psr = new_psr; |
1431 |
#ifdef TARGET_SPARC64
|
1432 |
new_psr = xcc_table[CC_OP].compute_all(); |
1433 |
env->xcc = new_psr; |
1434 |
#endif
|
1435 |
CC_OP = CC_OP_FLAGS; |
1436 |
} |
1437 |
|
1438 |
uint32_t helper_compute_C_icc(void)
|
1439 |
{ |
1440 |
uint32_t ret; |
1441 |
|
1442 |
ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT; |
1443 |
return ret;
|
1444 |
} |
1445 |
|
1446 |
static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
1447 |
{ |
1448 |
dst[0] = src[0]; |
1449 |
dst[1] = src[1]; |
1450 |
dst[2] = src[2]; |
1451 |
dst[3] = src[3]; |
1452 |
dst[4] = src[4]; |
1453 |
dst[5] = src[5]; |
1454 |
dst[6] = src[6]; |
1455 |
dst[7] = src[7]; |
1456 |
} |
1457 |
|
1458 |
static void set_cwp(int new_cwp) |
1459 |
{ |
1460 |
/* put the modified wrap registers at their proper location */
|
1461 |
if (env->cwp == env->nwindows - 1) { |
1462 |
memcpy32(env->regbase, env->regbase + env->nwindows * 16);
|
1463 |
} |
1464 |
env->cwp = new_cwp; |
1465 |
|
1466 |
/* put the wrap registers at their temporary location */
|
1467 |
if (new_cwp == env->nwindows - 1) { |
1468 |
memcpy32(env->regbase + env->nwindows * 16, env->regbase);
|
1469 |
} |
1470 |
env->regwptr = env->regbase + (new_cwp * 16);
|
1471 |
} |
1472 |
|
1473 |
void cpu_set_cwp(CPUState *env1, int new_cwp) |
1474 |
{ |
1475 |
CPUState *saved_env; |
1476 |
|
1477 |
saved_env = env; |
1478 |
env = env1; |
1479 |
set_cwp(new_cwp); |
1480 |
env = saved_env; |
1481 |
} |
1482 |
|
1483 |
static target_ulong get_psr(void) |
1484 |
{ |
1485 |
helper_compute_psr(); |
1486 |
|
1487 |
#if !defined (TARGET_SPARC64)
|
1488 |
return env->version | (env->psr & PSR_ICC) |
|
1489 |
(env->psref? PSR_EF : 0) |
|
1490 |
(env->psrpil << 8) |
|
1491 |
(env->psrs? PSR_S : 0) |
|
1492 |
(env->psrps? PSR_PS : 0) |
|
1493 |
(env->psret? PSR_ET : 0) | env->cwp;
|
1494 |
#else
|
1495 |
return env->psr & PSR_ICC;
|
1496 |
#endif
|
1497 |
} |
1498 |
|
1499 |
target_ulong cpu_get_psr(CPUState *env1) |
1500 |
{ |
1501 |
CPUState *saved_env; |
1502 |
target_ulong ret; |
1503 |
|
1504 |
saved_env = env; |
1505 |
env = env1; |
1506 |
ret = get_psr(); |
1507 |
env = saved_env; |
1508 |
return ret;
|
1509 |
} |
1510 |
|
1511 |
static void put_psr(target_ulong val) |
1512 |
{ |
1513 |
env->psr = val & PSR_ICC; |
1514 |
#if !defined (TARGET_SPARC64)
|
1515 |
env->psref = (val & PSR_EF)? 1 : 0; |
1516 |
env->psrpil = (val & PSR_PIL) >> 8;
|
1517 |
#endif
|
1518 |
#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
|
1519 |
cpu_check_irqs(env); |
1520 |
#endif
|
1521 |
#if !defined (TARGET_SPARC64)
|
1522 |
env->psrs = (val & PSR_S)? 1 : 0; |
1523 |
env->psrps = (val & PSR_PS)? 1 : 0; |
1524 |
env->psret = (val & PSR_ET)? 1 : 0; |
1525 |
set_cwp(val & PSR_CWP); |
1526 |
#endif
|
1527 |
env->cc_op = CC_OP_FLAGS; |
1528 |
} |
1529 |
|
1530 |
void cpu_put_psr(CPUState *env1, target_ulong val)
|
1531 |
{ |
1532 |
CPUState *saved_env; |
1533 |
|
1534 |
saved_env = env; |
1535 |
env = env1; |
1536 |
put_psr(val); |
1537 |
env = saved_env; |
1538 |
} |
1539 |
|
1540 |
static int cwp_inc(int cwp) |
1541 |
{ |
1542 |
if (unlikely(cwp >= env->nwindows)) {
|
1543 |
cwp -= env->nwindows; |
1544 |
} |
1545 |
return cwp;
|
1546 |
} |
1547 |
|
1548 |
int cpu_cwp_inc(CPUState *env1, int cwp) |
1549 |
{ |
1550 |
CPUState *saved_env; |
1551 |
target_ulong ret; |
1552 |
|
1553 |
saved_env = env; |
1554 |
env = env1; |
1555 |
ret = cwp_inc(cwp); |
1556 |
env = saved_env; |
1557 |
return ret;
|
1558 |
} |
1559 |
|
1560 |
static int cwp_dec(int cwp) |
1561 |
{ |
1562 |
if (unlikely(cwp < 0)) { |
1563 |
cwp += env->nwindows; |
1564 |
} |
1565 |
return cwp;
|
1566 |
} |
1567 |
|
1568 |
int cpu_cwp_dec(CPUState *env1, int cwp) |
1569 |
{ |
1570 |
CPUState *saved_env; |
1571 |
target_ulong ret; |
1572 |
|
1573 |
saved_env = env; |
1574 |
env = env1; |
1575 |
ret = cwp_dec(cwp); |
1576 |
env = saved_env; |
1577 |
return ret;
|
1578 |
} |
1579 |
|
1580 |
#ifdef TARGET_SPARC64
|
1581 |
GEN_FCMPS(fcmps_fcc1, float32, 22, 0); |
1582 |
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
1583 |
GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); |
1584 |
|
1585 |
GEN_FCMPS(fcmps_fcc2, float32, 24, 0); |
1586 |
GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
1587 |
GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); |
1588 |
|
1589 |
GEN_FCMPS(fcmps_fcc3, float32, 26, 0); |
1590 |
GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
1591 |
GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); |
1592 |
|
1593 |
GEN_FCMPS(fcmpes_fcc1, float32, 22, 1); |
1594 |
GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
1595 |
GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); |
1596 |
|
1597 |
GEN_FCMPS(fcmpes_fcc2, float32, 24, 1); |
1598 |
GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
1599 |
GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); |
1600 |
|
1601 |
GEN_FCMPS(fcmpes_fcc3, float32, 26, 1); |
1602 |
GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
1603 |
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); |
1604 |
#endif
|
1605 |
#undef GEN_FCMPS
|
1606 |
|
1607 |
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
|
1608 |
defined(DEBUG_MXCC) |
1609 |
static void dump_mxcc(CPUState *env) |
1610 |
{ |
1611 |
printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1612 |
"\n",
|
1613 |
env->mxccdata[0], env->mxccdata[1], |
1614 |
env->mxccdata[2], env->mxccdata[3]); |
1615 |
printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1616 |
"\n"
|
1617 |
" %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1618 |
"\n",
|
1619 |
env->mxccregs[0], env->mxccregs[1], |
1620 |
env->mxccregs[2], env->mxccregs[3], |
1621 |
env->mxccregs[4], env->mxccregs[5], |
1622 |
env->mxccregs[6], env->mxccregs[7]); |
1623 |
} |
1624 |
#endif
|
1625 |
|
1626 |
#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
|
1627 |
&& defined(DEBUG_ASI) |
1628 |
static void dump_asi(const char *txt, target_ulong addr, int asi, int size, |
1629 |
uint64_t r1) |
1630 |
{ |
1631 |
switch (size)
|
1632 |
{ |
1633 |
case 1: |
1634 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
1635 |
addr, asi, r1 & 0xff);
|
1636 |
break;
|
1637 |
case 2: |
1638 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
1639 |
addr, asi, r1 & 0xffff);
|
1640 |
break;
|
1641 |
case 4: |
1642 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
1643 |
addr, asi, r1 & 0xffffffff);
|
1644 |
break;
|
1645 |
case 8: |
1646 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
1647 |
addr, asi, r1); |
1648 |
break;
|
1649 |
} |
1650 |
} |
1651 |
#endif
|
1652 |
|
1653 |
#ifndef TARGET_SPARC64
|
1654 |
#ifndef CONFIG_USER_ONLY
|
1655 |
|
1656 |
|
1657 |
/* Leon3 cache control */
|
1658 |
|
1659 |
static void leon3_cache_control_int(void) |
1660 |
{ |
1661 |
uint32_t state = 0;
|
1662 |
|
1663 |
if (env->cache_control & CACHE_CTRL_IF) {
|
1664 |
/* Instruction cache state */
|
1665 |
state = env->cache_control & CACHE_STATE_MASK; |
1666 |
if (state == CACHE_ENABLED) {
|
1667 |
state = CACHE_FROZEN; |
1668 |
DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
|
1669 |
} |
1670 |
|
1671 |
env->cache_control &= ~CACHE_STATE_MASK; |
1672 |
env->cache_control |= state; |
1673 |
} |
1674 |
|
1675 |
if (env->cache_control & CACHE_CTRL_DF) {
|
1676 |
/* Data cache state */
|
1677 |
state = (env->cache_control >> 2) & CACHE_STATE_MASK;
|
1678 |
if (state == CACHE_ENABLED) {
|
1679 |
state = CACHE_FROZEN; |
1680 |
DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
|
1681 |
} |
1682 |
|
1683 |
env->cache_control &= ~(CACHE_STATE_MASK << 2);
|
1684 |
env->cache_control |= (state << 2);
|
1685 |
} |
1686 |
} |
1687 |
|
1688 |
static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size) |
1689 |
{ |
1690 |
DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", |
1691 |
addr, val, size); |
1692 |
|
1693 |
if (size != 4) { |
1694 |
DPRINTF_CACHE_CONTROL("32bits only\n");
|
1695 |
return;
|
1696 |
} |
1697 |
|
1698 |
switch (addr) {
|
1699 |
case 0x00: /* Cache control */ |
1700 |
|
1701 |
/* These values must always be read as zeros */
|
1702 |
val &= ~CACHE_CTRL_FD; |
1703 |
val &= ~CACHE_CTRL_FI; |
1704 |
val &= ~CACHE_CTRL_IB; |
1705 |
val &= ~CACHE_CTRL_IP; |
1706 |
val &= ~CACHE_CTRL_DP; |
1707 |
|
1708 |
env->cache_control = val; |
1709 |
break;
|
1710 |
case 0x04: /* Instruction cache configuration */ |
1711 |
case 0x08: /* Data cache configuration */ |
1712 |
/* Read Only */
|
1713 |
break;
|
1714 |
default:
|
1715 |
DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
|
1716 |
break;
|
1717 |
}; |
1718 |
} |
1719 |
|
1720 |
static uint64_t leon3_cache_control_ld(target_ulong addr, int size) |
1721 |
{ |
1722 |
uint64_t ret = 0;
|
1723 |
|
1724 |
if (size != 4) { |
1725 |
DPRINTF_CACHE_CONTROL("32bits only\n");
|
1726 |
return 0; |
1727 |
} |
1728 |
|
1729 |
switch (addr) {
|
1730 |
case 0x00: /* Cache control */ |
1731 |
ret = env->cache_control; |
1732 |
break;
|
1733 |
|
1734 |
/* Configuration registers are read and only always keep those
|
1735 |
predefined values */
|
1736 |
|
1737 |
case 0x04: /* Instruction cache configuration */ |
1738 |
ret = 0x10220000;
|
1739 |
break;
|
1740 |
case 0x08: /* Data cache configuration */ |
1741 |
ret = 0x18220000;
|
1742 |
break;
|
1743 |
default:
|
1744 |
DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
|
1745 |
break;
|
1746 |
}; |
1747 |
DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", |
1748 |
addr, ret, size); |
1749 |
return ret;
|
1750 |
} |
1751 |
|
1752 |
void leon3_irq_manager(void *irq_manager, int intno) |
1753 |
{ |
1754 |
leon3_irq_ack(irq_manager, intno); |
1755 |
leon3_cache_control_int(); |
1756 |
} |
1757 |
|
1758 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
1759 |
{ |
1760 |
uint64_t ret = 0;
|
1761 |
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
|
1762 |
uint32_t last_addr = addr; |
1763 |
#endif
|
1764 |
|
1765 |
helper_check_align(addr, size - 1);
|
1766 |
switch (asi) {
|
1767 |
case 2: /* SuperSparc MXCC registers and Leon3 cache control */ |
1768 |
switch (addr) {
|
1769 |
case 0x00: /* Leon3 Cache Control */ |
1770 |
case 0x08: /* Leon3 Instruction Cache config */ |
1771 |
case 0x0C: /* Leon3 Date Cache config */ |
1772 |
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
|
1773 |
ret = leon3_cache_control_ld(addr, size); |
1774 |
} |
1775 |
break;
|
1776 |
case 0x01c00a00: /* MXCC control register */ |
1777 |
if (size == 8) |
1778 |
ret = env->mxccregs[3];
|
1779 |
else
|
1780 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1781 |
size); |
1782 |
break;
|
1783 |
case 0x01c00a04: /* MXCC control register */ |
1784 |
if (size == 4) |
1785 |
ret = env->mxccregs[3];
|
1786 |
else
|
1787 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1788 |
size); |
1789 |
break;
|
1790 |
case 0x01c00c00: /* Module reset register */ |
1791 |
if (size == 8) { |
1792 |
ret = env->mxccregs[5];
|
1793 |
// should we do something here?
|
1794 |
} else
|
1795 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1796 |
size); |
1797 |
break;
|
1798 |
case 0x01c00f00: /* MBus port address register */ |
1799 |
if (size == 8) |
1800 |
ret = env->mxccregs[7];
|
1801 |
else
|
1802 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1803 |
size); |
1804 |
break;
|
1805 |
default:
|
1806 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
1807 |
size); |
1808 |
break;
|
1809 |
} |
1810 |
DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
|
1811 |
"addr = %08x -> ret = %" PRIx64 "," |
1812 |
"addr = %08x\n", asi, size, sign, last_addr, ret, addr);
|
1813 |
#ifdef DEBUG_MXCC
|
1814 |
dump_mxcc(env); |
1815 |
#endif
|
1816 |
break;
|
1817 |
case 3: /* MMU probe */ |
1818 |
{ |
1819 |
int mmulev;
|
1820 |
|
1821 |
mmulev = (addr >> 8) & 15; |
1822 |
if (mmulev > 4) |
1823 |
ret = 0;
|
1824 |
else
|
1825 |
ret = mmu_probe(env, addr, mmulev); |
1826 |
DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", |
1827 |
addr, mmulev, ret); |
1828 |
} |
1829 |
break;
|
1830 |
case 4: /* read MMU regs */ |
1831 |
{ |
1832 |
int reg = (addr >> 8) & 0x1f; |
1833 |
|
1834 |
ret = env->mmuregs[reg]; |
1835 |
if (reg == 3) /* Fault status cleared on read */ |
1836 |
env->mmuregs[3] = 0; |
1837 |
else if (reg == 0x13) /* Fault status read */ |
1838 |
ret = env->mmuregs[3];
|
1839 |
else if (reg == 0x14) /* Fault address read */ |
1840 |
ret = env->mmuregs[4];
|
1841 |
DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
1842 |
} |
1843 |
break;
|
1844 |
case 5: // Turbosparc ITLB Diagnostic |
1845 |
case 6: // Turbosparc DTLB Diagnostic |
1846 |
case 7: // Turbosparc IOTLB Diagnostic |
1847 |
break;
|
1848 |
case 9: /* Supervisor code access */ |
1849 |
switch(size) {
|
1850 |
case 1: |
1851 |
ret = ldub_code(addr); |
1852 |
break;
|
1853 |
case 2: |
1854 |
ret = lduw_code(addr); |
1855 |
break;
|
1856 |
default:
|
1857 |
case 4: |
1858 |
ret = ldl_code(addr); |
1859 |
break;
|
1860 |
case 8: |
1861 |
ret = ldq_code(addr); |
1862 |
break;
|
1863 |
} |
1864 |
break;
|
1865 |
case 0xa: /* User data access */ |
1866 |
switch(size) {
|
1867 |
case 1: |
1868 |
ret = ldub_user(addr); |
1869 |
break;
|
1870 |
case 2: |
1871 |
ret = lduw_user(addr); |
1872 |
break;
|
1873 |
default:
|
1874 |
case 4: |
1875 |
ret = ldl_user(addr); |
1876 |
break;
|
1877 |
case 8: |
1878 |
ret = ldq_user(addr); |
1879 |
break;
|
1880 |
} |
1881 |
break;
|
1882 |
case 0xb: /* Supervisor data access */ |
1883 |
switch(size) {
|
1884 |
case 1: |
1885 |
ret = ldub_kernel(addr); |
1886 |
break;
|
1887 |
case 2: |
1888 |
ret = lduw_kernel(addr); |
1889 |
break;
|
1890 |
default:
|
1891 |
case 4: |
1892 |
ret = ldl_kernel(addr); |
1893 |
break;
|
1894 |
case 8: |
1895 |
ret = ldq_kernel(addr); |
1896 |
break;
|
1897 |
} |
1898 |
break;
|
1899 |
case 0xc: /* I-cache tag */ |
1900 |
case 0xd: /* I-cache data */ |
1901 |
case 0xe: /* D-cache tag */ |
1902 |
case 0xf: /* D-cache data */ |
1903 |
break;
|
1904 |
case 0x20: /* MMU passthrough */ |
1905 |
switch(size) {
|
1906 |
case 1: |
1907 |
ret = ldub_phys(addr); |
1908 |
break;
|
1909 |
case 2: |
1910 |
ret = lduw_phys(addr); |
1911 |
break;
|
1912 |
default:
|
1913 |
case 4: |
1914 |
ret = ldl_phys(addr); |
1915 |
break;
|
1916 |
case 8: |
1917 |
ret = ldq_phys(addr); |
1918 |
break;
|
1919 |
} |
1920 |
break;
|
1921 |
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
1922 |
switch(size) {
|
1923 |
case 1: |
1924 |
ret = ldub_phys((target_phys_addr_t)addr |
1925 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
1926 |
break;
|
1927 |
case 2: |
1928 |
ret = lduw_phys((target_phys_addr_t)addr |
1929 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
1930 |
break;
|
1931 |
default:
|
1932 |
case 4: |
1933 |
ret = ldl_phys((target_phys_addr_t)addr |
1934 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
1935 |
break;
|
1936 |
case 8: |
1937 |
ret = ldq_phys((target_phys_addr_t)addr |
1938 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
1939 |
break;
|
1940 |
} |
1941 |
break;
|
1942 |
case 0x30: // Turbosparc secondary cache diagnostic |
1943 |
case 0x31: // Turbosparc RAM snoop |
1944 |
case 0x32: // Turbosparc page table descriptor diagnostic |
1945 |
case 0x39: /* data cache diagnostic register */ |
1946 |
ret = 0;
|
1947 |
break;
|
1948 |
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ |
1949 |
{ |
1950 |
int reg = (addr >> 8) & 3; |
1951 |
|
1952 |
switch(reg) {
|
1953 |
case 0: /* Breakpoint Value (Addr) */ |
1954 |
ret = env->mmubpregs[reg]; |
1955 |
break;
|
1956 |
case 1: /* Breakpoint Mask */ |
1957 |
ret = env->mmubpregs[reg]; |
1958 |
break;
|
1959 |
case 2: /* Breakpoint Control */ |
1960 |
ret = env->mmubpregs[reg]; |
1961 |
break;
|
1962 |
case 3: /* Breakpoint Status */ |
1963 |
ret = env->mmubpregs[reg]; |
1964 |
env->mmubpregs[reg] = 0ULL;
|
1965 |
break;
|
1966 |
} |
1967 |
DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, |
1968 |
ret); |
1969 |
} |
1970 |
break;
|
1971 |
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
1972 |
ret = env->mmubpctrv; |
1973 |
break;
|
1974 |
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
1975 |
ret = env->mmubpctrc; |
1976 |
break;
|
1977 |
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
1978 |
ret = env->mmubpctrs; |
1979 |
break;
|
1980 |
case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
1981 |
ret = env->mmubpaction; |
1982 |
break;
|
1983 |
case 8: /* User code access, XXX */ |
1984 |
default:
|
1985 |
do_unassigned_access(addr, 0, 0, asi, size); |
1986 |
ret = 0;
|
1987 |
break;
|
1988 |
} |
1989 |
if (sign) {
|
1990 |
switch(size) {
|
1991 |
case 1: |
1992 |
ret = (int8_t) ret; |
1993 |
break;
|
1994 |
case 2: |
1995 |
ret = (int16_t) ret; |
1996 |
break;
|
1997 |
case 4: |
1998 |
ret = (int32_t) ret; |
1999 |
break;
|
2000 |
default:
|
2001 |
break;
|
2002 |
} |
2003 |
} |
2004 |
#ifdef DEBUG_ASI
|
2005 |
dump_asi("read ", last_addr, asi, size, ret);
|
2006 |
#endif
|
2007 |
return ret;
|
2008 |
} |
2009 |
|
2010 |
void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
2011 |
{ |
2012 |
helper_check_align(addr, size - 1);
|
2013 |
switch(asi) {
|
2014 |
case 2: /* SuperSparc MXCC registers and Leon3 cache control */ |
2015 |
switch (addr) {
|
2016 |
case 0x00: /* Leon3 Cache Control */ |
2017 |
case 0x08: /* Leon3 Instruction Cache config */ |
2018 |
case 0x0C: /* Leon3 Date Cache config */ |
2019 |
if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
|
2020 |
leon3_cache_control_st(addr, val, size); |
2021 |
} |
2022 |
break;
|
2023 |
|
2024 |
case 0x01c00000: /* MXCC stream data register 0 */ |
2025 |
if (size == 8) |
2026 |
env->mxccdata[0] = val;
|
2027 |
else
|
2028 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2029 |
size); |
2030 |
break;
|
2031 |
case 0x01c00008: /* MXCC stream data register 1 */ |
2032 |
if (size == 8) |
2033 |
env->mxccdata[1] = val;
|
2034 |
else
|
2035 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2036 |
size); |
2037 |
break;
|
2038 |
case 0x01c00010: /* MXCC stream data register 2 */ |
2039 |
if (size == 8) |
2040 |
env->mxccdata[2] = val;
|
2041 |
else
|
2042 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2043 |
size); |
2044 |
break;
|
2045 |
case 0x01c00018: /* MXCC stream data register 3 */ |
2046 |
if (size == 8) |
2047 |
env->mxccdata[3] = val;
|
2048 |
else
|
2049 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2050 |
size); |
2051 |
break;
|
2052 |
case 0x01c00100: /* MXCC stream source */ |
2053 |
if (size == 8) |
2054 |
env->mxccregs[0] = val;
|
2055 |
else
|
2056 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2057 |
size); |
2058 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2059 |
0);
|
2060 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2061 |
8);
|
2062 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2063 |
16);
|
2064 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2065 |
24);
|
2066 |
break;
|
2067 |
case 0x01c00200: /* MXCC stream destination */ |
2068 |
if (size == 8) |
2069 |
env->mxccregs[1] = val;
|
2070 |
else
|
2071 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2072 |
size); |
2073 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, |
2074 |
env->mxccdata[0]);
|
2075 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, |
2076 |
env->mxccdata[1]);
|
2077 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, |
2078 |
env->mxccdata[2]);
|
2079 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, |
2080 |
env->mxccdata[3]);
|
2081 |
break;
|
2082 |
case 0x01c00a00: /* MXCC control register */ |
2083 |
if (size == 8) |
2084 |
env->mxccregs[3] = val;
|
2085 |
else
|
2086 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2087 |
size); |
2088 |
break;
|
2089 |
case 0x01c00a04: /* MXCC control register */ |
2090 |
if (size == 4) |
2091 |
env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) |
2092 |
| val; |
2093 |
else
|
2094 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2095 |
size); |
2096 |
break;
|
2097 |
case 0x01c00e00: /* MXCC error register */ |
2098 |
// writing a 1 bit clears the error
|
2099 |
if (size == 8) |
2100 |
env->mxccregs[6] &= ~val;
|
2101 |
else
|
2102 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2103 |
size); |
2104 |
break;
|
2105 |
case 0x01c00f00: /* MBus port address register */ |
2106 |
if (size == 8) |
2107 |
env->mxccregs[7] = val;
|
2108 |
else
|
2109 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2110 |
size); |
2111 |
break;
|
2112 |
default:
|
2113 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
2114 |
size); |
2115 |
break;
|
2116 |
} |
2117 |
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", |
2118 |
asi, size, addr, val); |
2119 |
#ifdef DEBUG_MXCC
|
2120 |
dump_mxcc(env); |
2121 |
#endif
|
2122 |
break;
|
2123 |
case 3: /* MMU flush */ |
2124 |
{ |
2125 |
int mmulev;
|
2126 |
|
2127 |
mmulev = (addr >> 8) & 15; |
2128 |
DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
2129 |
switch (mmulev) {
|
2130 |
case 0: // flush page |
2131 |
tlb_flush_page(env, addr & 0xfffff000);
|
2132 |
break;
|
2133 |
case 1: // flush segment (256k) |
2134 |
case 2: // flush region (16M) |
2135 |
case 3: // flush context (4G) |
2136 |
case 4: // flush entire |
2137 |
tlb_flush(env, 1);
|
2138 |
break;
|
2139 |
default:
|
2140 |
break;
|
2141 |
} |
2142 |
#ifdef DEBUG_MMU
|
2143 |
dump_mmu(stdout, fprintf, env); |
2144 |
#endif
|
2145 |
} |
2146 |
break;
|
2147 |
case 4: /* write MMU regs */ |
2148 |
{ |
2149 |
int reg = (addr >> 8) & 0x1f; |
2150 |
uint32_t oldreg; |
2151 |
|
2152 |
oldreg = env->mmuregs[reg]; |
2153 |
switch(reg) {
|
2154 |
case 0: // Control Register |
2155 |
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
|
2156 |
(val & 0x00ffffff);
|
2157 |
// Mappings generated during no-fault mode or MMU
|
2158 |
// disabled mode are invalid in normal mode
|
2159 |
if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
|
2160 |
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) |
2161 |
tlb_flush(env, 1);
|
2162 |
break;
|
2163 |
case 1: // Context Table Pointer Register |
2164 |
env->mmuregs[reg] = val & env->def->mmu_ctpr_mask; |
2165 |
break;
|
2166 |
case 2: // Context Register |
2167 |
env->mmuregs[reg] = val & env->def->mmu_cxr_mask; |
2168 |
if (oldreg != env->mmuregs[reg]) {
|
2169 |
/* we flush when the MMU context changes because
|
2170 |
QEMU has no MMU context support */
|
2171 |
tlb_flush(env, 1);
|
2172 |
} |
2173 |
break;
|
2174 |
case 3: // Synchronous Fault Status Register with Clear |
2175 |
case 4: // Synchronous Fault Address Register |
2176 |
break;
|
2177 |
case 0x10: // TLB Replacement Control Register |
2178 |
env->mmuregs[reg] = val & env->def->mmu_trcr_mask; |
2179 |
break;
|
2180 |
case 0x13: // Synchronous Fault Status Register with Read and Clear |
2181 |
env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
|
2182 |
break;
|
2183 |
case 0x14: // Synchronous Fault Address Register |
2184 |
env->mmuregs[4] = val;
|
2185 |
break;
|
2186 |
default:
|
2187 |
env->mmuregs[reg] = val; |
2188 |
break;
|
2189 |
} |
2190 |
if (oldreg != env->mmuregs[reg]) {
|
2191 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
|
2192 |
reg, oldreg, env->mmuregs[reg]); |
2193 |
} |
2194 |
#ifdef DEBUG_MMU
|
2195 |
dump_mmu(stdout, fprintf, env); |
2196 |
#endif
|
2197 |
} |
2198 |
break;
|
2199 |
case 5: // Turbosparc ITLB Diagnostic |
2200 |
case 6: // Turbosparc DTLB Diagnostic |
2201 |
case 7: // Turbosparc IOTLB Diagnostic |
2202 |
break;
|
2203 |
case 0xa: /* User data access */ |
2204 |
switch(size) {
|
2205 |
case 1: |
2206 |
stb_user(addr, val); |
2207 |
break;
|
2208 |
case 2: |
2209 |
stw_user(addr, val); |
2210 |
break;
|
2211 |
default:
|
2212 |
case 4: |
2213 |
stl_user(addr, val); |
2214 |
break;
|
2215 |
case 8: |
2216 |
stq_user(addr, val); |
2217 |
break;
|
2218 |
} |
2219 |
break;
|
2220 |
case 0xb: /* Supervisor data access */ |
2221 |
switch(size) {
|
2222 |
case 1: |
2223 |
stb_kernel(addr, val); |
2224 |
break;
|
2225 |
case 2: |
2226 |
stw_kernel(addr, val); |
2227 |
break;
|
2228 |
default:
|
2229 |
case 4: |
2230 |
stl_kernel(addr, val); |
2231 |
break;
|
2232 |
case 8: |
2233 |
stq_kernel(addr, val); |
2234 |
break;
|
2235 |
} |
2236 |
break;
|
2237 |
case 0xc: /* I-cache tag */ |
2238 |
case 0xd: /* I-cache data */ |
2239 |
case 0xe: /* D-cache tag */ |
2240 |
case 0xf: /* D-cache data */ |
2241 |
case 0x10: /* I/D-cache flush page */ |
2242 |
case 0x11: /* I/D-cache flush segment */ |
2243 |
case 0x12: /* I/D-cache flush region */ |
2244 |
case 0x13: /* I/D-cache flush context */ |
2245 |
case 0x14: /* I/D-cache flush user */ |
2246 |
break;
|
2247 |
case 0x17: /* Block copy, sta access */ |
2248 |
{ |
2249 |
// val = src
|
2250 |
// addr = dst
|
2251 |
// copy 32 bytes
|
2252 |
unsigned int i; |
2253 |
uint32_t src = val & ~3, dst = addr & ~3, temp; |
2254 |
|
2255 |
for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
2256 |
temp = ldl_kernel(src); |
2257 |
stl_kernel(dst, temp); |
2258 |
} |
2259 |
} |
2260 |
break;
|
2261 |
case 0x1f: /* Block fill, stda access */ |
2262 |
{ |
2263 |
// addr = dst
|
2264 |
// fill 32 bytes with val
|
2265 |
unsigned int i; |
2266 |
uint32_t dst = addr & 7;
|
2267 |
|
2268 |
for (i = 0; i < 32; i += 8, dst += 8) |
2269 |
stq_kernel(dst, val); |
2270 |
} |
2271 |
break;
|
2272 |
case 0x20: /* MMU passthrough */ |
2273 |
{ |
2274 |
switch(size) {
|
2275 |
case 1: |
2276 |
stb_phys(addr, val); |
2277 |
break;
|
2278 |
case 2: |
2279 |
stw_phys(addr, val); |
2280 |
break;
|
2281 |
case 4: |
2282 |
default:
|
2283 |
stl_phys(addr, val); |
2284 |
break;
|
2285 |
case 8: |
2286 |
stq_phys(addr, val); |
2287 |
break;
|
2288 |
} |
2289 |
} |
2290 |
break;
|
2291 |
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
2292 |
{ |
2293 |
switch(size) {
|
2294 |
case 1: |
2295 |
stb_phys((target_phys_addr_t)addr |
2296 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2297 |
break;
|
2298 |
case 2: |
2299 |
stw_phys((target_phys_addr_t)addr |
2300 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2301 |
break;
|
2302 |
case 4: |
2303 |
default:
|
2304 |
stl_phys((target_phys_addr_t)addr |
2305 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2306 |
break;
|
2307 |
case 8: |
2308 |
stq_phys((target_phys_addr_t)addr |
2309 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2310 |
break;
|
2311 |
} |
2312 |
} |
2313 |
break;
|
2314 |
case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
2315 |
case 0x31: // store buffer data, Ross RT620 I-cache flush or |
2316 |
// Turbosparc snoop RAM
|
2317 |
case 0x32: // store buffer control or Turbosparc page table |
2318 |
// descriptor diagnostic
|
2319 |
case 0x36: /* I-cache flash clear */ |
2320 |
case 0x37: /* D-cache flash clear */ |
2321 |
break;
|
2322 |
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ |
2323 |
{ |
2324 |
int reg = (addr >> 8) & 3; |
2325 |
|
2326 |
switch(reg) {
|
2327 |
case 0: /* Breakpoint Value (Addr) */ |
2328 |
env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
2329 |
break;
|
2330 |
case 1: /* Breakpoint Mask */ |
2331 |
env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
2332 |
break;
|
2333 |
case 2: /* Breakpoint Control */ |
2334 |
env->mmubpregs[reg] = (val & 0x7fULL);
|
2335 |
break;
|
2336 |
case 3: /* Breakpoint Status */ |
2337 |
env->mmubpregs[reg] = (val & 0xfULL);
|
2338 |
break;
|
2339 |
} |
2340 |
DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
|
2341 |
env->mmuregs[reg]); |
2342 |
} |
2343 |
break;
|
2344 |
case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
2345 |
env->mmubpctrv = val & 0xffffffff;
|
2346 |
break;
|
2347 |
case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
2348 |
env->mmubpctrc = val & 0x3;
|
2349 |
break;
|
2350 |
case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
2351 |
env->mmubpctrs = val & 0x3;
|
2352 |
break;
|
2353 |
case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
2354 |
env->mmubpaction = val & 0x1fff;
|
2355 |
break;
|
2356 |
case 8: /* User code access, XXX */ |
2357 |
case 9: /* Supervisor code access, XXX */ |
2358 |
default:
|
2359 |
do_unassigned_access(addr, 1, 0, asi, size); |
2360 |
break;
|
2361 |
} |
2362 |
#ifdef DEBUG_ASI
|
2363 |
dump_asi("write", addr, asi, size, val);
|
2364 |
#endif
|
2365 |
} |
2366 |
|
2367 |
#endif /* CONFIG_USER_ONLY */ |
2368 |
#else /* TARGET_SPARC64 */ |
2369 |
|
2370 |
#ifdef CONFIG_USER_ONLY
|
2371 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
2372 |
{ |
2373 |
uint64_t ret = 0;
|
2374 |
#if defined(DEBUG_ASI)
|
2375 |
target_ulong last_addr = addr; |
2376 |
#endif
|
2377 |
|
2378 |
if (asi < 0x80) |
2379 |
raise_exception(TT_PRIV_ACT); |
2380 |
|
2381 |
helper_check_align(addr, size - 1);
|
2382 |
addr = asi_address_mask(env, asi, addr); |
2383 |
|
2384 |
switch (asi) {
|
2385 |
case 0x82: // Primary no-fault |
2386 |
case 0x8a: // Primary no-fault LE |
2387 |
if (page_check_range(addr, size, PAGE_READ) == -1) { |
2388 |
#ifdef DEBUG_ASI
|
2389 |
dump_asi("read ", last_addr, asi, size, ret);
|
2390 |
#endif
|
2391 |
return 0; |
2392 |
} |
2393 |
// Fall through
|
2394 |
case 0x80: // Primary |
2395 |
case 0x88: // Primary LE |
2396 |
{ |
2397 |
switch(size) {
|
2398 |
case 1: |
2399 |
ret = ldub_raw(addr); |
2400 |
break;
|
2401 |
case 2: |
2402 |
ret = lduw_raw(addr); |
2403 |
break;
|
2404 |
case 4: |
2405 |
ret = ldl_raw(addr); |
2406 |
break;
|
2407 |
default:
|
2408 |
case 8: |
2409 |
ret = ldq_raw(addr); |
2410 |
break;
|
2411 |
} |
2412 |
} |
2413 |
break;
|
2414 |
case 0x83: // Secondary no-fault |
2415 |
case 0x8b: // Secondary no-fault LE |
2416 |
if (page_check_range(addr, size, PAGE_READ) == -1) { |
2417 |
#ifdef DEBUG_ASI
|
2418 |
dump_asi("read ", last_addr, asi, size, ret);
|
2419 |
#endif
|
2420 |
return 0; |
2421 |
} |
2422 |
// Fall through
|
2423 |
case 0x81: // Secondary |
2424 |
case 0x89: // Secondary LE |
2425 |
// XXX
|
2426 |
break;
|
2427 |
default:
|
2428 |
break;
|
2429 |
} |
2430 |
|
2431 |
/* Convert from little endian */
|
2432 |
switch (asi) {
|
2433 |
case 0x88: // Primary LE |
2434 |
case 0x89: // Secondary LE |
2435 |
case 0x8a: // Primary no-fault LE |
2436 |
case 0x8b: // Secondary no-fault LE |
2437 |
switch(size) {
|
2438 |
case 2: |
2439 |
ret = bswap16(ret); |
2440 |
break;
|
2441 |
case 4: |
2442 |
ret = bswap32(ret); |
2443 |
break;
|
2444 |
case 8: |
2445 |
ret = bswap64(ret); |
2446 |
break;
|
2447 |
default:
|
2448 |
break;
|
2449 |
} |
2450 |
default:
|
2451 |
break;
|
2452 |
} |
2453 |
|
2454 |
/* Convert to signed number */
|
2455 |
if (sign) {
|
2456 |
switch(size) {
|
2457 |
case 1: |
2458 |
ret = (int8_t) ret; |
2459 |
break;
|
2460 |
case 2: |
2461 |
ret = (int16_t) ret; |
2462 |
break;
|
2463 |
case 4: |
2464 |
ret = (int32_t) ret; |
2465 |
break;
|
2466 |
default:
|
2467 |
break;
|
2468 |
} |
2469 |
} |
2470 |
#ifdef DEBUG_ASI
|
2471 |
dump_asi("read ", last_addr, asi, size, ret);
|
2472 |
#endif
|
2473 |
return ret;
|
2474 |
} |
2475 |
|
2476 |
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
2477 |
{ |
2478 |
#ifdef DEBUG_ASI
|
2479 |
dump_asi("write", addr, asi, size, val);
|
2480 |
#endif
|
2481 |
if (asi < 0x80) |
2482 |
raise_exception(TT_PRIV_ACT); |
2483 |
|
2484 |
helper_check_align(addr, size - 1);
|
2485 |
addr = asi_address_mask(env, asi, addr); |
2486 |
|
2487 |
/* Convert to little endian */
|
2488 |
switch (asi) {
|
2489 |
case 0x88: // Primary LE |
2490 |
case 0x89: // Secondary LE |
2491 |
switch(size) {
|
2492 |
case 2: |
2493 |
val = bswap16(val); |
2494 |
break;
|
2495 |
case 4: |
2496 |
val = bswap32(val); |
2497 |
break;
|
2498 |
case 8: |
2499 |
val = bswap64(val); |
2500 |
break;
|
2501 |
default:
|
2502 |
break;
|
2503 |
} |
2504 |
default:
|
2505 |
break;
|
2506 |
} |
2507 |
|
2508 |
switch(asi) {
|
2509 |
case 0x80: // Primary |
2510 |
case 0x88: // Primary LE |
2511 |
{ |
2512 |
switch(size) {
|
2513 |
case 1: |
2514 |
stb_raw(addr, val); |
2515 |
break;
|
2516 |
case 2: |
2517 |
stw_raw(addr, val); |
2518 |
break;
|
2519 |
case 4: |
2520 |
stl_raw(addr, val); |
2521 |
break;
|
2522 |
case 8: |
2523 |
default:
|
2524 |
stq_raw(addr, val); |
2525 |
break;
|
2526 |
} |
2527 |
} |
2528 |
break;
|
2529 |
case 0x81: // Secondary |
2530 |
case 0x89: // Secondary LE |
2531 |
// XXX
|
2532 |
return;
|
2533 |
|
2534 |
case 0x82: // Primary no-fault, RO |
2535 |
case 0x83: // Secondary no-fault, RO |
2536 |
case 0x8a: // Primary no-fault LE, RO |
2537 |
case 0x8b: // Secondary no-fault LE, RO |
2538 |
default:
|
2539 |
do_unassigned_access(addr, 1, 0, 1, size); |
2540 |
return;
|
2541 |
} |
2542 |
} |
2543 |
|
2544 |
#else /* CONFIG_USER_ONLY */ |
2545 |
|
2546 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
2547 |
{ |
2548 |
uint64_t ret = 0;
|
2549 |
#if defined(DEBUG_ASI)
|
2550 |
target_ulong last_addr = addr; |
2551 |
#endif
|
2552 |
|
2553 |
asi &= 0xff;
|
2554 |
|
2555 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2556 |
|| (cpu_has_hypervisor(env) |
2557 |
&& asi >= 0x30 && asi < 0x80 |
2558 |
&& !(env->hpstate & HS_PRIV))) |
2559 |
raise_exception(TT_PRIV_ACT); |
2560 |
|
2561 |
helper_check_align(addr, size - 1);
|
2562 |
addr = asi_address_mask(env, asi, addr); |
2563 |
|
2564 |
switch (asi) {
|
2565 |
case 0x82: // Primary no-fault |
2566 |
case 0x8a: // Primary no-fault LE |
2567 |
case 0x83: // Secondary no-fault |
2568 |
case 0x8b: // Secondary no-fault LE |
2569 |
{ |
2570 |
/* secondary space access has lowest asi bit equal to 1 */
|
2571 |
int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX |
2572 |
: MMU_KERNEL_SECONDARY_IDX; |
2573 |
|
2574 |
if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) { |
2575 |
#ifdef DEBUG_ASI
|
2576 |
dump_asi("read ", last_addr, asi, size, ret);
|
2577 |
#endif
|
2578 |
return 0; |
2579 |
} |
2580 |
} |
2581 |
// Fall through
|
2582 |
case 0x10: // As if user primary |
2583 |
case 0x11: // As if user secondary |
2584 |
case 0x18: // As if user primary LE |
2585 |
case 0x19: // As if user secondary LE |
2586 |
case 0x80: // Primary |
2587 |
case 0x81: // Secondary |
2588 |
case 0x88: // Primary LE |
2589 |
case 0x89: // Secondary LE |
2590 |
case 0xe2: // UA2007 Primary block init |
2591 |
case 0xe3: // UA2007 Secondary block init |
2592 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2593 |
if (cpu_hypervisor_mode(env)) {
|
2594 |
switch(size) {
|
2595 |
case 1: |
2596 |
ret = ldub_hypv(addr); |
2597 |
break;
|
2598 |
case 2: |
2599 |
ret = lduw_hypv(addr); |
2600 |
break;
|
2601 |
case 4: |
2602 |
ret = ldl_hypv(addr); |
2603 |
break;
|
2604 |
default:
|
2605 |
case 8: |
2606 |
ret = ldq_hypv(addr); |
2607 |
break;
|
2608 |
} |
2609 |
} else {
|
2610 |
/* secondary space access has lowest asi bit equal to 1 */
|
2611 |
if (asi & 1) { |
2612 |
switch(size) {
|
2613 |
case 1: |
2614 |
ret = ldub_kernel_secondary(addr); |
2615 |
break;
|
2616 |
case 2: |
2617 |
ret = lduw_kernel_secondary(addr); |
2618 |
break;
|
2619 |
case 4: |
2620 |
ret = ldl_kernel_secondary(addr); |
2621 |
break;
|
2622 |
default:
|
2623 |
case 8: |
2624 |
ret = ldq_kernel_secondary(addr); |
2625 |
break;
|
2626 |
} |
2627 |
} else {
|
2628 |
switch(size) {
|
2629 |
case 1: |
2630 |
ret = ldub_kernel(addr); |
2631 |
break;
|
2632 |
case 2: |
2633 |
ret = lduw_kernel(addr); |
2634 |
break;
|
2635 |
case 4: |
2636 |
ret = ldl_kernel(addr); |
2637 |
break;
|
2638 |
default:
|
2639 |
case 8: |
2640 |
ret = ldq_kernel(addr); |
2641 |
break;
|
2642 |
} |
2643 |
} |
2644 |
} |
2645 |
} else {
|
2646 |
/* secondary space access has lowest asi bit equal to 1 */
|
2647 |
if (asi & 1) { |
2648 |
switch(size) {
|
2649 |
case 1: |
2650 |
ret = ldub_user_secondary(addr); |
2651 |
break;
|
2652 |
case 2: |
2653 |
ret = lduw_user_secondary(addr); |
2654 |
break;
|
2655 |
case 4: |
2656 |
ret = ldl_user_secondary(addr); |
2657 |
break;
|
2658 |
default:
|
2659 |
case 8: |
2660 |
ret = ldq_user_secondary(addr); |
2661 |
break;
|
2662 |
} |
2663 |
} else {
|
2664 |
switch(size) {
|
2665 |
case 1: |
2666 |
ret = ldub_user(addr); |
2667 |
break;
|
2668 |
case 2: |
2669 |
ret = lduw_user(addr); |
2670 |
break;
|
2671 |
case 4: |
2672 |
ret = ldl_user(addr); |
2673 |
break;
|
2674 |
default:
|
2675 |
case 8: |
2676 |
ret = ldq_user(addr); |
2677 |
break;
|
2678 |
} |
2679 |
} |
2680 |
} |
2681 |
break;
|
2682 |
case 0x14: // Bypass |
2683 |
case 0x15: // Bypass, non-cacheable |
2684 |
case 0x1c: // Bypass LE |
2685 |
case 0x1d: // Bypass, non-cacheable LE |
2686 |
{ |
2687 |
switch(size) {
|
2688 |
case 1: |
2689 |
ret = ldub_phys(addr); |
2690 |
break;
|
2691 |
case 2: |
2692 |
ret = lduw_phys(addr); |
2693 |
break;
|
2694 |
case 4: |
2695 |
ret = ldl_phys(addr); |
2696 |
break;
|
2697 |
default:
|
2698 |
case 8: |
2699 |
ret = ldq_phys(addr); |
2700 |
break;
|
2701 |
} |
2702 |
break;
|
2703 |
} |
2704 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
2705 |
case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
2706 |
// Only ldda allowed
|
2707 |
raise_exception(TT_ILL_INSN); |
2708 |
return 0; |
2709 |
case 0x04: // Nucleus |
2710 |
case 0x0c: // Nucleus Little Endian (LE) |
2711 |
{ |
2712 |
switch(size) {
|
2713 |
case 1: |
2714 |
ret = ldub_nucleus(addr); |
2715 |
break;
|
2716 |
case 2: |
2717 |
ret = lduw_nucleus(addr); |
2718 |
break;
|
2719 |
case 4: |
2720 |
ret = ldl_nucleus(addr); |
2721 |
break;
|
2722 |
default:
|
2723 |
case 8: |
2724 |
ret = ldq_nucleus(addr); |
2725 |
break;
|
2726 |
} |
2727 |
break;
|
2728 |
} |
2729 |
case 0x4a: // UPA config |
2730 |
// XXX
|
2731 |
break;
|
2732 |
case 0x45: // LSU |
2733 |
ret = env->lsu; |
2734 |
break;
|
2735 |
case 0x50: // I-MMU regs |
2736 |
{ |
2737 |
int reg = (addr >> 3) & 0xf; |
2738 |
|
2739 |
if (reg == 0) { |
2740 |
// I-TSB Tag Target register
|
2741 |
ret = ultrasparc_tag_target(env->immu.tag_access); |
2742 |
} else {
|
2743 |
ret = env->immuregs[reg]; |
2744 |
} |
2745 |
|
2746 |
break;
|
2747 |
} |
2748 |
case 0x51: // I-MMU 8k TSB pointer |
2749 |
{ |
2750 |
// env->immuregs[5] holds I-MMU TSB register value
|
2751 |
// env->immuregs[6] holds I-MMU Tag Access register value
|
2752 |
ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
2753 |
8*1024); |
2754 |
break;
|
2755 |
} |
2756 |
case 0x52: // I-MMU 64k TSB pointer |
2757 |
{ |
2758 |
// env->immuregs[5] holds I-MMU TSB register value
|
2759 |
// env->immuregs[6] holds I-MMU Tag Access register value
|
2760 |
ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
2761 |
64*1024); |
2762 |
break;
|
2763 |
} |
2764 |
case 0x55: // I-MMU data access |
2765 |
{ |
2766 |
int reg = (addr >> 3) & 0x3f; |
2767 |
|
2768 |
ret = env->itlb[reg].tte; |
2769 |
break;
|
2770 |
} |
2771 |
case 0x56: // I-MMU tag read |
2772 |
{ |
2773 |
int reg = (addr >> 3) & 0x3f; |
2774 |
|
2775 |
ret = env->itlb[reg].tag; |
2776 |
break;
|
2777 |
} |
2778 |
case 0x58: // D-MMU regs |
2779 |
{ |
2780 |
int reg = (addr >> 3) & 0xf; |
2781 |
|
2782 |
if (reg == 0) { |
2783 |
// D-TSB Tag Target register
|
2784 |
ret = ultrasparc_tag_target(env->dmmu.tag_access); |
2785 |
} else {
|
2786 |
ret = env->dmmuregs[reg]; |
2787 |
} |
2788 |
break;
|
2789 |
} |
2790 |
case 0x59: // D-MMU 8k TSB pointer |
2791 |
{ |
2792 |
// env->dmmuregs[5] holds D-MMU TSB register value
|
2793 |
// env->dmmuregs[6] holds D-MMU Tag Access register value
|
2794 |
ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
2795 |
8*1024); |
2796 |
break;
|
2797 |
} |
2798 |
case 0x5a: // D-MMU 64k TSB pointer |
2799 |
{ |
2800 |
// env->dmmuregs[5] holds D-MMU TSB register value
|
2801 |
// env->dmmuregs[6] holds D-MMU Tag Access register value
|
2802 |
ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
2803 |
64*1024); |
2804 |
break;
|
2805 |
} |
2806 |
case 0x5d: // D-MMU data access |
2807 |
{ |
2808 |
int reg = (addr >> 3) & 0x3f; |
2809 |
|
2810 |
ret = env->dtlb[reg].tte; |
2811 |
break;
|
2812 |
} |
2813 |
case 0x5e: // D-MMU tag read |
2814 |
{ |
2815 |
int reg = (addr >> 3) & 0x3f; |
2816 |
|
2817 |
ret = env->dtlb[reg].tag; |
2818 |
break;
|
2819 |
} |
2820 |
case 0x46: // D-cache data |
2821 |
case 0x47: // D-cache tag access |
2822 |
case 0x4b: // E-cache error enable |
2823 |
case 0x4c: // E-cache asynchronous fault status |
2824 |
case 0x4d: // E-cache asynchronous fault address |
2825 |
case 0x4e: // E-cache tag data |
2826 |
case 0x66: // I-cache instruction access |
2827 |
case 0x67: // I-cache tag access |
2828 |
case 0x6e: // I-cache predecode |
2829 |
case 0x6f: // I-cache LRU etc. |
2830 |
case 0x76: // E-cache tag |
2831 |
case 0x7e: // E-cache tag |
2832 |
break;
|
2833 |
case 0x5b: // D-MMU data pointer |
2834 |
case 0x48: // Interrupt dispatch, RO |
2835 |
case 0x49: // Interrupt data receive |
2836 |
case 0x7f: // Incoming interrupt vector, RO |
2837 |
// XXX
|
2838 |
break;
|
2839 |
case 0x54: // I-MMU data in, WO |
2840 |
case 0x57: // I-MMU demap, WO |
2841 |
case 0x5c: // D-MMU data in, WO |
2842 |
case 0x5f: // D-MMU demap, WO |
2843 |
case 0x77: // Interrupt vector, WO |
2844 |
default:
|
2845 |
do_unassigned_access(addr, 0, 0, 1, size); |
2846 |
ret = 0;
|
2847 |
break;
|
2848 |
} |
2849 |
|
2850 |
/* Convert from little endian */
|
2851 |
switch (asi) {
|
2852 |
case 0x0c: // Nucleus Little Endian (LE) |
2853 |
case 0x18: // As if user primary LE |
2854 |
case 0x19: // As if user secondary LE |
2855 |
case 0x1c: // Bypass LE |
2856 |
case 0x1d: // Bypass, non-cacheable LE |
2857 |
case 0x88: // Primary LE |
2858 |
case 0x89: // Secondary LE |
2859 |
case 0x8a: // Primary no-fault LE |
2860 |
case 0x8b: // Secondary no-fault LE |
2861 |
switch(size) {
|
2862 |
case 2: |
2863 |
ret = bswap16(ret); |
2864 |
break;
|
2865 |
case 4: |
2866 |
ret = bswap32(ret); |
2867 |
break;
|
2868 |
case 8: |
2869 |
ret = bswap64(ret); |
2870 |
break;
|
2871 |
default:
|
2872 |
break;
|
2873 |
} |
2874 |
default:
|
2875 |
break;
|
2876 |
} |
2877 |
|
2878 |
/* Convert to signed number */
|
2879 |
if (sign) {
|
2880 |
switch(size) {
|
2881 |
case 1: |
2882 |
ret = (int8_t) ret; |
2883 |
break;
|
2884 |
case 2: |
2885 |
ret = (int16_t) ret; |
2886 |
break;
|
2887 |
case 4: |
2888 |
ret = (int32_t) ret; |
2889 |
break;
|
2890 |
default:
|
2891 |
break;
|
2892 |
} |
2893 |
} |
2894 |
#ifdef DEBUG_ASI
|
2895 |
dump_asi("read ", last_addr, asi, size, ret);
|
2896 |
#endif
|
2897 |
return ret;
|
2898 |
} |
2899 |
|
2900 |
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
2901 |
{ |
2902 |
#ifdef DEBUG_ASI
|
2903 |
dump_asi("write", addr, asi, size, val);
|
2904 |
#endif
|
2905 |
|
2906 |
asi &= 0xff;
|
2907 |
|
2908 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2909 |
|| (cpu_has_hypervisor(env) |
2910 |
&& asi >= 0x30 && asi < 0x80 |
2911 |
&& !(env->hpstate & HS_PRIV))) |
2912 |
raise_exception(TT_PRIV_ACT); |
2913 |
|
2914 |
helper_check_align(addr, size - 1);
|
2915 |
addr = asi_address_mask(env, asi, addr); |
2916 |
|
2917 |
/* Convert to little endian */
|
2918 |
switch (asi) {
|
2919 |
case 0x0c: // Nucleus Little Endian (LE) |
2920 |
case 0x18: // As if user primary LE |
2921 |
case 0x19: // As if user secondary LE |
2922 |
case 0x1c: // Bypass LE |
2923 |
case 0x1d: // Bypass, non-cacheable LE |
2924 |
case 0x88: // Primary LE |
2925 |
case 0x89: // Secondary LE |
2926 |
switch(size) {
|
2927 |
case 2: |
2928 |
val = bswap16(val); |
2929 |
break;
|
2930 |
case 4: |
2931 |
val = bswap32(val); |
2932 |
break;
|
2933 |
case 8: |
2934 |
val = bswap64(val); |
2935 |
break;
|
2936 |
default:
|
2937 |
break;
|
2938 |
} |
2939 |
default:
|
2940 |
break;
|
2941 |
} |
2942 |
|
2943 |
switch(asi) {
|
2944 |
case 0x10: // As if user primary |
2945 |
case 0x11: // As if user secondary |
2946 |
case 0x18: // As if user primary LE |
2947 |
case 0x19: // As if user secondary LE |
2948 |
case 0x80: // Primary |
2949 |
case 0x81: // Secondary |
2950 |
case 0x88: // Primary LE |
2951 |
case 0x89: // Secondary LE |
2952 |
case 0xe2: // UA2007 Primary block init |
2953 |
case 0xe3: // UA2007 Secondary block init |
2954 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2955 |
if (cpu_hypervisor_mode(env)) {
|
2956 |
switch(size) {
|
2957 |
case 1: |
2958 |
stb_hypv(addr, val); |
2959 |
break;
|
2960 |
case 2: |
2961 |
stw_hypv(addr, val); |
2962 |
break;
|
2963 |
case 4: |
2964 |
stl_hypv(addr, val); |
2965 |
break;
|
2966 |
case 8: |
2967 |
default:
|
2968 |
stq_hypv(addr, val); |
2969 |
break;
|
2970 |
} |
2971 |
} else {
|
2972 |
/* secondary space access has lowest asi bit equal to 1 */
|
2973 |
if (asi & 1) { |
2974 |
switch(size) {
|
2975 |
case 1: |
2976 |
stb_kernel_secondary(addr, val); |
2977 |
break;
|
2978 |
case 2: |
2979 |
stw_kernel_secondary(addr, val); |
2980 |
break;
|
2981 |
case 4: |
2982 |
stl_kernel_secondary(addr, val); |
2983 |
break;
|
2984 |
case 8: |
2985 |
default:
|
2986 |
stq_kernel_secondary(addr, val); |
2987 |
break;
|
2988 |
} |
2989 |
} else {
|
2990 |
switch(size) {
|
2991 |
case 1: |
2992 |
stb_kernel(addr, val); |
2993 |
break;
|
2994 |
case 2: |
2995 |
stw_kernel(addr, val); |
2996 |
break;
|
2997 |
case 4: |
2998 |
stl_kernel(addr, val); |
2999 |
break;
|
3000 |
case 8: |
3001 |
default:
|
3002 |
stq_kernel(addr, val); |
3003 |
break;
|
3004 |
} |
3005 |
} |
3006 |
} |
3007 |
} else {
|
3008 |
/* secondary space access has lowest asi bit equal to 1 */
|
3009 |
if (asi & 1) { |
3010 |
switch(size) {
|
3011 |
case 1: |
3012 |
stb_user_secondary(addr, val); |
3013 |
break;
|
3014 |
case 2: |
3015 |
stw_user_secondary(addr, val); |
3016 |
break;
|
3017 |
case 4: |
3018 |
stl_user_secondary(addr, val); |
3019 |
break;
|
3020 |
case 8: |
3021 |
default:
|
3022 |
stq_user_secondary(addr, val); |
3023 |
break;
|
3024 |
} |
3025 |
} else {
|
3026 |
switch(size) {
|
3027 |
case 1: |
3028 |
stb_user(addr, val); |
3029 |
break;
|
3030 |
case 2: |
3031 |
stw_user(addr, val); |
3032 |
break;
|
3033 |
case 4: |
3034 |
stl_user(addr, val); |
3035 |
break;
|
3036 |
case 8: |
3037 |
default:
|
3038 |
stq_user(addr, val); |
3039 |
break;
|
3040 |
} |
3041 |
} |
3042 |
} |
3043 |
break;
|
3044 |
case 0x14: // Bypass |
3045 |
case 0x15: // Bypass, non-cacheable |
3046 |
case 0x1c: // Bypass LE |
3047 |
case 0x1d: // Bypass, non-cacheable LE |
3048 |
{ |
3049 |
switch(size) {
|
3050 |
case 1: |
3051 |
stb_phys(addr, val); |
3052 |
break;
|
3053 |
case 2: |
3054 |
stw_phys(addr, val); |
3055 |
break;
|
3056 |
case 4: |
3057 |
stl_phys(addr, val); |
3058 |
break;
|
3059 |
case 8: |
3060 |
default:
|
3061 |
stq_phys(addr, val); |
3062 |
break;
|
3063 |
} |
3064 |
} |
3065 |
return;
|
3066 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
3067 |
case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
3068 |
// Only ldda allowed
|
3069 |
raise_exception(TT_ILL_INSN); |
3070 |
return;
|
3071 |
case 0x04: // Nucleus |
3072 |
case 0x0c: // Nucleus Little Endian (LE) |
3073 |
{ |
3074 |
switch(size) {
|
3075 |
case 1: |
3076 |
stb_nucleus(addr, val); |
3077 |
break;
|
3078 |
case 2: |
3079 |
stw_nucleus(addr, val); |
3080 |
break;
|
3081 |
case 4: |
3082 |
stl_nucleus(addr, val); |
3083 |
break;
|
3084 |
default:
|
3085 |
case 8: |
3086 |
stq_nucleus(addr, val); |
3087 |
break;
|
3088 |
} |
3089 |
break;
|
3090 |
} |
3091 |
|
3092 |
case 0x4a: // UPA config |
3093 |
// XXX
|
3094 |
return;
|
3095 |
case 0x45: // LSU |
3096 |
{ |
3097 |
uint64_t oldreg; |
3098 |
|
3099 |
oldreg = env->lsu; |
3100 |
env->lsu = val & (DMMU_E | IMMU_E); |
3101 |
// Mappings generated during D/I MMU disabled mode are
|
3102 |
// invalid in normal mode
|
3103 |
if (oldreg != env->lsu) {
|
3104 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", |
3105 |
oldreg, env->lsu); |
3106 |
#ifdef DEBUG_MMU
|
3107 |
dump_mmu(stdout, fprintf, env1); |
3108 |
#endif
|
3109 |
tlb_flush(env, 1);
|
3110 |
} |
3111 |
return;
|
3112 |
} |
3113 |
case 0x50: // I-MMU regs |
3114 |
{ |
3115 |
int reg = (addr >> 3) & 0xf; |
3116 |
uint64_t oldreg; |
3117 |
|
3118 |
oldreg = env->immuregs[reg]; |
3119 |
switch(reg) {
|
3120 |
case 0: // RO |
3121 |
return;
|
3122 |
case 1: // Not in I-MMU |
3123 |
case 2: |
3124 |
return;
|
3125 |
case 3: // SFSR |
3126 |
if ((val & 1) == 0) |
3127 |
val = 0; // Clear SFSR |
3128 |
env->immu.sfsr = val; |
3129 |
break;
|
3130 |
case 4: // RO |
3131 |
return;
|
3132 |
case 5: // TSB access |
3133 |
DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" |
3134 |
PRIx64 "\n", env->immu.tsb, val);
|
3135 |
env->immu.tsb = val; |
3136 |
break;
|
3137 |
case 6: // Tag access |
3138 |
env->immu.tag_access = val; |
3139 |
break;
|
3140 |
case 7: |
3141 |
case 8: |
3142 |
return;
|
3143 |
default:
|
3144 |
break;
|
3145 |
} |
3146 |
|
3147 |
if (oldreg != env->immuregs[reg]) {
|
3148 |
DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
3149 |
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
3150 |
} |
3151 |
#ifdef DEBUG_MMU
|
3152 |
dump_mmu(stdout, fprintf, env); |
3153 |
#endif
|
3154 |
return;
|
3155 |
} |
3156 |
case 0x54: // I-MMU data in |
3157 |
replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
|
3158 |
return;
|
3159 |
case 0x55: // I-MMU data access |
3160 |
{ |
3161 |
// TODO: auto demap
|
3162 |
|
3163 |
unsigned int i = (addr >> 3) & 0x3f; |
3164 |
|
3165 |
replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env); |
3166 |
|
3167 |
#ifdef DEBUG_MMU
|
3168 |
DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
|
3169 |
dump_mmu(stdout, fprintf, env); |
3170 |
#endif
|
3171 |
return;
|
3172 |
} |
3173 |
case 0x57: // I-MMU demap |
3174 |
demap_tlb(env->itlb, addr, "immu", env);
|
3175 |
return;
|
3176 |
case 0x58: // D-MMU regs |
3177 |
{ |
3178 |
int reg = (addr >> 3) & 0xf; |
3179 |
uint64_t oldreg; |
3180 |
|
3181 |
oldreg = env->dmmuregs[reg]; |
3182 |
switch(reg) {
|
3183 |
case 0: // RO |
3184 |
case 4: |
3185 |
return;
|
3186 |
case 3: // SFSR |
3187 |
if ((val & 1) == 0) { |
3188 |
val = 0; // Clear SFSR, Fault address |
3189 |
env->dmmu.sfar = 0;
|
3190 |
} |
3191 |
env->dmmu.sfsr = val; |
3192 |
break;
|
3193 |
case 1: // Primary context |
3194 |
env->dmmu.mmu_primary_context = val; |
3195 |
/* can be optimized to only flush MMU_USER_IDX
|
3196 |
and MMU_KERNEL_IDX entries */
|
3197 |
tlb_flush(env, 1);
|
3198 |
break;
|
3199 |
case 2: // Secondary context |
3200 |
env->dmmu.mmu_secondary_context = val; |
3201 |
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
|
3202 |
and MMU_KERNEL_SECONDARY_IDX entries */
|
3203 |
tlb_flush(env, 1);
|
3204 |
break;
|
3205 |
case 5: // TSB access |
3206 |
DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" |
3207 |
PRIx64 "\n", env->dmmu.tsb, val);
|
3208 |
env->dmmu.tsb = val; |
3209 |
break;
|
3210 |
case 6: // Tag access |
3211 |
env->dmmu.tag_access = val; |
3212 |
break;
|
3213 |
case 7: // Virtual Watchpoint |
3214 |
case 8: // Physical Watchpoint |
3215 |
default:
|
3216 |
env->dmmuregs[reg] = val; |
3217 |
break;
|
3218 |
} |
3219 |
|
3220 |
if (oldreg != env->dmmuregs[reg]) {
|
3221 |
DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
3222 |
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
3223 |
} |
3224 |
#ifdef DEBUG_MMU
|
3225 |
dump_mmu(stdout, fprintf, env); |
3226 |
#endif
|
3227 |
return;
|
3228 |
} |
3229 |
case 0x5c: // D-MMU data in |
3230 |
replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
|
3231 |
return;
|
3232 |
case 0x5d: // D-MMU data access |
3233 |
{ |
3234 |
unsigned int i = (addr >> 3) & 0x3f; |
3235 |
|
3236 |
replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env); |
3237 |
|
3238 |
#ifdef DEBUG_MMU
|
3239 |
DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
|
3240 |
dump_mmu(stdout, fprintf, env); |
3241 |
#endif
|
3242 |
return;
|
3243 |
} |
3244 |
case 0x5f: // D-MMU demap |
3245 |
demap_tlb(env->dtlb, addr, "dmmu", env);
|
3246 |
return;
|
3247 |
case 0x49: // Interrupt data receive |
3248 |
// XXX
|
3249 |
return;
|
3250 |
case 0x46: // D-cache data |
3251 |
case 0x47: // D-cache tag access |
3252 |
case 0x4b: // E-cache error enable |
3253 |
case 0x4c: // E-cache asynchronous fault status |
3254 |
case 0x4d: // E-cache asynchronous fault address |
3255 |
case 0x4e: // E-cache tag data |
3256 |
case 0x66: // I-cache instruction access |
3257 |
case 0x67: // I-cache tag access |
3258 |
case 0x6e: // I-cache predecode |
3259 |
case 0x6f: // I-cache LRU etc. |
3260 |
case 0x76: // E-cache tag |
3261 |
case 0x7e: // E-cache tag |
3262 |
return;
|
3263 |
case 0x51: // I-MMU 8k TSB pointer, RO |
3264 |
case 0x52: // I-MMU 64k TSB pointer, RO |
3265 |
case 0x56: // I-MMU tag read, RO |
3266 |
case 0x59: // D-MMU 8k TSB pointer, RO |
3267 |
case 0x5a: // D-MMU 64k TSB pointer, RO |
3268 |
case 0x5b: // D-MMU data pointer, RO |
3269 |
case 0x5e: // D-MMU tag read, RO |
3270 |
case 0x48: // Interrupt dispatch, RO |
3271 |
case 0x7f: // Incoming interrupt vector, RO |
3272 |
case 0x82: // Primary no-fault, RO |
3273 |
case 0x83: // Secondary no-fault, RO |
3274 |
case 0x8a: // Primary no-fault LE, RO |
3275 |
case 0x8b: // Secondary no-fault LE, RO |
3276 |
default:
|
3277 |
do_unassigned_access(addr, 1, 0, 1, size); |
3278 |
return;
|
3279 |
} |
3280 |
} |
3281 |
#endif /* CONFIG_USER_ONLY */ |
3282 |
|
3283 |
void helper_ldda_asi(target_ulong addr, int asi, int rd) |
3284 |
{ |
3285 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
3286 |
|| (cpu_has_hypervisor(env) |
3287 |
&& asi >= 0x30 && asi < 0x80 |
3288 |
&& !(env->hpstate & HS_PRIV))) |
3289 |
raise_exception(TT_PRIV_ACT); |
3290 |
|
3291 |
addr = asi_address_mask(env, asi, addr); |
3292 |
|
3293 |
switch (asi) {
|
3294 |
#if !defined(CONFIG_USER_ONLY)
|
3295 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
3296 |
case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
3297 |
helper_check_align(addr, 0xf);
|
3298 |
if (rd == 0) { |
3299 |
env->gregs[1] = ldq_nucleus(addr + 8); |
3300 |
if (asi == 0x2c) |
3301 |
bswap64s(&env->gregs[1]);
|
3302 |
} else if (rd < 8) { |
3303 |
env->gregs[rd] = ldq_nucleus(addr); |
3304 |
env->gregs[rd + 1] = ldq_nucleus(addr + 8); |
3305 |
if (asi == 0x2c) { |
3306 |
bswap64s(&env->gregs[rd]); |
3307 |
bswap64s(&env->gregs[rd + 1]);
|
3308 |
} |
3309 |
} else {
|
3310 |
env->regwptr[rd] = ldq_nucleus(addr); |
3311 |
env->regwptr[rd + 1] = ldq_nucleus(addr + 8); |
3312 |
if (asi == 0x2c) { |
3313 |
bswap64s(&env->regwptr[rd]); |
3314 |
bswap64s(&env->regwptr[rd + 1]);
|
3315 |
} |
3316 |
} |
3317 |
break;
|
3318 |
#endif
|
3319 |
default:
|
3320 |
helper_check_align(addr, 0x3);
|
3321 |
if (rd == 0) |
3322 |
env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3323 |
else if (rd < 8) { |
3324 |
env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0); |
3325 |
env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3326 |
} else {
|
3327 |
env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0); |
3328 |
env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3329 |
} |
3330 |
break;
|
3331 |
} |
3332 |
} |
3333 |
|
3334 |
void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
3335 |
{ |
3336 |
unsigned int i; |
3337 |
CPU_DoubleU u; |
3338 |
|
3339 |
helper_check_align(addr, 3);
|
3340 |
addr = asi_address_mask(env, asi, addr); |
3341 |
|
3342 |
switch (asi) {
|
3343 |
case 0xf0: /* UA2007/JPS1 Block load primary */ |
3344 |
case 0xf1: /* UA2007/JPS1 Block load secondary */ |
3345 |
case 0xf8: /* UA2007/JPS1 Block load primary LE */ |
3346 |
case 0xf9: /* UA2007/JPS1 Block load secondary LE */ |
3347 |
if (rd & 7) { |
3348 |
raise_exception(TT_ILL_INSN); |
3349 |
return;
|
3350 |
} |
3351 |
helper_check_align(addr, 0x3f);
|
3352 |
for (i = 0; i < 16; i++) { |
3353 |
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, |
3354 |
0);
|
3355 |
addr += 4;
|
3356 |
} |
3357 |
|
3358 |
return;
|
3359 |
case 0x16: /* UA2007 Block load primary, user privilege */ |
3360 |
case 0x17: /* UA2007 Block load secondary, user privilege */ |
3361 |
case 0x1e: /* UA2007 Block load primary LE, user privilege */ |
3362 |
case 0x1f: /* UA2007 Block load secondary LE, user privilege */ |
3363 |
case 0x70: /* JPS1 Block load primary, user privilege */ |
3364 |
case 0x71: /* JPS1 Block load secondary, user privilege */ |
3365 |
case 0x78: /* JPS1 Block load primary LE, user privilege */ |
3366 |
case 0x79: /* JPS1 Block load secondary LE, user privilege */ |
3367 |
if (rd & 7) { |
3368 |
raise_exception(TT_ILL_INSN); |
3369 |
return;
|
3370 |
} |
3371 |
helper_check_align(addr, 0x3f);
|
3372 |
for (i = 0; i < 16; i++) { |
3373 |
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x19, 4, |
3374 |
0);
|
3375 |
addr += 4;
|
3376 |
} |
3377 |
|
3378 |
return;
|
3379 |
default:
|
3380 |
break;
|
3381 |
} |
3382 |
|
3383 |
switch(size) {
|
3384 |
default:
|
3385 |
case 4: |
3386 |
*((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
|
3387 |
break;
|
3388 |
case 8: |
3389 |
u.ll = helper_ld_asi(addr, asi, size, 0);
|
3390 |
*((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
3391 |
*((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
3392 |
break;
|
3393 |
case 16: |
3394 |
u.ll = helper_ld_asi(addr, asi, 8, 0); |
3395 |
*((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
3396 |
*((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
3397 |
u.ll = helper_ld_asi(addr + 8, asi, 8, 0); |
3398 |
*((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
3399 |
*((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
3400 |
break;
|
3401 |
} |
3402 |
} |
3403 |
|
3404 |
void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
3405 |
{ |
3406 |
unsigned int i; |
3407 |
target_ulong val = 0;
|
3408 |
CPU_DoubleU u; |
3409 |
|
3410 |
helper_check_align(addr, 3);
|
3411 |
addr = asi_address_mask(env, asi, addr); |
3412 |
|
3413 |
switch (asi) {
|
3414 |
case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */ |
3415 |
case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */ |
3416 |
case 0xf0: /* UA2007/JPS1 Block store primary */ |
3417 |
case 0xf1: /* UA2007/JPS1 Block store secondary */ |
3418 |
case 0xf8: /* UA2007/JPS1 Block store primary LE */ |
3419 |
case 0xf9: /* UA2007/JPS1 Block store secondary LE */ |
3420 |
if (rd & 7) { |
3421 |
raise_exception(TT_ILL_INSN); |
3422 |
return;
|
3423 |
} |
3424 |
helper_check_align(addr, 0x3f);
|
3425 |
for (i = 0; i < 16; i++) { |
3426 |
val = *(uint32_t *)&env->fpr[rd++]; |
3427 |
helper_st_asi(addr, val, asi & 0x8f, 4); |
3428 |
addr += 4;
|
3429 |
} |
3430 |
|
3431 |
return;
|
3432 |
case 0x16: /* UA2007 Block load primary, user privilege */ |
3433 |
case 0x17: /* UA2007 Block load secondary, user privilege */ |
3434 |
case 0x1e: /* UA2007 Block load primary LE, user privilege */ |
3435 |
case 0x1f: /* UA2007 Block load secondary LE, user privilege */ |
3436 |
case 0x70: /* JPS1 Block store primary, user privilege */ |
3437 |
case 0x71: /* JPS1 Block store secondary, user privilege */ |
3438 |
case 0x78: /* JPS1 Block load primary LE, user privilege */ |
3439 |
case 0x79: /* JPS1 Block load secondary LE, user privilege */ |
3440 |
if (rd & 7) { |
3441 |
raise_exception(TT_ILL_INSN); |
3442 |
return;
|
3443 |
} |
3444 |
helper_check_align(addr, 0x3f);
|
3445 |
for (i = 0; i < 16; i++) { |
3446 |
val = *(uint32_t *)&env->fpr[rd++]; |
3447 |
helper_st_asi(addr, val, asi & 0x19, 4); |
3448 |
addr += 4;
|
3449 |
} |
3450 |
|
3451 |
return;
|
3452 |
default:
|
3453 |
break;
|
3454 |
} |
3455 |
|
3456 |
switch(size) {
|
3457 |
default:
|
3458 |
case 4: |
3459 |
helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size); |
3460 |
break;
|
3461 |
case 8: |
3462 |
u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
3463 |
u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
3464 |
helper_st_asi(addr, u.ll, asi, size); |
3465 |
break;
|
3466 |
case 16: |
3467 |
u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
3468 |
u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
3469 |
helper_st_asi(addr, u.ll, asi, 8);
|
3470 |
u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
3471 |
u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
3472 |
helper_st_asi(addr + 8, u.ll, asi, 8); |
3473 |
break;
|
3474 |
} |
3475 |
} |
3476 |
|
3477 |
target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, |
3478 |
target_ulong val2, uint32_t asi) |
3479 |
{ |
3480 |
target_ulong ret; |
3481 |
|
3482 |
val2 &= 0xffffffffUL;
|
3483 |
ret = helper_ld_asi(addr, asi, 4, 0); |
3484 |
ret &= 0xffffffffUL;
|
3485 |
if (val2 == ret)
|
3486 |
helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4); |
3487 |
return ret;
|
3488 |
} |
3489 |
|
3490 |
target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
3491 |
target_ulong val2, uint32_t asi) |
3492 |
{ |
3493 |
target_ulong ret; |
3494 |
|
3495 |
ret = helper_ld_asi(addr, asi, 8, 0); |
3496 |
if (val2 == ret)
|
3497 |
helper_st_asi(addr, val1, asi, 8);
|
3498 |
return ret;
|
3499 |
} |
3500 |
#endif /* TARGET_SPARC64 */ |
3501 |
|
3502 |
#ifndef TARGET_SPARC64
|
3503 |
void helper_rett(void) |
3504 |
{ |
3505 |
unsigned int cwp; |
3506 |
|
3507 |
if (env->psret == 1) |
3508 |
raise_exception(TT_ILL_INSN); |
3509 |
|
3510 |
env->psret = 1;
|
3511 |
cwp = cwp_inc(env->cwp + 1) ;
|
3512 |
if (env->wim & (1 << cwp)) { |
3513 |
raise_exception(TT_WIN_UNF); |
3514 |
} |
3515 |
set_cwp(cwp); |
3516 |
env->psrs = env->psrps; |
3517 |
} |
3518 |
#endif
|
3519 |
|
3520 |
static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc) |
3521 |
{ |
3522 |
int overflow = 0; |
3523 |
uint64_t x0; |
3524 |
uint32_t x1; |
3525 |
|
3526 |
x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3527 |
x1 = (b & 0xffffffff);
|
3528 |
|
3529 |
if (x1 == 0) { |
3530 |
raise_exception(TT_DIV_ZERO); |
3531 |
} |
3532 |
|
3533 |
x0 = x0 / x1; |
3534 |
if (x0 > 0xffffffff) { |
3535 |
x0 = 0xffffffff;
|
3536 |
overflow = 1;
|
3537 |
} |
3538 |
|
3539 |
if (cc) {
|
3540 |
env->cc_dst = x0; |
3541 |
env->cc_src2 = overflow; |
3542 |
env->cc_op = CC_OP_DIV; |
3543 |
} |
3544 |
return x0;
|
3545 |
} |
3546 |
|
3547 |
target_ulong helper_udiv(target_ulong a, target_ulong b) |
3548 |
{ |
3549 |
return helper_udiv_common(a, b, 0); |
3550 |
} |
3551 |
|
3552 |
target_ulong helper_udiv_cc(target_ulong a, target_ulong b) |
3553 |
{ |
3554 |
return helper_udiv_common(a, b, 1); |
3555 |
} |
3556 |
|
3557 |
static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc) |
3558 |
{ |
3559 |
int overflow = 0; |
3560 |
int64_t x0; |
3561 |
int32_t x1; |
3562 |
|
3563 |
x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3564 |
x1 = (b & 0xffffffff);
|
3565 |
|
3566 |
if (x1 == 0) { |
3567 |
raise_exception(TT_DIV_ZERO); |
3568 |
} |
3569 |
|
3570 |
x0 = x0 / x1; |
3571 |
if ((int32_t) x0 != x0) {
|
3572 |
x0 = x0 < 0 ? 0x80000000: 0x7fffffff; |
3573 |
overflow = 1;
|
3574 |
} |
3575 |
|
3576 |
if (cc) {
|
3577 |
env->cc_dst = x0; |
3578 |
env->cc_src2 = overflow; |
3579 |
env->cc_op = CC_OP_DIV; |
3580 |
} |
3581 |
return x0;
|
3582 |
} |
3583 |
|
3584 |
target_ulong helper_sdiv(target_ulong a, target_ulong b) |
3585 |
{ |
3586 |
return helper_sdiv_common(a, b, 0); |
3587 |
} |
3588 |
|
3589 |
target_ulong helper_sdiv_cc(target_ulong a, target_ulong b) |
3590 |
{ |
3591 |
return helper_sdiv_common(a, b, 1); |
3592 |
} |
3593 |
|
3594 |
void helper_stdf(target_ulong addr, int mem_idx) |
3595 |
{ |
3596 |
helper_check_align(addr, 7);
|
3597 |
#if !defined(CONFIG_USER_ONLY)
|
3598 |
switch (mem_idx) {
|
3599 |
case MMU_USER_IDX:
|
3600 |
stfq_user(addr, DT0); |
3601 |
break;
|
3602 |
case MMU_KERNEL_IDX:
|
3603 |
stfq_kernel(addr, DT0); |
3604 |
break;
|
3605 |
#ifdef TARGET_SPARC64
|
3606 |
case MMU_HYPV_IDX:
|
3607 |
stfq_hypv(addr, DT0); |
3608 |
break;
|
3609 |
#endif
|
3610 |
default:
|
3611 |
DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
|
3612 |
break;
|
3613 |
} |
3614 |
#else
|
3615 |
stfq_raw(address_mask(env, addr), DT0); |
3616 |
#endif
|
3617 |
} |
3618 |
|
3619 |
void helper_lddf(target_ulong addr, int mem_idx) |
3620 |
{ |
3621 |
helper_check_align(addr, 7);
|
3622 |
#if !defined(CONFIG_USER_ONLY)
|
3623 |
switch (mem_idx) {
|
3624 |
case MMU_USER_IDX:
|
3625 |
DT0 = ldfq_user(addr); |
3626 |
break;
|
3627 |
case MMU_KERNEL_IDX:
|
3628 |
DT0 = ldfq_kernel(addr); |
3629 |
break;
|
3630 |
#ifdef TARGET_SPARC64
|
3631 |
case MMU_HYPV_IDX:
|
3632 |
DT0 = ldfq_hypv(addr); |
3633 |
break;
|
3634 |
#endif
|
3635 |
default:
|
3636 |
DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
|
3637 |
break;
|
3638 |
} |
3639 |
#else
|
3640 |
DT0 = ldfq_raw(address_mask(env, addr)); |
3641 |
#endif
|
3642 |
} |
3643 |
|
3644 |
void helper_ldqf(target_ulong addr, int mem_idx) |
3645 |
{ |
3646 |
// XXX add 128 bit load
|
3647 |
CPU_QuadU u; |
3648 |
|
3649 |
helper_check_align(addr, 7);
|
3650 |
#if !defined(CONFIG_USER_ONLY)
|
3651 |
switch (mem_idx) {
|
3652 |
case MMU_USER_IDX:
|
3653 |
u.ll.upper = ldq_user(addr); |
3654 |
u.ll.lower = ldq_user(addr + 8);
|
3655 |
QT0 = u.q; |
3656 |
break;
|
3657 |
case MMU_KERNEL_IDX:
|
3658 |
u.ll.upper = ldq_kernel(addr); |
3659 |
u.ll.lower = ldq_kernel(addr + 8);
|
3660 |
QT0 = u.q; |
3661 |
break;
|
3662 |
#ifdef TARGET_SPARC64
|
3663 |
case MMU_HYPV_IDX:
|
3664 |
u.ll.upper = ldq_hypv(addr); |
3665 |
u.ll.lower = ldq_hypv(addr + 8);
|
3666 |
QT0 = u.q; |
3667 |
break;
|
3668 |
#endif
|
3669 |
default:
|
3670 |
DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
|
3671 |
break;
|
3672 |
} |
3673 |
#else
|
3674 |
u.ll.upper = ldq_raw(address_mask(env, addr)); |
3675 |
u.ll.lower = ldq_raw(address_mask(env, addr + 8));
|
3676 |
QT0 = u.q; |
3677 |
#endif
|
3678 |
} |
3679 |
|
3680 |
void helper_stqf(target_ulong addr, int mem_idx) |
3681 |
{ |
3682 |
// XXX add 128 bit store
|
3683 |
CPU_QuadU u; |
3684 |
|
3685 |
helper_check_align(addr, 7);
|
3686 |
#if !defined(CONFIG_USER_ONLY)
|
3687 |
switch (mem_idx) {
|
3688 |
case MMU_USER_IDX:
|
3689 |
u.q = QT0; |
3690 |
stq_user(addr, u.ll.upper); |
3691 |
stq_user(addr + 8, u.ll.lower);
|
3692 |
break;
|
3693 |
case MMU_KERNEL_IDX:
|
3694 |
u.q = QT0; |
3695 |
stq_kernel(addr, u.ll.upper); |
3696 |
stq_kernel(addr + 8, u.ll.lower);
|
3697 |
break;
|
3698 |
#ifdef TARGET_SPARC64
|
3699 |
case MMU_HYPV_IDX:
|
3700 |
u.q = QT0; |
3701 |
stq_hypv(addr, u.ll.upper); |
3702 |
stq_hypv(addr + 8, u.ll.lower);
|
3703 |
break;
|
3704 |
#endif
|
3705 |
default:
|
3706 |
DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
|
3707 |
break;
|
3708 |
} |
3709 |
#else
|
3710 |
u.q = QT0; |
3711 |
stq_raw(address_mask(env, addr), u.ll.upper); |
3712 |
stq_raw(address_mask(env, addr + 8), u.ll.lower);
|
3713 |
#endif
|
3714 |
} |
3715 |
|
3716 |
static inline void set_fsr(void) |
3717 |
{ |
3718 |
int rnd_mode;
|
3719 |
|
3720 |
switch (env->fsr & FSR_RD_MASK) {
|
3721 |
case FSR_RD_NEAREST:
|
3722 |
rnd_mode = float_round_nearest_even; |
3723 |
break;
|
3724 |
default:
|
3725 |
case FSR_RD_ZERO:
|
3726 |
rnd_mode = float_round_to_zero; |
3727 |
break;
|
3728 |
case FSR_RD_POS:
|
3729 |
rnd_mode = float_round_up; |
3730 |
break;
|
3731 |
case FSR_RD_NEG:
|
3732 |
rnd_mode = float_round_down; |
3733 |
break;
|
3734 |
} |
3735 |
set_float_rounding_mode(rnd_mode, &env->fp_status); |
3736 |
} |
3737 |
|
3738 |
void helper_ldfsr(uint32_t new_fsr)
|
3739 |
{ |
3740 |
env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK); |
3741 |
set_fsr(); |
3742 |
} |
3743 |
|
3744 |
#ifdef TARGET_SPARC64
|
3745 |
void helper_ldxfsr(uint64_t new_fsr)
|
3746 |
{ |
3747 |
env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK); |
3748 |
set_fsr(); |
3749 |
} |
3750 |
#endif
|
3751 |
|
3752 |
void helper_debug(void) |
3753 |
{ |
3754 |
env->exception_index = EXCP_DEBUG; |
3755 |
cpu_loop_exit(env); |
3756 |
} |
3757 |
|
3758 |
#ifndef TARGET_SPARC64
|
3759 |
/* XXX: use another pointer for %iN registers to avoid slow wrapping
|
3760 |
handling ? */
|
3761 |
void helper_save(void) |
3762 |
{ |
3763 |
uint32_t cwp; |
3764 |
|
3765 |
cwp = cwp_dec(env->cwp - 1);
|
3766 |
if (env->wim & (1 << cwp)) { |
3767 |
raise_exception(TT_WIN_OVF); |
3768 |
} |
3769 |
set_cwp(cwp); |
3770 |
} |
3771 |
|
3772 |
void helper_restore(void) |
3773 |
{ |
3774 |
uint32_t cwp; |
3775 |
|
3776 |
cwp = cwp_inc(env->cwp + 1);
|
3777 |
if (env->wim & (1 << cwp)) { |
3778 |
raise_exception(TT_WIN_UNF); |
3779 |
} |
3780 |
set_cwp(cwp); |
3781 |
} |
3782 |
|
3783 |
void helper_wrpsr(target_ulong new_psr)
|
3784 |
{ |
3785 |
if ((new_psr & PSR_CWP) >= env->nwindows) {
|
3786 |
raise_exception(TT_ILL_INSN); |
3787 |
} else {
|
3788 |
cpu_put_psr(env, new_psr); |
3789 |
} |
3790 |
} |
3791 |
|
3792 |
target_ulong helper_rdpsr(void)
|
3793 |
{ |
3794 |
return get_psr();
|
3795 |
} |
3796 |
|
3797 |
#else
|
3798 |
/* XXX: use another pointer for %iN registers to avoid slow wrapping
|
3799 |
handling ? */
|
3800 |
void helper_save(void) |
3801 |
{ |
3802 |
uint32_t cwp; |
3803 |
|
3804 |
cwp = cwp_dec(env->cwp - 1);
|
3805 |
if (env->cansave == 0) { |
3806 |
raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
3807 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3808 |
((env->wstate & 0x7) << 2))); |
3809 |
} else {
|
3810 |
if (env->cleanwin - env->canrestore == 0) { |
3811 |
// XXX Clean windows without trap
|
3812 |
raise_exception(TT_CLRWIN); |
3813 |
} else {
|
3814 |
env->cansave--; |
3815 |
env->canrestore++; |
3816 |
set_cwp(cwp); |
3817 |
} |
3818 |
} |
3819 |
} |
3820 |
|
3821 |
void helper_restore(void) |
3822 |
{ |
3823 |
uint32_t cwp; |
3824 |
|
3825 |
cwp = cwp_inc(env->cwp + 1);
|
3826 |
if (env->canrestore == 0) { |
3827 |
raise_exception(TT_FILL | (env->otherwin != 0 ?
|
3828 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3829 |
((env->wstate & 0x7) << 2))); |
3830 |
} else {
|
3831 |
env->cansave++; |
3832 |
env->canrestore--; |
3833 |
set_cwp(cwp); |
3834 |
} |
3835 |
} |
3836 |
|
3837 |
void helper_flushw(void) |
3838 |
{ |
3839 |
if (env->cansave != env->nwindows - 2) { |
3840 |
raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
3841 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3842 |
((env->wstate & 0x7) << 2))); |
3843 |
} |
3844 |
} |
3845 |
|
3846 |
void helper_saved(void) |
3847 |
{ |
3848 |
env->cansave++; |
3849 |
if (env->otherwin == 0) |
3850 |
env->canrestore--; |
3851 |
else
|
3852 |
env->otherwin--; |
3853 |
} |
3854 |
|
3855 |
void helper_restored(void) |
3856 |
{ |
3857 |
env->canrestore++; |
3858 |
if (env->cleanwin < env->nwindows - 1) |
3859 |
env->cleanwin++; |
3860 |
if (env->otherwin == 0) |
3861 |
env->cansave--; |
3862 |
else
|
3863 |
env->otherwin--; |
3864 |
} |
3865 |
|
3866 |
static target_ulong get_ccr(void) |
3867 |
{ |
3868 |
target_ulong psr; |
3869 |
|
3870 |
psr = get_psr(); |
3871 |
|
3872 |
return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20); |
3873 |
} |
3874 |
|
3875 |
target_ulong cpu_get_ccr(CPUState *env1) |
3876 |
{ |
3877 |
CPUState *saved_env; |
3878 |
target_ulong ret; |
3879 |
|
3880 |
saved_env = env; |
3881 |
env = env1; |
3882 |
ret = get_ccr(); |
3883 |
env = saved_env; |
3884 |
return ret;
|
3885 |
} |
3886 |
|
3887 |
static void put_ccr(target_ulong val) |
3888 |
{ |
3889 |
target_ulong tmp = val; |
3890 |
|
3891 |
env->xcc = (tmp >> 4) << 20; |
3892 |
env->psr = (tmp & 0xf) << 20; |
3893 |
CC_OP = CC_OP_FLAGS; |
3894 |
} |
3895 |
|
3896 |
void cpu_put_ccr(CPUState *env1, target_ulong val)
|
3897 |
{ |
3898 |
CPUState *saved_env; |
3899 |
|
3900 |
saved_env = env; |
3901 |
env = env1; |
3902 |
put_ccr(val); |
3903 |
env = saved_env; |
3904 |
} |
3905 |
|
3906 |
static target_ulong get_cwp64(void) |
3907 |
{ |
3908 |
return env->nwindows - 1 - env->cwp; |
3909 |
} |
3910 |
|
3911 |
target_ulong cpu_get_cwp64(CPUState *env1) |
3912 |
{ |
3913 |
CPUState *saved_env; |
3914 |
target_ulong ret; |
3915 |
|
3916 |
saved_env = env; |
3917 |
env = env1; |
3918 |
ret = get_cwp64(); |
3919 |
env = saved_env; |
3920 |
return ret;
|
3921 |
} |
3922 |
|
3923 |
static void put_cwp64(int cwp) |
3924 |
{ |
3925 |
if (unlikely(cwp >= env->nwindows || cwp < 0)) { |
3926 |
cwp %= env->nwindows; |
3927 |
} |
3928 |
set_cwp(env->nwindows - 1 - cwp);
|
3929 |
} |
3930 |
|
3931 |
void cpu_put_cwp64(CPUState *env1, int cwp) |
3932 |
{ |
3933 |
CPUState *saved_env; |
3934 |
|
3935 |
saved_env = env; |
3936 |
env = env1; |
3937 |
put_cwp64(cwp); |
3938 |
env = saved_env; |
3939 |
} |
3940 |
|
3941 |
target_ulong helper_rdccr(void)
|
3942 |
{ |
3943 |
return get_ccr();
|
3944 |
} |
3945 |
|
3946 |
void helper_wrccr(target_ulong new_ccr)
|
3947 |
{ |
3948 |
put_ccr(new_ccr); |
3949 |
} |
3950 |
|
3951 |
// CWP handling is reversed in V9, but we still use the V8 register
|
3952 |
// order.
|
3953 |
target_ulong helper_rdcwp(void)
|
3954 |
{ |
3955 |
return get_cwp64();
|
3956 |
} |
3957 |
|
3958 |
void helper_wrcwp(target_ulong new_cwp)
|
3959 |
{ |
3960 |
put_cwp64(new_cwp); |
3961 |
} |
3962 |
|
3963 |
// This function uses non-native bit order
|
3964 |
#define GET_FIELD(X, FROM, TO) \
|
3965 |
((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) |
3966 |
|
3967 |
// This function uses the order in the manuals, i.e. bit 0 is 2^0
|
3968 |
#define GET_FIELD_SP(X, FROM, TO) \
|
3969 |
GET_FIELD(X, 63 - (TO), 63 - (FROM)) |
3970 |
|
3971 |
target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) |
3972 |
{ |
3973 |
return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) | |
3974 |
(GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) | |
3975 |
(GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) | |
3976 |
(GET_FIELD_SP(pixel_addr, 56, 59) << 13) | |
3977 |
(GET_FIELD_SP(pixel_addr, 35, 38) << 9) | |
3978 |
(GET_FIELD_SP(pixel_addr, 13, 16) << 5) | |
3979 |
(((pixel_addr >> 55) & 1) << 4) | |
3980 |
(GET_FIELD_SP(pixel_addr, 33, 34) << 2) | |
3981 |
GET_FIELD_SP(pixel_addr, 11, 12); |
3982 |
} |
3983 |
|
3984 |
target_ulong helper_alignaddr(target_ulong addr, target_ulong offset) |
3985 |
{ |
3986 |
uint64_t tmp; |
3987 |
|
3988 |
tmp = addr + offset; |
3989 |
env->gsr &= ~7ULL;
|
3990 |
env->gsr |= tmp & 7ULL;
|
3991 |
return tmp & ~7ULL; |
3992 |
} |
3993 |
|
3994 |
target_ulong helper_popc(target_ulong val) |
3995 |
{ |
3996 |
return ctpop64(val);
|
3997 |
} |
3998 |
|
3999 |
static inline uint64_t *get_gregset(uint32_t pstate) |
4000 |
{ |
4001 |
switch (pstate) {
|
4002 |
default:
|
4003 |
DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
|
4004 |
pstate, |
4005 |
(pstate & PS_IG) ? " IG" : "", |
4006 |
(pstate & PS_MG) ? " MG" : "", |
4007 |
(pstate & PS_AG) ? " AG" : ""); |
4008 |
/* pass through to normal set of global registers */
|
4009 |
case 0: |
4010 |
return env->bgregs;
|
4011 |
case PS_AG:
|
4012 |
return env->agregs;
|
4013 |
case PS_MG:
|
4014 |
return env->mgregs;
|
4015 |
case PS_IG:
|
4016 |
return env->igregs;
|
4017 |
} |
4018 |
} |
4019 |
|
4020 |
static inline void change_pstate(uint32_t new_pstate) |
4021 |
{ |
4022 |
uint32_t pstate_regs, new_pstate_regs; |
4023 |
uint64_t *src, *dst; |
4024 |
|
4025 |
if (env->def->features & CPU_FEATURE_GL) {
|
4026 |
// PS_AG is not implemented in this case
|
4027 |
new_pstate &= ~PS_AG; |
4028 |
} |
4029 |
|
4030 |
pstate_regs = env->pstate & 0xc01;
|
4031 |
new_pstate_regs = new_pstate & 0xc01;
|
4032 |
|
4033 |
if (new_pstate_regs != pstate_regs) {
|
4034 |
DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
|
4035 |
pstate_regs, new_pstate_regs); |
4036 |
// Switch global register bank
|
4037 |
src = get_gregset(new_pstate_regs); |
4038 |
dst = get_gregset(pstate_regs); |
4039 |
memcpy32(dst, env->gregs); |
4040 |
memcpy32(env->gregs, src); |
4041 |
} |
4042 |
else {
|
4043 |
DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
|
4044 |
new_pstate_regs); |
4045 |
} |
4046 |
env->pstate = new_pstate; |
4047 |
} |
4048 |
|
4049 |
void helper_wrpstate(target_ulong new_state)
|
4050 |
{ |
4051 |
change_pstate(new_state & 0xf3f);
|
4052 |
|
4053 |
#if !defined(CONFIG_USER_ONLY)
|
4054 |
if (cpu_interrupts_enabled(env)) {
|
4055 |
cpu_check_irqs(env); |
4056 |
} |
4057 |
#endif
|
4058 |
} |
4059 |
|
4060 |
void cpu_change_pstate(CPUState *env1, uint32_t new_pstate)
|
4061 |
{ |
4062 |
CPUState *saved_env; |
4063 |
|
4064 |
saved_env = env; |
4065 |
env = env1; |
4066 |
change_pstate(new_pstate); |
4067 |
env = saved_env; |
4068 |
} |
4069 |
|
4070 |
void helper_wrpil(target_ulong new_pil)
|
4071 |
{ |
4072 |
#if !defined(CONFIG_USER_ONLY)
|
4073 |
DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
|
4074 |
env->psrpil, (uint32_t)new_pil); |
4075 |
|
4076 |
env->psrpil = new_pil; |
4077 |
|
4078 |
if (cpu_interrupts_enabled(env)) {
|
4079 |
cpu_check_irqs(env); |
4080 |
} |
4081 |
#endif
|
4082 |
} |
4083 |
|
4084 |
void helper_done(void) |
4085 |
{ |
4086 |
trap_state* tsptr = cpu_tsptr(env); |
4087 |
|
4088 |
env->pc = tsptr->tnpc; |
4089 |
env->npc = tsptr->tnpc + 4;
|
4090 |
put_ccr(tsptr->tstate >> 32);
|
4091 |
env->asi = (tsptr->tstate >> 24) & 0xff; |
4092 |
change_pstate((tsptr->tstate >> 8) & 0xf3f); |
4093 |
put_cwp64(tsptr->tstate & 0xff);
|
4094 |
env->tl--; |
4095 |
|
4096 |
DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
|
4097 |
|
4098 |
#if !defined(CONFIG_USER_ONLY)
|
4099 |
if (cpu_interrupts_enabled(env)) {
|
4100 |
cpu_check_irqs(env); |
4101 |
} |
4102 |
#endif
|
4103 |
} |
4104 |
|
4105 |
void helper_retry(void) |
4106 |
{ |
4107 |
trap_state* tsptr = cpu_tsptr(env); |
4108 |
|
4109 |
env->pc = tsptr->tpc; |
4110 |
env->npc = tsptr->tnpc; |
4111 |
put_ccr(tsptr->tstate >> 32);
|
4112 |
env->asi = (tsptr->tstate >> 24) & 0xff; |
4113 |
change_pstate((tsptr->tstate >> 8) & 0xf3f); |
4114 |
put_cwp64(tsptr->tstate & 0xff);
|
4115 |
env->tl--; |
4116 |
|
4117 |
DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
|
4118 |
|
4119 |
#if !defined(CONFIG_USER_ONLY)
|
4120 |
if (cpu_interrupts_enabled(env)) {
|
4121 |
cpu_check_irqs(env); |
4122 |
} |
4123 |
#endif
|
4124 |
} |
4125 |
|
4126 |
static void do_modify_softint(const char* operation, uint32_t value) |
4127 |
{ |
4128 |
if (env->softint != value) {
|
4129 |
env->softint = value; |
4130 |
DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
|
4131 |
#if !defined(CONFIG_USER_ONLY)
|
4132 |
if (cpu_interrupts_enabled(env)) {
|
4133 |
cpu_check_irqs(env); |
4134 |
} |
4135 |
#endif
|
4136 |
} |
4137 |
} |
4138 |
|
4139 |
void helper_set_softint(uint64_t value)
|
4140 |
{ |
4141 |
do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
|
4142 |
} |
4143 |
|
4144 |
void helper_clear_softint(uint64_t value)
|
4145 |
{ |
4146 |
do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
|
4147 |
} |
4148 |
|
4149 |
void helper_write_softint(uint64_t value)
|
4150 |
{ |
4151 |
do_modify_softint("helper_write_softint", (uint32_t)value);
|
4152 |
} |
4153 |
#endif
|
4154 |
|
4155 |
#ifdef TARGET_SPARC64
|
4156 |
trap_state* cpu_tsptr(CPUState* env) |
4157 |
{ |
4158 |
return &env->ts[env->tl & MAXTL_MASK];
|
4159 |
} |
4160 |
#endif
|
4161 |
|
4162 |
#if !defined(CONFIG_USER_ONLY)
|
4163 |
|
4164 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4165 |
void *retaddr);
|
4166 |
|
4167 |
#define MMUSUFFIX _mmu
|
4168 |
#define ALIGNED_ONLY
|
4169 |
|
4170 |
#define SHIFT 0 |
4171 |
#include "softmmu_template.h" |
4172 |
|
4173 |
#define SHIFT 1 |
4174 |
#include "softmmu_template.h" |
4175 |
|
4176 |
#define SHIFT 2 |
4177 |
#include "softmmu_template.h" |
4178 |
|
4179 |
#define SHIFT 3 |
4180 |
#include "softmmu_template.h" |
4181 |
|
4182 |
/* XXX: make it generic ? */
|
4183 |
static void cpu_restore_state2(void *retaddr) |
4184 |
{ |
4185 |
TranslationBlock *tb; |
4186 |
unsigned long pc; |
4187 |
|
4188 |
if (retaddr) {
|
4189 |
/* now we have a real cpu fault */
|
4190 |
pc = (unsigned long)retaddr; |
4191 |
tb = tb_find_pc(pc); |
4192 |
if (tb) {
|
4193 |
/* the PC is inside the translated code. It means that we have
|
4194 |
a virtual CPU fault */
|
4195 |
cpu_restore_state(tb, env, pc); |
4196 |
} |
4197 |
} |
4198 |
} |
4199 |
|
4200 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4201 |
void *retaddr)
|
4202 |
{ |
4203 |
#ifdef DEBUG_UNALIGNED
|
4204 |
printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
4205 |
"\n", addr, env->pc);
|
4206 |
#endif
|
4207 |
cpu_restore_state2(retaddr); |
4208 |
raise_exception(TT_UNALIGNED); |
4209 |
} |
4210 |
|
4211 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
4212 |
NULL, it means that the function was called in C code (i.e. not
|
4213 |
from generated code or from helper.c) */
|
4214 |
/* XXX: fix it to restore all registers */
|
4215 |
void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
4216 |
{ |
4217 |
int ret;
|
4218 |
CPUState *saved_env; |
4219 |
|
4220 |
/* XXX: hack to restore env in all cases, even if not called from
|
4221 |
generated code */
|
4222 |
saved_env = env; |
4223 |
env = cpu_single_env; |
4224 |
|
4225 |
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
4226 |
if (ret) {
|
4227 |
cpu_restore_state2(retaddr); |
4228 |
cpu_loop_exit(env); |
4229 |
} |
4230 |
env = saved_env; |
4231 |
} |
4232 |
|
4233 |
#endif /* !CONFIG_USER_ONLY */ |
4234 |
|
4235 |
#ifndef TARGET_SPARC64
|
4236 |
#if !defined(CONFIG_USER_ONLY)
|
4237 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
4238 |
int is_asi, int size) |
4239 |
{ |
4240 |
CPUState *saved_env; |
4241 |
int fault_type;
|
4242 |
|
4243 |
/* XXX: hack to restore env in all cases, even if not called from
|
4244 |
generated code */
|
4245 |
saved_env = env; |
4246 |
env = cpu_single_env; |
4247 |
#ifdef DEBUG_UNASSIGNED
|
4248 |
if (is_asi)
|
4249 |
printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
4250 |
" asi 0x%02x from " TARGET_FMT_lx "\n", |
4251 |
is_exec ? "exec" : is_write ? "write" : "read", size, |
4252 |
size == 1 ? "" : "s", addr, is_asi, env->pc); |
4253 |
else
|
4254 |
printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
4255 |
" from " TARGET_FMT_lx "\n", |
4256 |
is_exec ? "exec" : is_write ? "write" : "read", size, |
4257 |
size == 1 ? "" : "s", addr, env->pc); |
4258 |
#endif
|
4259 |
/* Don't overwrite translation and access faults */
|
4260 |
fault_type = (env->mmuregs[3] & 0x1c) >> 2; |
4261 |
if ((fault_type > 4) || (fault_type == 0)) { |
4262 |
env->mmuregs[3] = 0; /* Fault status register */ |
4263 |
if (is_asi)
|
4264 |
env->mmuregs[3] |= 1 << 16; |
4265 |
if (env->psrs)
|
4266 |
env->mmuregs[3] |= 1 << 5; |
4267 |
if (is_exec)
|
4268 |
env->mmuregs[3] |= 1 << 6; |
4269 |
if (is_write)
|
4270 |
env->mmuregs[3] |= 1 << 7; |
4271 |
env->mmuregs[3] |= (5 << 2) | 2; |
4272 |
/* SuperSPARC will never place instruction fault addresses in the FAR */
|
4273 |
if (!is_exec) {
|
4274 |
env->mmuregs[4] = addr; /* Fault address register */ |
4275 |
} |
4276 |
} |
4277 |
/* overflow (same type fault was not read before another fault) */
|
4278 |
if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { |
4279 |
env->mmuregs[3] |= 1; |
4280 |
} |
4281 |
|
4282 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
4283 |
if (is_exec)
|
4284 |
raise_exception(TT_CODE_ACCESS); |
4285 |
else
|
4286 |
raise_exception(TT_DATA_ACCESS); |
4287 |
} |
4288 |
|
4289 |
/* flush neverland mappings created during no-fault mode,
|
4290 |
so the sequential MMU faults report proper fault types */
|
4291 |
if (env->mmuregs[0] & MMU_NF) { |
4292 |
tlb_flush(env, 1);
|
4293 |
} |
4294 |
|
4295 |
env = saved_env; |
4296 |
} |
4297 |
#endif
|
4298 |
#else
|
4299 |
#if defined(CONFIG_USER_ONLY)
|
4300 |
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
4301 |
int is_asi, int size) |
4302 |
#else
|
4303 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
4304 |
int is_asi, int size) |
4305 |
#endif
|
4306 |
{ |
4307 |
CPUState *saved_env; |
4308 |
|
4309 |
/* XXX: hack to restore env in all cases, even if not called from
|
4310 |
generated code */
|
4311 |
saved_env = env; |
4312 |
env = cpu_single_env; |
4313 |
|
4314 |
#ifdef DEBUG_UNASSIGNED
|
4315 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
4316 |
"\n", addr, env->pc);
|
4317 |
#endif
|
4318 |
|
4319 |
if (is_exec)
|
4320 |
raise_exception(TT_CODE_ACCESS); |
4321 |
else
|
4322 |
raise_exception(TT_DATA_ACCESS); |
4323 |
|
4324 |
env = saved_env; |
4325 |
} |
4326 |
#endif
|
4327 |
|
4328 |
|
4329 |
#ifdef TARGET_SPARC64
|
4330 |
void helper_tick_set_count(void *opaque, uint64_t count) |
4331 |
{ |
4332 |
#if !defined(CONFIG_USER_ONLY)
|
4333 |
cpu_tick_set_count(opaque, count); |
4334 |
#endif
|
4335 |
} |
4336 |
|
4337 |
uint64_t helper_tick_get_count(void *opaque)
|
4338 |
{ |
4339 |
#if !defined(CONFIG_USER_ONLY)
|
4340 |
return cpu_tick_get_count(opaque);
|
4341 |
#else
|
4342 |
return 0; |
4343 |
#endif
|
4344 |
} |
4345 |
|
4346 |
void helper_tick_set_limit(void *opaque, uint64_t limit) |
4347 |
{ |
4348 |
#if !defined(CONFIG_USER_ONLY)
|
4349 |
cpu_tick_set_limit(opaque, limit); |
4350 |
#endif
|
4351 |
} |
4352 |
#endif
|