Revision afcea8cb hw/isa_mmio.c
| b/hw/isa_mmio.c | ||
|---|---|---|
| 28 | 28 |
static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr, |
| 29 | 29 |
uint32_t val) |
| 30 | 30 |
{
|
| 31 |
cpu_outb(NULL, addr & IOPORTS_MASK, val);
|
|
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cpu_outb(addr & IOPORTS_MASK, val); |
|
| 32 | 32 |
} |
| 33 | 33 |
|
| 34 | 34 |
static void isa_mmio_writew (void *opaque, target_phys_addr_t addr, |
| ... | ... | |
| 37 | 37 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 38 | 38 |
val = bswap16(val); |
| 39 | 39 |
#endif |
| 40 |
cpu_outw(NULL, addr & IOPORTS_MASK, val);
|
|
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cpu_outw(addr & IOPORTS_MASK, val); |
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| 41 | 41 |
} |
| 42 | 42 |
|
| 43 | 43 |
static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, |
| ... | ... | |
| 46 | 46 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 47 | 47 |
val = bswap32(val); |
| 48 | 48 |
#endif |
| 49 |
cpu_outl(NULL, addr & IOPORTS_MASK, val);
|
|
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cpu_outl(addr & IOPORTS_MASK, val); |
|
| 50 | 50 |
} |
| 51 | 51 |
|
| 52 | 52 |
static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) |
| 53 | 53 |
{
|
| 54 | 54 |
uint32_t val; |
| 55 | 55 |
|
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val = cpu_inb(NULL, addr & IOPORTS_MASK);
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val = cpu_inb(addr & IOPORTS_MASK); |
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| 57 | 57 |
return val; |
| 58 | 58 |
} |
| 59 | 59 |
|
| ... | ... | |
| 61 | 61 |
{
|
| 62 | 62 |
uint32_t val; |
| 63 | 63 |
|
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val = cpu_inw(NULL, addr & IOPORTS_MASK);
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|
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val = cpu_inw(addr & IOPORTS_MASK); |
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| 65 | 65 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 66 | 66 |
val = bswap16(val); |
| 67 | 67 |
#endif |
| ... | ... | |
| 72 | 72 |
{
|
| 73 | 73 |
uint32_t val; |
| 74 | 74 |
|
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val = cpu_inl(NULL, addr & IOPORTS_MASK);
|
|
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val = cpu_inl(addr & IOPORTS_MASK); |
|
| 76 | 76 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 77 | 77 |
val = bswap32(val); |
| 78 | 78 |
#endif |
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