root / target-arm / exec.h @ b0109805
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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM execution defines
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 8294eba1 | ths | #include "config.h" |
21 | 2c0262af | bellard | #include "dyngen-exec.h" |
22 | 2c0262af | bellard | |
23 | 2c0262af | bellard | register struct CPUARMState *env asm(AREG0); |
24 | 2c0262af | bellard | register uint32_t T0 asm(AREG1); |
25 | 2c0262af | bellard | register uint32_t T1 asm(AREG2); |
26 | 2c0262af | bellard | register uint32_t T2 asm(AREG3); |
27 | 2c0262af | bellard | |
28 | b7bcbe95 | bellard | /* TODO: Put these in FP regs on targets that have such things. */
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29 | b7bcbe95 | bellard | /* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */
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30 | b7bcbe95 | bellard | #define FT0s env->vfp.tmp0s
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31 | b7bcbe95 | bellard | #define FT1s env->vfp.tmp1s
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32 | b7bcbe95 | bellard | #define FT0d env->vfp.tmp0d
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33 | b7bcbe95 | bellard | #define FT1d env->vfp.tmp1d
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34 | b7bcbe95 | bellard | |
35 | 18c9b560 | balrog | #define M0 env->iwmmxt.val
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36 | 18c9b560 | balrog | |
37 | 2c0262af | bellard | #include "cpu.h" |
38 | 2c0262af | bellard | #include "exec-all.h" |
39 | 2c0262af | bellard | |
40 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
41 | 0d1a29f9 | bellard | { |
42 | 0d1a29f9 | bellard | } |
43 | 0d1a29f9 | bellard | |
44 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
45 | 0d1a29f9 | bellard | { |
46 | 0d1a29f9 | bellard | } |
47 | b8a9e8f1 | bellard | |
48 | b8a9e8f1 | bellard | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
49 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
50 | b7bcbe95 | bellard | |
51 | bfed01fc | ths | static inline int cpu_halted(CPUState *env) { |
52 | bfed01fc | ths | if (!env->halted)
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53 | bfed01fc | ths | return 0; |
54 | bfed01fc | ths | /* An interrupt wakes the CPU even if the I and F CPSR bits are
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55 | bfed01fc | ths | set. We use EXITTB to silently wake CPU without causing an
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56 | bfed01fc | ths | actual interrupt. */
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57 | bfed01fc | ths | if (env->interrupt_request &
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58 | bfed01fc | ths | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) { |
59 | bfed01fc | ths | env->halted = 0;
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60 | bfed01fc | ths | return 0; |
61 | bfed01fc | ths | } |
62 | bfed01fc | ths | return EXCP_HALTED;
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63 | bfed01fc | ths | } |
64 | bfed01fc | ths | |
65 | b5ff1b31 | bellard | #if !defined(CONFIG_USER_ONLY)
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66 | b5ff1b31 | bellard | #include "softmmu_exec.h" |
67 | b5ff1b31 | bellard | #endif
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68 | b5ff1b31 | bellard | |
69 | b7bcbe95 | bellard | /* In op_helper.c */
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70 | b7bcbe95 | bellard | |
71 | c1713132 | balrog | void helper_set_cp(CPUState *, uint32_t, uint32_t);
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72 | c1713132 | balrog | uint32_t helper_get_cp(CPUState *, uint32_t); |
73 | b5ff1b31 | bellard | void helper_set_cp15(CPUState *, uint32_t, uint32_t);
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74 | b5ff1b31 | bellard | uint32_t helper_get_cp15(CPUState *, uint32_t); |
75 | 9ee6e8bb | pbrook | uint32_t helper_v7m_mrs(CPUState *env, int reg);
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76 | 9ee6e8bb | pbrook | void helper_v7m_msr(CPUState *env, int reg, uint32_t val); |
77 | 9ee6e8bb | pbrook | |
78 | 9ee6e8bb | pbrook | void helper_mark_exclusive(CPUARMState *, uint32_t addr);
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79 | 9ee6e8bb | pbrook | int helper_test_exclusive(CPUARMState *, uint32_t addr);
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80 | 9ee6e8bb | pbrook | void helper_clrex(CPUARMState *env);
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81 | b5ff1b31 | bellard | |
82 | b7bcbe95 | bellard | void cpu_loop_exit(void); |
83 | b7bcbe95 | bellard | |
84 | b7bcbe95 | bellard | void raise_exception(int); |
85 | b7bcbe95 | bellard | |
86 | b7bcbe95 | bellard | void do_vfp_abss(void); |
87 | b7bcbe95 | bellard | void do_vfp_absd(void); |
88 | b7bcbe95 | bellard | void do_vfp_negs(void); |
89 | b7bcbe95 | bellard | void do_vfp_negd(void); |
90 | b7bcbe95 | bellard | void do_vfp_sqrts(void); |
91 | b7bcbe95 | bellard | void do_vfp_sqrtd(void); |
92 | b7bcbe95 | bellard | void do_vfp_cmps(void); |
93 | b7bcbe95 | bellard | void do_vfp_cmpd(void); |
94 | b7bcbe95 | bellard | void do_vfp_cmpes(void); |
95 | b7bcbe95 | bellard | void do_vfp_cmped(void); |
96 | b7bcbe95 | bellard | void do_vfp_set_fpscr(void); |
97 | b7bcbe95 | bellard | void do_vfp_get_fpscr(void); |
98 | 9ee6e8bb | pbrook | float32 helper_recps_f32(float32, float32); |
99 | 9ee6e8bb | pbrook | float32 helper_rsqrts_f32(float32, float32); |
100 | 9ee6e8bb | pbrook | uint32_t helper_recpe_u32(uint32_t); |
101 | 9ee6e8bb | pbrook | uint32_t helper_rsqrte_u32(uint32_t); |
102 | 9ee6e8bb | pbrook | float32 helper_recpe_f32(float32); |
103 | 9ee6e8bb | pbrook | float32 helper_rsqrte_f32(float32); |
104 | 9ee6e8bb | pbrook | void helper_neon_tbl(int rn, int maxindex); |
105 | 9ee6e8bb | pbrook | uint32_t helper_neon_mul_p8(uint32_t op1, uint32_t op2); |