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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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#ifndef CONFIG_NO_DYNGEN_OP
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/* legacy dyngen operations */
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#include "gen-op.h"
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#endif
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int gen_new_label(void);
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static inline void tcg_gen_op1(int opc, TCGv arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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}
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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}
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                               TCGv arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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}
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                                TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, 
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                                 TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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}
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, 
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                                TCGv arg3, TCGv arg4,
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                                TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5, TCGv arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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    *gen_opparam_ptr++ = GET_TCGV(arg6);
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}
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, 
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                                 TCGv arg3, TCGv arg4,
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                                 TCGArg arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_br(int label)
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{
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    tcg_gen_op1i(INDEX_op_br, label);
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}
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg)
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{
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    tcg_gen_op2(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg)
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{
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    tcg_gen_op2i(INDEX_op_movi_i32, ret, arg);
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}
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0
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static inline void tcg_gen_helper_0_0(void *func)
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{
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 0, NULL);
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}
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 1, &arg);
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}
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 2, args);
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}
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static inline void tcg_gen_helper_0_3(void *func,
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                                      TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    TCGv args[3];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 3, args);
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}
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static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2,
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                                      TCGv arg3, TCGv arg4)
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{
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    TCGv args[4];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 4, args);
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}
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static inline void tcg_gen_helper_1_0(void *func, TCGv ret)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 0, NULL);
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}
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static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 1, &arg1);
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}
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, 
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                                      TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 2, args);
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}
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static inline void tcg_gen_helper_1_3(void *func, TCGv ret,
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                                      TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    TCGv args[3];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 3, args);
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}
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static inline void tcg_gen_helper_1_4(void *func, TCGv ret,
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                                      TCGv arg1, TCGv arg2, TCGv arg3,
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                                      TCGv arg4)
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{
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    TCGv args[4];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 4, args);
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}
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_movi_i32(ret, 0);
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    } else if (arg2 == 0xffffffff) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
366 c896fe29 bellard
367 ac56dd48 pbrook
static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2)
368 c896fe29 bellard
{
369 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2);
370 c896fe29 bellard
}
371 c896fe29 bellard
372 ac56dd48 pbrook
static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2)
373 c896fe29 bellard
{
374 c896fe29 bellard
    /* some cases can be optimized here */
375 c896fe29 bellard
    if (arg2 == 0xffffffff) {
376 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
377 c896fe29 bellard
    } else if (arg2 == 0) {
378 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
379 c896fe29 bellard
    } else {
380 c896fe29 bellard
        tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2));
381 c896fe29 bellard
    }
382 c896fe29 bellard
}
383 c896fe29 bellard
384 ac56dd48 pbrook
static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2)
385 c896fe29 bellard
{
386 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2);
387 c896fe29 bellard
}
388 c896fe29 bellard
389 ac56dd48 pbrook
static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2)
390 c896fe29 bellard
{
391 c896fe29 bellard
    /* some cases can be optimized here */
392 c896fe29 bellard
    if (arg2 == 0) {
393 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
394 c896fe29 bellard
    } else {
395 c896fe29 bellard
        tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2));
396 c896fe29 bellard
    }
397 c896fe29 bellard
}
398 c896fe29 bellard
399 ac56dd48 pbrook
static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2)
400 c896fe29 bellard
{
401 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2);
402 c896fe29 bellard
}
403 c896fe29 bellard
404 ac56dd48 pbrook
static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2)
405 c896fe29 bellard
{
406 c896fe29 bellard
    tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2));
407 c896fe29 bellard
}
408 c896fe29 bellard
409 ac56dd48 pbrook
static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2)
410 c896fe29 bellard
{
411 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2);
412 c896fe29 bellard
}
413 c896fe29 bellard
414 ac56dd48 pbrook
static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2)
415 c896fe29 bellard
{
416 c896fe29 bellard
    tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2));
417 c896fe29 bellard
}
418 c896fe29 bellard
419 ac56dd48 pbrook
static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2)
420 c896fe29 bellard
{
421 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2);
422 c896fe29 bellard
}
423 c896fe29 bellard
424 ac56dd48 pbrook
static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2)
425 c896fe29 bellard
{
426 c896fe29 bellard
    tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2));
427 c896fe29 bellard
}
428 c896fe29 bellard
429 ac56dd48 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, 
430 c896fe29 bellard
                                      int label_index)
431 c896fe29 bellard
{
432 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
433 c896fe29 bellard
}
434 c896fe29 bellard
435 ac56dd48 pbrook
static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2)
436 c896fe29 bellard
{
437 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2);
438 c896fe29 bellard
}
439 c896fe29 bellard
440 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
441 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
442 c896fe29 bellard
{
443 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2);
444 c896fe29 bellard
}
445 c896fe29 bellard
446 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
447 c896fe29 bellard
{
448 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2);
449 c896fe29 bellard
}
450 c896fe29 bellard
451 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
452 c896fe29 bellard
{
453 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2);
454 c896fe29 bellard
}
455 c896fe29 bellard
456 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
457 c896fe29 bellard
{
458 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2);
459 c896fe29 bellard
}
460 c896fe29 bellard
#else
461 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
462 c896fe29 bellard
{
463 ac56dd48 pbrook
    TCGv t0;
464 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
465 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
466 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
467 c896fe29 bellard
}
468 c896fe29 bellard
469 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
470 c896fe29 bellard
{
471 ac56dd48 pbrook
    TCGv t0;
472 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
473 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
474 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
475 c896fe29 bellard
}
476 c896fe29 bellard
477 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
478 c896fe29 bellard
{
479 ac56dd48 pbrook
    TCGv t0;
480 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
481 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
482 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
483 c896fe29 bellard
}
484 c896fe29 bellard
485 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
486 c896fe29 bellard
{
487 ac56dd48 pbrook
    TCGv t0;
488 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
489 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
490 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
491 c896fe29 bellard
}
492 c896fe29 bellard
#endif
493 c896fe29 bellard
494 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
495 c896fe29 bellard
496 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
497 c896fe29 bellard
{
498 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
499 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
500 c896fe29 bellard
}
501 c896fe29 bellard
502 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
503 c896fe29 bellard
{
504 c896fe29 bellard
    tcg_gen_movi_i32(ret, arg);
505 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
506 c896fe29 bellard
}
507 c896fe29 bellard
508 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
509 c896fe29 bellard
{
510 c896fe29 bellard
    tcg_gen_ld8u_i32(ret, arg2, offset);
511 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
512 c896fe29 bellard
}
513 c896fe29 bellard
514 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
515 c896fe29 bellard
{
516 c896fe29 bellard
    tcg_gen_ld8s_i32(ret, arg2, offset);
517 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
518 c896fe29 bellard
}
519 c896fe29 bellard
520 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
521 c896fe29 bellard
{
522 c896fe29 bellard
    tcg_gen_ld16u_i32(ret, arg2, offset);
523 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
524 c896fe29 bellard
}
525 c896fe29 bellard
526 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
527 c896fe29 bellard
{
528 c896fe29 bellard
    tcg_gen_ld16s_i32(ret, arg2, offset);
529 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
530 c896fe29 bellard
}
531 c896fe29 bellard
532 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
533 c896fe29 bellard
{
534 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
535 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
536 c896fe29 bellard
}
537 c896fe29 bellard
538 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
539 c896fe29 bellard
{
540 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
541 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
542 c896fe29 bellard
}
543 c896fe29 bellard
544 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
545 c896fe29 bellard
{
546 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
547 c896fe29 bellard
       same temporary */
548 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
549 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
550 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset + 4);
551 c896fe29 bellard
#else
552 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
553 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
554 c896fe29 bellard
#endif
555 c896fe29 bellard
}
556 c896fe29 bellard
557 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
558 c896fe29 bellard
{
559 c896fe29 bellard
    tcg_gen_st8_i32(arg1, arg2, offset);
560 c896fe29 bellard
}
561 c896fe29 bellard
562 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
563 c896fe29 bellard
{
564 c896fe29 bellard
    tcg_gen_st16_i32(arg1, arg2, offset);
565 c896fe29 bellard
}
566 c896fe29 bellard
567 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
568 c896fe29 bellard
{
569 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
570 c896fe29 bellard
}
571 c896fe29 bellard
572 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
573 c896fe29 bellard
{
574 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
575 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
576 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset + 4);
577 c896fe29 bellard
#else
578 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
579 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
580 c896fe29 bellard
#endif
581 c896fe29 bellard
}
582 c896fe29 bellard
583 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
584 c896fe29 bellard
{
585 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), 
586 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
587 c896fe29 bellard
}
588 c896fe29 bellard
589 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
590 c896fe29 bellard
{
591 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
592 c896fe29 bellard
}
593 c896fe29 bellard
594 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
595 c896fe29 bellard
{
596 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), 
597 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
598 c896fe29 bellard
}
599 c896fe29 bellard
600 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
601 c896fe29 bellard
{
602 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
603 c896fe29 bellard
}
604 c896fe29 bellard
605 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
606 c896fe29 bellard
{
607 c896fe29 bellard
    tcg_gen_and_i32(ret, arg1, arg2);
608 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
609 c896fe29 bellard
}
610 c896fe29 bellard
611 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
612 c896fe29 bellard
{
613 c896fe29 bellard
    tcg_gen_andi_i32(ret, arg1, arg2);
614 ac56dd48 pbrook
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
615 c896fe29 bellard
}
616 c896fe29 bellard
617 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
618 c896fe29 bellard
{
619 c896fe29 bellard
    tcg_gen_or_i32(ret, arg1, arg2);
620 ac56dd48 pbrook
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
621 c896fe29 bellard
}
622 c896fe29 bellard
623 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
624 c896fe29 bellard
{
625 c896fe29 bellard
    tcg_gen_ori_i32(ret, arg1, arg2);
626 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
627 c896fe29 bellard
}
628 c896fe29 bellard
629 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
630 c896fe29 bellard
{
631 c896fe29 bellard
    tcg_gen_xor_i32(ret, arg1, arg2);
632 ac56dd48 pbrook
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
633 c896fe29 bellard
}
634 c896fe29 bellard
635 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
636 c896fe29 bellard
{
637 c896fe29 bellard
    tcg_gen_xori_i32(ret, arg1, arg2);
638 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
639 c896fe29 bellard
}
640 c896fe29 bellard
641 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
642 c896fe29 bellard
   specific code (x86) */
643 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
644 c896fe29 bellard
{
645 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2);
646 c896fe29 bellard
}
647 c896fe29 bellard
648 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
649 c896fe29 bellard
{
650 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
651 c896fe29 bellard
}
652 c896fe29 bellard
653 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
654 c896fe29 bellard
{
655 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2);
656 c896fe29 bellard
}
657 c896fe29 bellard
658 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
659 c896fe29 bellard
{
660 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
661 c896fe29 bellard
}
662 c896fe29 bellard
663 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
664 c896fe29 bellard
{
665 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2);
666 c896fe29 bellard
}
667 c896fe29 bellard
668 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
669 c896fe29 bellard
{
670 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
671 c896fe29 bellard
}
672 c896fe29 bellard
673 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
674 c896fe29 bellard
                                      int label_index)
675 c896fe29 bellard
{
676 ac56dd48 pbrook
    tcg_gen_op6ii(INDEX_op_brcond2_i32, 
677 ac56dd48 pbrook
                  arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2),
678 ac56dd48 pbrook
                  cond, label_index);
679 c896fe29 bellard
}
680 c896fe29 bellard
681 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
682 c896fe29 bellard
{
683 ac56dd48 pbrook
    TCGv t0, t1;
684 c896fe29 bellard
    
685 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
686 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
687 c896fe29 bellard
688 ac56dd48 pbrook
    tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2);
689 c896fe29 bellard
    
690 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2));
691 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
692 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2);
693 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
694 c896fe29 bellard
    
695 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
696 c896fe29 bellard
}
697 c896fe29 bellard
698 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
699 c896fe29 bellard
{
700 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2);
701 c896fe29 bellard
}
702 c896fe29 bellard
703 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
704 c896fe29 bellard
{
705 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2);
706 c896fe29 bellard
}
707 c896fe29 bellard
708 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
709 c896fe29 bellard
{
710 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2);
711 c896fe29 bellard
}
712 c896fe29 bellard
713 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
714 c896fe29 bellard
{
715 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2);
716 c896fe29 bellard
}
717 c896fe29 bellard
718 c896fe29 bellard
#else
719 c896fe29 bellard
720 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
721 c896fe29 bellard
{
722 c896fe29 bellard
    tcg_gen_op2(INDEX_op_mov_i64, ret, arg);
723 c896fe29 bellard
}
724 c896fe29 bellard
725 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
726 c896fe29 bellard
{
727 ac56dd48 pbrook
    tcg_gen_op2i(INDEX_op_movi_i64, ret, arg);
728 c896fe29 bellard
}
729 c896fe29 bellard
730 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2,
731 ac56dd48 pbrook
                                    tcg_target_long offset)
732 c896fe29 bellard
{
733 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset);
734 c896fe29 bellard
}
735 c896fe29 bellard
736 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2,
737 ac56dd48 pbrook
                                    tcg_target_long offset)
738 c896fe29 bellard
{
739 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset);
740 c896fe29 bellard
}
741 c896fe29 bellard
742 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2,
743 ac56dd48 pbrook
                                     tcg_target_long offset)
744 c896fe29 bellard
{
745 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset);
746 c896fe29 bellard
}
747 c896fe29 bellard
748 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2,
749 ac56dd48 pbrook
                                     tcg_target_long offset)
750 c896fe29 bellard
{
751 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset);
752 c896fe29 bellard
}
753 c896fe29 bellard
754 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2,
755 ac56dd48 pbrook
                                     tcg_target_long offset)
756 c896fe29 bellard
{
757 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset);
758 c896fe29 bellard
}
759 c896fe29 bellard
760 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2,
761 ac56dd48 pbrook
                                     tcg_target_long offset)
762 c896fe29 bellard
{
763 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset);
764 c896fe29 bellard
}
765 c896fe29 bellard
766 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
767 c896fe29 bellard
{
768 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset);
769 c896fe29 bellard
}
770 c896fe29 bellard
771 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2,
772 ac56dd48 pbrook
                                   tcg_target_long offset)
773 c896fe29 bellard
{
774 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset);
775 c896fe29 bellard
}
776 c896fe29 bellard
777 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2,
778 ac56dd48 pbrook
                                    tcg_target_long offset)
779 c896fe29 bellard
{
780 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset);
781 c896fe29 bellard
}
782 c896fe29 bellard
783 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2,
784 ac56dd48 pbrook
                                    tcg_target_long offset)
785 c896fe29 bellard
{
786 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset);
787 c896fe29 bellard
}
788 c896fe29 bellard
789 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
790 c896fe29 bellard
{
791 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset);
792 c896fe29 bellard
}
793 c896fe29 bellard
794 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
795 c896fe29 bellard
{
796 c896fe29 bellard
    tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2);
797 c896fe29 bellard
}
798 c896fe29 bellard
799 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
800 c896fe29 bellard
{
801 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
802 c896fe29 bellard
}
803 c896fe29 bellard
804 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
805 c896fe29 bellard
{
806 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2);
807 c896fe29 bellard
}
808 c896fe29 bellard
809 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
810 c896fe29 bellard
{
811 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
812 c896fe29 bellard
}
813 c896fe29 bellard
814 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
815 c896fe29 bellard
{
816 c896fe29 bellard
    tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2);
817 c896fe29 bellard
}
818 c896fe29 bellard
819 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
820 c896fe29 bellard
{
821 c896fe29 bellard
    tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2));
822 c896fe29 bellard
}
823 c896fe29 bellard
824 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
825 c896fe29 bellard
{
826 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2);
827 c896fe29 bellard
}
828 c896fe29 bellard
829 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
830 c896fe29 bellard
{
831 c896fe29 bellard
    tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2));
832 c896fe29 bellard
}
833 c896fe29 bellard
834 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
835 c896fe29 bellard
{
836 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2);
837 c896fe29 bellard
}
838 c896fe29 bellard
839 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
840 c896fe29 bellard
{
841 c896fe29 bellard
    tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2));
842 c896fe29 bellard
}
843 c896fe29 bellard
844 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
845 c896fe29 bellard
{
846 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2);
847 c896fe29 bellard
}
848 c896fe29 bellard
849 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
850 c896fe29 bellard
{
851 c896fe29 bellard
    tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2));
852 c896fe29 bellard
}
853 c896fe29 bellard
854 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
855 c896fe29 bellard
{
856 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2);
857 c896fe29 bellard
}
858 c896fe29 bellard
859 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
860 c896fe29 bellard
{
861 c896fe29 bellard
    tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2));
862 c896fe29 bellard
}
863 c896fe29 bellard
864 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
865 c896fe29 bellard
{
866 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2);
867 c896fe29 bellard
}
868 c896fe29 bellard
869 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
870 c896fe29 bellard
{
871 c896fe29 bellard
    tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2));
872 c896fe29 bellard
}
873 c896fe29 bellard
874 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
875 c896fe29 bellard
                                      int label_index)
876 c896fe29 bellard
{
877 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
878 c896fe29 bellard
}
879 c896fe29 bellard
880 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
881 c896fe29 bellard
{
882 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2);
883 c896fe29 bellard
}
884 c896fe29 bellard
885 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
886 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
887 c896fe29 bellard
{
888 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2);
889 c896fe29 bellard
}
890 c896fe29 bellard
891 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
892 c896fe29 bellard
{
893 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2);
894 c896fe29 bellard
}
895 c896fe29 bellard
896 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
897 c896fe29 bellard
{
898 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2);
899 c896fe29 bellard
}
900 c896fe29 bellard
901 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
902 c896fe29 bellard
{
903 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2);
904 c896fe29 bellard
}
905 c896fe29 bellard
#else
906 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
907 c896fe29 bellard
{
908 ac56dd48 pbrook
    TCGv t0;
909 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
910 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
911 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
912 c896fe29 bellard
}
913 c896fe29 bellard
914 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
915 c896fe29 bellard
{
916 ac56dd48 pbrook
    TCGv t0;
917 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
918 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
919 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
920 c896fe29 bellard
}
921 c896fe29 bellard
922 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
923 c896fe29 bellard
{
924 ac56dd48 pbrook
    TCGv t0;
925 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
926 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
927 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
928 c896fe29 bellard
}
929 c896fe29 bellard
930 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
931 c896fe29 bellard
{
932 ac56dd48 pbrook
    TCGv t0;
933 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
934 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
935 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
936 c896fe29 bellard
}
937 c896fe29 bellard
#endif
938 c896fe29 bellard
939 c896fe29 bellard
#endif
940 c896fe29 bellard
941 c896fe29 bellard
/***************************************/
942 c896fe29 bellard
/* optional operations */
943 c896fe29 bellard
944 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg)
945 c896fe29 bellard
{
946 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
947 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg);
948 c896fe29 bellard
#else
949 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
950 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
951 c896fe29 bellard
#endif
952 c896fe29 bellard
}
953 c896fe29 bellard
954 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg)
955 c896fe29 bellard
{
956 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
957 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg);
958 c896fe29 bellard
#else
959 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
960 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
961 c896fe29 bellard
#endif
962 c896fe29 bellard
}
963 c896fe29 bellard
964 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
965 ac56dd48 pbrook
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg)
966 c896fe29 bellard
{
967 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
968 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg);
969 c896fe29 bellard
#else
970 ac56dd48 pbrook
    TCGv t0, t1;
971 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
972 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
973 c896fe29 bellard
    
974 c896fe29 bellard
    tcg_gen_shri_i32(t0, arg, 8);
975 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x000000ff);
976 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
977 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
978 c896fe29 bellard
#endif
979 c896fe29 bellard
}
980 c896fe29 bellard
981 ac56dd48 pbrook
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg)
982 c896fe29 bellard
{
983 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i32
984 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i32, ret, arg);
985 c896fe29 bellard
#else
986 ac56dd48 pbrook
    TCGv t0, t1;
987 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
988 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
989 c896fe29 bellard
    
990 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
991 c896fe29 bellard
    
992 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
993 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
994 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
995 c896fe29 bellard
    
996 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
997 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
998 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
999 c896fe29 bellard
    
1000 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1001 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1002 c896fe29 bellard
#endif
1003 c896fe29 bellard
}
1004 c896fe29 bellard
1005 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1006 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
1007 c896fe29 bellard
{
1008 c896fe29 bellard
    tcg_gen_ext8s_i32(ret, arg);
1009 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1010 c896fe29 bellard
}
1011 c896fe29 bellard
1012 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
1013 c896fe29 bellard
{
1014 c896fe29 bellard
    tcg_gen_ext16s_i32(ret, arg);
1015 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1016 c896fe29 bellard
}
1017 c896fe29 bellard
1018 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
1019 c896fe29 bellard
{
1020 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1021 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1022 c896fe29 bellard
}
1023 c896fe29 bellard
1024 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1025 c896fe29 bellard
{
1026 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1027 c896fe29 bellard
}
1028 c896fe29 bellard
1029 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1030 c896fe29 bellard
{
1031 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1032 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1033 c896fe29 bellard
}
1034 c896fe29 bellard
1035 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1036 c896fe29 bellard
{
1037 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1038 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1039 c896fe29 bellard
}
1040 c896fe29 bellard
1041 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1042 c896fe29 bellard
{
1043 ac56dd48 pbrook
    TCGv t0, t1;
1044 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1045 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1046 c896fe29 bellard
1047 c896fe29 bellard
    tcg_gen_bswap_i32(t0, arg);
1048 ac56dd48 pbrook
    tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
1049 c896fe29 bellard
    tcg_gen_mov_i32(ret, t1);
1050 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1051 c896fe29 bellard
}
1052 c896fe29 bellard
#else
1053 c896fe29 bellard
1054 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
1055 c896fe29 bellard
{
1056 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1057 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg);
1058 c896fe29 bellard
#else
1059 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1060 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1061 c896fe29 bellard
#endif
1062 c896fe29 bellard
}
1063 c896fe29 bellard
1064 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
1065 c896fe29 bellard
{
1066 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1067 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg);
1068 c896fe29 bellard
#else
1069 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1070 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1071 c896fe29 bellard
#endif
1072 c896fe29 bellard
}
1073 c896fe29 bellard
1074 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
1075 c896fe29 bellard
{
1076 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1077 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg);
1078 c896fe29 bellard
#else
1079 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1080 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1081 c896fe29 bellard
#endif
1082 c896fe29 bellard
}
1083 c896fe29 bellard
1084 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1085 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1086 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1087 c896fe29 bellard
{
1088 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1089 c896fe29 bellard
}
1090 c896fe29 bellard
1091 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1092 c896fe29 bellard
   registers */
1093 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1094 c896fe29 bellard
{
1095 c896fe29 bellard
    tcg_gen_andi_i64(ret, arg, 0xffffffff);
1096 c896fe29 bellard
}
1097 c896fe29 bellard
1098 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1099 c896fe29 bellard
   registers */
1100 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1101 c896fe29 bellard
{
1102 c896fe29 bellard
    tcg_gen_ext32s_i64(ret, arg);
1103 c896fe29 bellard
}
1104 c896fe29 bellard
1105 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1106 c896fe29 bellard
{
1107 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i64
1108 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i64, ret, arg);
1109 c896fe29 bellard
#else
1110 ac56dd48 pbrook
    TCGv t0, t1;
1111 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1112 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1113 c896fe29 bellard
    
1114 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1115 c896fe29 bellard
    
1116 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1117 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1118 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1119 c896fe29 bellard
    
1120 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1121 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1122 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1123 c896fe29 bellard
1124 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1125 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1126 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1127 c896fe29 bellard
1128 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1129 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1130 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1131 c896fe29 bellard
    
1132 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1133 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1134 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1135 c896fe29 bellard
1136 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1137 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1138 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1139 c896fe29 bellard
1140 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1141 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1142 c896fe29 bellard
#endif
1143 c896fe29 bellard
}
1144 c896fe29 bellard
1145 c896fe29 bellard
#endif
1146 c896fe29 bellard
1147 5ff9d6a4 bellard
1148 5ff9d6a4 bellard
static inline void tcg_gen_discard_i32(TCGv arg)
1149 5ff9d6a4 bellard
{
1150 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1151 5ff9d6a4 bellard
}
1152 5ff9d6a4 bellard
1153 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1154 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1155 5ff9d6a4 bellard
{
1156 5ff9d6a4 bellard
    tcg_gen_discard_i32(arg);
1157 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1158 5ff9d6a4 bellard
}
1159 5ff9d6a4 bellard
#else
1160 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1161 5ff9d6a4 bellard
{
1162 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1163 5ff9d6a4 bellard
}
1164 5ff9d6a4 bellard
#endif
1165 5ff9d6a4 bellard
1166 c896fe29 bellard
/***************************************/
1167 ac56dd48 pbrook
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id)
1168 c896fe29 bellard
{
1169 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id);
1170 c896fe29 bellard
}
1171 c896fe29 bellard
1172 c896fe29 bellard
/***************************************/
1173 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1174 c896fe29 bellard
   type. */
1175 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1176 c896fe29 bellard
#error must include QEMU headers
1177 c896fe29 bellard
#endif
1178 c896fe29 bellard
1179 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1180 c896fe29 bellard
{
1181 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1182 c896fe29 bellard
}
1183 c896fe29 bellard
1184 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1185 c896fe29 bellard
{
1186 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1187 c896fe29 bellard
}
1188 c896fe29 bellard
1189 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1190 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1191 c896fe29 bellard
{
1192 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1193 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1194 c896fe29 bellard
#else
1195 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index);
1196 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1197 c896fe29 bellard
#endif
1198 c896fe29 bellard
}
1199 c896fe29 bellard
1200 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1201 c896fe29 bellard
{
1202 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1203 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1204 c896fe29 bellard
#else
1205 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index);
1206 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1207 c896fe29 bellard
#endif
1208 c896fe29 bellard
}
1209 c896fe29 bellard
1210 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1211 c896fe29 bellard
{
1212 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1213 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1214 c896fe29 bellard
#else
1215 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index);
1216 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1217 c896fe29 bellard
#endif
1218 c896fe29 bellard
}
1219 c896fe29 bellard
1220 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1221 c896fe29 bellard
{
1222 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1223 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1224 c896fe29 bellard
#else
1225 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index);
1226 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1227 c896fe29 bellard
#endif
1228 c896fe29 bellard
}
1229 c896fe29 bellard
1230 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1231 c896fe29 bellard
{
1232 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1233 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1234 c896fe29 bellard
#else
1235 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1236 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1237 c896fe29 bellard
#endif
1238 c896fe29 bellard
}
1239 c896fe29 bellard
1240 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1241 c896fe29 bellard
{
1242 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1243 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1244 c896fe29 bellard
#else
1245 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1246 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1247 c896fe29 bellard
#endif
1248 c896fe29 bellard
}
1249 c896fe29 bellard
1250 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1251 c896fe29 bellard
{
1252 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1253 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index);
1254 c896fe29 bellard
#else
1255 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret),
1256 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1257 c896fe29 bellard
#endif
1258 c896fe29 bellard
}
1259 c896fe29 bellard
1260 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1261 c896fe29 bellard
{
1262 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1263 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1264 c896fe29 bellard
#else
1265 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index);
1266 c896fe29 bellard
#endif
1267 c896fe29 bellard
}
1268 c896fe29 bellard
1269 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1270 c896fe29 bellard
{
1271 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1272 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1273 c896fe29 bellard
#else
1274 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index);
1275 c896fe29 bellard
#endif
1276 c896fe29 bellard
}
1277 c896fe29 bellard
1278 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1279 c896fe29 bellard
{
1280 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1281 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1282 c896fe29 bellard
#else
1283 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index);
1284 c896fe29 bellard
#endif
1285 c896fe29 bellard
}
1286 c896fe29 bellard
1287 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1288 c896fe29 bellard
{
1289 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1290 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index);
1291 c896fe29 bellard
#else
1292 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg),
1293 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1294 c896fe29 bellard
#endif
1295 c896fe29 bellard
}
1296 c896fe29 bellard
1297 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
1298 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
1299 f8422f52 blueswir1
1300 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1301 c896fe29 bellard
1302 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1303 c896fe29 bellard
{
1304 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1305 c896fe29 bellard
}
1306 c896fe29 bellard
1307 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1308 c896fe29 bellard
{
1309 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1310 c896fe29 bellard
}
1311 c896fe29 bellard
1312 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1313 c896fe29 bellard
{
1314 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1315 c896fe29 bellard
}
1316 c896fe29 bellard
1317 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1318 c896fe29 bellard
{
1319 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1320 c896fe29 bellard
}
1321 c896fe29 bellard
1322 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1323 c896fe29 bellard
{
1324 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1325 c896fe29 bellard
}
1326 c896fe29 bellard
1327 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1328 c896fe29 bellard
{
1329 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1330 c896fe29 bellard
}
1331 c896fe29 bellard
1332 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1333 c896fe29 bellard
{
1334 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index);
1335 c896fe29 bellard
}
1336 c896fe29 bellard
1337 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1338 c896fe29 bellard
{
1339 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1340 c896fe29 bellard
}
1341 c896fe29 bellard
1342 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1343 c896fe29 bellard
{
1344 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1345 c896fe29 bellard
}
1346 c896fe29 bellard
1347 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1348 c896fe29 bellard
{
1349 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1350 c896fe29 bellard
}
1351 c896fe29 bellard
1352 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1353 c896fe29 bellard
{
1354 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index);
1355 c896fe29 bellard
}
1356 c896fe29 bellard
1357 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
1358 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
1359 f8422f52 blueswir1
1360 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
1361 f8422f52 blueswir1
1362 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
1363 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
1364 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
1365 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
1366 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1367 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1368 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1369 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1370 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1371 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1372 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
1373 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
1374 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
1375 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
1376 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
1377 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
1378 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
1379 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
1380 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
1381 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
1382 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
1383 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
1384 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
1385 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
1386 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
1387 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
1388 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
1389 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
1390 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
1391 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
1392 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
1393 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
1394 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
1395 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
1396 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1397 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1398 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1399 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1400 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
1401 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
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#else
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#define TCG_TYPE_TL TCG_TYPE_I32
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#define tcg_gen_movi_tl tcg_gen_movi_i32
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#define tcg_gen_mov_tl tcg_gen_mov_i32
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#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
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#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
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#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
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#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
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#define tcg_gen_ld32u_tl tcg_gen_ld_i32
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#define tcg_gen_ld32s_tl tcg_gen_ld_i32
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#define tcg_gen_ld_tl tcg_gen_ld_i32
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#define tcg_gen_st8_tl tcg_gen_st8_i32
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#define tcg_gen_st16_tl tcg_gen_st16_i32
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#define tcg_gen_st32_tl tcg_gen_st_i32
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#define tcg_gen_st_tl tcg_gen_st_i32
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#define tcg_gen_add_tl tcg_gen_add_i32
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#define tcg_gen_addi_tl tcg_gen_addi_i32
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#define tcg_gen_sub_tl tcg_gen_sub_i32
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#define tcg_gen_subi_tl tcg_gen_subi_i32
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#define tcg_gen_and_tl tcg_gen_and_i32
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#define tcg_gen_andi_tl tcg_gen_andi_i32
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#define tcg_gen_or_tl tcg_gen_or_i32
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#define tcg_gen_ori_tl tcg_gen_ori_i32
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#define tcg_gen_xor_tl tcg_gen_xor_i32
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#define tcg_gen_xori_tl tcg_gen_xori_i32
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#define tcg_gen_shl_tl tcg_gen_shl_i32
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#define tcg_gen_shli_tl tcg_gen_shli_i32
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#define tcg_gen_shr_tl tcg_gen_shr_i32
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#define tcg_gen_shri_tl tcg_gen_shri_i32
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#define tcg_gen_sar_tl tcg_gen_sar_i32
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#define tcg_gen_sari_tl tcg_gen_sari_i32
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#define tcg_gen_brcond_tl tcg_gen_brcond_i32
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#define tcg_gen_discard_tl tcg_gen_discard_i32
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#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
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#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
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#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
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#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
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#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
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#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
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#define tcg_const_tl tcg_const_i32
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#endif
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#if TCG_TARGET_REG_BITS == 32
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#define tcg_gen_addi_ptr tcg_gen_addi_i32
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#else /* TCG_TARGET_REG_BITS == 32 */
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#define tcg_gen_addi_ptr tcg_gen_addi_i64
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#endif /* TCG_TARGET_REG_BITS != 32 */