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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%eax",
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    "%ecx",
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    "%edx",
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    "%ebx",
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    "%esp",
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    "%ebp",
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    "%esi",
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    "%edi",
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};
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int tcg_target_reg_alloc_order[] = {
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    TCG_REG_EAX,
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    TCG_REG_EDX,
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    TCG_REG_ECX,
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    TCG_REG_EBX,
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    TCG_REG_ESI,
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    TCG_REG_EDI,
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    TCG_REG_EBP,
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    TCG_REG_ESP,
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};
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const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
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const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
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static uint8_t *tb_ret_addr;
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static void patch_reloc(uint8_t *code_ptr, int type, 
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                        tcg_target_long value, tcg_target_long addend)
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{
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    value += addend;
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    switch(type) {
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    case R_386_32:
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        *(uint32_t *)code_ptr = value;
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        break;
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    case R_386_PC32:
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        *(uint32_t *)code_ptr = value - (long)code_ptr;
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        break;
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    default:
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        tcg_abort();
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    }
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}
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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    flags &= TCG_CALL_TYPE_MASK;
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    switch(flags) {
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    case TCG_CALL_TYPE_STD:
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        return 0;
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    case TCG_CALL_TYPE_REGPARM_1:
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    case TCG_CALL_TYPE_REGPARM_2:
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    case TCG_CALL_TYPE_REGPARM:
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        return flags - TCG_CALL_TYPE_REGPARM_1 + 1;
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    default:
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        tcg_abort();
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    }
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}
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/* parse target specific constraints */
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int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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    const char *ct_str;
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    ct_str = *pct_str;
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    switch(ct_str[0]) {
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    case 'a':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
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        break;
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    case 'b':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
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        break;
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    case 'c':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
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        break;
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    case 'd':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
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        break;
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    case 'S':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
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        break;
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    case 'D':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
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        break;
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    case 'q':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xf);
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        break;
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    case 'r':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xff);
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        break;
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        /* qemu_ld/st address constraint */
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    case 'L':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xff);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
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        break;
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    default:
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        return -1;
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    }
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    ct_str++;
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    *pct_str = ct_str;
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    return 0;
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}
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val,
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                                         const TCGArgConstraint *arg_ct)
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{
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    int ct;
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    ct = arg_ct->ct;
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    if (ct & TCG_CT_CONST)
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        return 1;
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    else
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        return 0;
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}
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#define ARITH_ADD 0
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#define ARITH_OR  1
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#define ARITH_ADC 2
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#define ARITH_SBB 3
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#define ARITH_AND 4
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#define ARITH_SUB 5
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#define ARITH_XOR 6
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#define ARITH_CMP 7
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#define SHIFT_SHL 4
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#define SHIFT_SHR 5
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#define SHIFT_SAR 7
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#define JCC_JMP (-1)
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#define JCC_JO  0x0
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#define JCC_JNO 0x1
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#define JCC_JB  0x2
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#define JCC_JAE 0x3
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#define JCC_JE  0x4
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#define JCC_JNE 0x5
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#define JCC_JBE 0x6
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#define JCC_JA  0x7
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#define JCC_JS  0x8
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#define JCC_JNS 0x9
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#define JCC_JP  0xa
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#define JCC_JNP 0xb
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#define JCC_JL  0xc
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#define JCC_JGE 0xd
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#define JCC_JLE 0xe
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#define JCC_JG  0xf
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#define P_EXT   0x100 /* 0x0f opcode prefix */
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static const uint8_t tcg_cond_to_jcc[10] = {
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    [TCG_COND_EQ] = JCC_JE,
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    [TCG_COND_NE] = JCC_JNE,
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    [TCG_COND_LT] = JCC_JL,
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    [TCG_COND_GE] = JCC_JGE,
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    [TCG_COND_LE] = JCC_JLE,
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    [TCG_COND_GT] = JCC_JG,
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    [TCG_COND_LTU] = JCC_JB,
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    [TCG_COND_GEU] = JCC_JAE,
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    [TCG_COND_LEU] = JCC_JBE,
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    [TCG_COND_GTU] = JCC_JA,
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};
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static inline void tcg_out_opc(TCGContext *s, int opc)
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{
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    if (opc & P_EXT)
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        tcg_out8(s, 0x0f);
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    tcg_out8(s, opc);
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}
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static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
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{
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    tcg_out_opc(s, opc);
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    tcg_out8(s, 0xc0 | (r << 3) | rm);
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}
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/* rm == -1 means no register index */
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static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, 
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                                        int32_t offset)
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{
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    tcg_out_opc(s, opc);
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    if (rm == -1) {
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        tcg_out8(s, 0x05 | (r << 3));
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        tcg_out32(s, offset);
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    } else if (offset == 0 && rm != TCG_REG_EBP) {
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        if (rm == TCG_REG_ESP) {
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            tcg_out8(s, 0x04 | (r << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x00 | (r << 3) | rm);
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        }
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    } else if ((int8_t)offset == offset) {
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        if (rm == TCG_REG_ESP) {
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            tcg_out8(s, 0x44 | (r << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x40 | (r << 3) | rm);
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        }
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        tcg_out8(s, offset);
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    } else {
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        if (rm == TCG_REG_ESP) {
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            tcg_out8(s, 0x84 | (r << 3));
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            tcg_out8(s, 0x24);
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        } else {
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            tcg_out8(s, 0x80 | (r << 3) | rm);
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        }
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        tcg_out32(s, offset);
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    }
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}
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
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{
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    if (arg != ret)
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        tcg_out_modrm(s, 0x8b, ret, arg);
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}
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static inline void tcg_out_movi(TCGContext *s, TCGType type,
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                                int ret, int32_t arg)
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{
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    if (arg == 0) {
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        /* xor r0,r0 */
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        tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret);
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    } else {
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        tcg_out8(s, 0xb8 + ret);
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        tcg_out32(s, arg);
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    }
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}
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static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
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                              int arg1, tcg_target_long arg2)
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{
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    /* movl */
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    tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
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}
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static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
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                              int arg1, tcg_target_long arg2)
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{
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    /* movl */
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    tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
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}
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static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val)
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{
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    if (val == (int8_t)val) {
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        tcg_out_modrm(s, 0x83, c, r0);
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        tcg_out8(s, val);
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    } else {
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        tcg_out_modrm(s, 0x81, c, r0);
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        tcg_out32(s, val);
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    }
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}
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void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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{
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    if (val != 0)
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        tgen_arithi(s, ARITH_ADD, reg, val);
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}
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static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
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{
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    int32_t val, val1;
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    TCGLabel *l = &s->labels[label_index];
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    if (l->has_value) {
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        val = l->u.value - (tcg_target_long)s->code_ptr;
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        val1 = val - 2;
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        if ((int8_t)val1 == val1) {
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            if (opc == -1)
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                tcg_out8(s, 0xeb);
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            else
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                tcg_out8(s, 0x70 + opc);
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            tcg_out8(s, val1);
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        } else {
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            if (opc == -1) {
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                tcg_out8(s, 0xe9);
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                tcg_out32(s, val - 5);
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            } else {
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                tcg_out8(s, 0x0f);
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                tcg_out8(s, 0x80 + opc);
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                tcg_out32(s, val - 6);
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            }
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        }
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    } else {
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        if (opc == -1) {
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            tcg_out8(s, 0xe9);
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        } else {
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            tcg_out8(s, 0x0f);
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            tcg_out8(s, 0x80 + opc);
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        }
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        tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
324 623e265c pbrook
        s->code_ptr += 4;
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    }
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}
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static void tcg_out_brcond(TCGContext *s, int cond, 
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                           TCGArg arg1, TCGArg arg2, int const_arg2,
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                           int label_index)
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{
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    int c;
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    if (const_arg2) {
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        if (arg2 == 0) {
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            /* use test */
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            switch(cond) {
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            case TCG_COND_EQ:
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                c = JCC_JE;
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                break;
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            case TCG_COND_NE:
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                c = JCC_JNE;
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                break;
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            case TCG_COND_LT:
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                c = JCC_JS;
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                break;
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            case TCG_COND_GE:
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                c = JCC_JNS;
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                break;
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            default:
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                goto do_cmpi;
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            }
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            /* test r, r */
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            tcg_out_modrm(s, 0x85, arg1, arg1);
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            tcg_out_jxx(s, c, label_index);
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        } else {
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        do_cmpi:
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            tgen_arithi(s, ARITH_CMP, arg1, arg2);
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            tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
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        }
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    } else {
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        tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3), arg2, arg1);
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        tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
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    }
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}
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/* XXX: we implement it at the target level to avoid having to
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   handle cross basic blocks temporaries */
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static void tcg_out_brcond2(TCGContext *s,
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                            const TCGArg *args, const int *const_args)
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{
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    int label_next;
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    label_next = gen_new_label();
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    switch(args[4]) {
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    case TCG_COND_EQ:
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        tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
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        tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
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        break;
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    case TCG_COND_NE:
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        tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
380 bb210e78 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
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        break;
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    case TCG_COND_LT:
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        tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
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        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
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        tcg_out_brcond(s, TCG_COND_LT, args[0], args[2], const_args[2], args[5]);
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        break;
387 c896fe29 bellard
    case TCG_COND_LE:
388 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
389 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
390 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LE, args[0], args[2], const_args[2], args[5]);
391 c896fe29 bellard
        break;
392 c896fe29 bellard
    case TCG_COND_GT:
393 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
394 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
395 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GT, args[0], args[2], const_args[2], args[5]);
396 c896fe29 bellard
        break;
397 c896fe29 bellard
    case TCG_COND_GE:
398 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
399 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
400 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GE, args[0], args[2], const_args[2], args[5]);
401 c896fe29 bellard
        break;
402 c896fe29 bellard
    case TCG_COND_LTU:
403 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
404 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
405 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
406 c896fe29 bellard
        break;
407 c896fe29 bellard
    case TCG_COND_LEU:
408 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
409 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
410 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
411 c896fe29 bellard
        break;
412 c896fe29 bellard
    case TCG_COND_GTU:
413 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
414 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
415 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
416 c896fe29 bellard
        break;
417 c896fe29 bellard
    case TCG_COND_GEU:
418 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
419 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
420 c896fe29 bellard
        tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
421 c896fe29 bellard
        break;
422 c896fe29 bellard
    default:
423 c896fe29 bellard
        tcg_abort();
424 c896fe29 bellard
    }
425 c896fe29 bellard
    tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
426 c896fe29 bellard
}
427 c896fe29 bellard
428 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
429 c896fe29 bellard
extern void __ldb_mmu(void);
430 c896fe29 bellard
extern void __ldw_mmu(void);
431 c896fe29 bellard
extern void __ldl_mmu(void);
432 c896fe29 bellard
extern void __ldq_mmu(void);
433 c896fe29 bellard
434 c896fe29 bellard
extern void __stb_mmu(void);
435 c896fe29 bellard
extern void __stw_mmu(void);
436 c896fe29 bellard
extern void __stl_mmu(void);
437 c896fe29 bellard
extern void __stq_mmu(void);
438 c896fe29 bellard
439 c896fe29 bellard
static void *qemu_ld_helpers[4] = {
440 c896fe29 bellard
    __ldb_mmu,
441 c896fe29 bellard
    __ldw_mmu,
442 c896fe29 bellard
    __ldl_mmu,
443 c896fe29 bellard
    __ldq_mmu,
444 c896fe29 bellard
};
445 c896fe29 bellard
446 c896fe29 bellard
static void *qemu_st_helpers[4] = {
447 c896fe29 bellard
    __stb_mmu,
448 c896fe29 bellard
    __stw_mmu,
449 c896fe29 bellard
    __stl_mmu,
450 c896fe29 bellard
    __stq_mmu,
451 c896fe29 bellard
};
452 c896fe29 bellard
#endif
453 c896fe29 bellard
454 c896fe29 bellard
/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
455 c896fe29 bellard
   EAX. It will be useful once fixed registers globals are less
456 c896fe29 bellard
   common. */
457 c896fe29 bellard
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
458 c896fe29 bellard
                            int opc)
459 c896fe29 bellard
{
460 c896fe29 bellard
    int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
461 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
462 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
463 c896fe29 bellard
#endif
464 c896fe29 bellard
#if TARGET_LONG_BITS == 64
465 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
466 c896fe29 bellard
    uint8_t *label3_ptr;
467 c896fe29 bellard
#endif
468 c896fe29 bellard
    int addr_reg2;
469 c896fe29 bellard
#endif
470 c896fe29 bellard
471 c896fe29 bellard
    data_reg = *args++;
472 c896fe29 bellard
    if (opc == 3)
473 c896fe29 bellard
        data_reg2 = *args++;
474 c896fe29 bellard
    else
475 c896fe29 bellard
        data_reg2 = 0;
476 c896fe29 bellard
    addr_reg = *args++;
477 c896fe29 bellard
#if TARGET_LONG_BITS == 64
478 c896fe29 bellard
    addr_reg2 = *args++;
479 c896fe29 bellard
#endif
480 c896fe29 bellard
    mem_index = *args;
481 c896fe29 bellard
    s_bits = opc & 3;
482 c896fe29 bellard
483 c896fe29 bellard
    r0 = TCG_REG_EAX;
484 c896fe29 bellard
    r1 = TCG_REG_EDX;
485 c896fe29 bellard
486 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
487 c896fe29 bellard
    tcg_out_mov(s, r1, addr_reg); 
488 c896fe29 bellard
489 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg); 
490 c896fe29 bellard
 
491 c896fe29 bellard
    tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
492 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
493 c896fe29 bellard
    
494 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
495 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
496 c896fe29 bellard
    
497 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
498 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
499 c896fe29 bellard
500 c896fe29 bellard
    tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
501 c896fe29 bellard
    tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
502 c896fe29 bellard
    tcg_out8(s, (5 << 3) | r1);
503 c896fe29 bellard
    tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
504 c896fe29 bellard
505 c896fe29 bellard
    /* cmp 0(r1), r0 */
506 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
507 c896fe29 bellard
    
508 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg);
509 c896fe29 bellard
    
510 c896fe29 bellard
#if TARGET_LONG_BITS == 32
511 c896fe29 bellard
    /* je label1 */
512 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
513 c896fe29 bellard
    label1_ptr = s->code_ptr;
514 c896fe29 bellard
    s->code_ptr++;
515 c896fe29 bellard
#else
516 c896fe29 bellard
    /* jne label3 */
517 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JNE);
518 c896fe29 bellard
    label3_ptr = s->code_ptr;
519 c896fe29 bellard
    s->code_ptr++;
520 c896fe29 bellard
    
521 c896fe29 bellard
    /* cmp 4(r1), addr_reg2 */
522 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
523 c896fe29 bellard
524 c896fe29 bellard
    /* je label1 */
525 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
526 c896fe29 bellard
    label1_ptr = s->code_ptr;
527 c896fe29 bellard
    s->code_ptr++;
528 c896fe29 bellard
    
529 c896fe29 bellard
    /* label3: */
530 c896fe29 bellard
    *label3_ptr = s->code_ptr - label3_ptr - 1;
531 c896fe29 bellard
#endif
532 c896fe29 bellard
533 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
534 c896fe29 bellard
#if TARGET_LONG_BITS == 32
535 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index);
536 c896fe29 bellard
#else
537 c896fe29 bellard
    tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
538 c896fe29 bellard
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
539 c896fe29 bellard
#endif
540 c896fe29 bellard
    tcg_out8(s, 0xe8);
541 c896fe29 bellard
    tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - 
542 c896fe29 bellard
              (tcg_target_long)s->code_ptr - 4);
543 c896fe29 bellard
544 c896fe29 bellard
    switch(opc) {
545 c896fe29 bellard
    case 0 | 4:
546 c896fe29 bellard
        /* movsbl */
547 c896fe29 bellard
        tcg_out_modrm(s, 0xbe | P_EXT, data_reg, TCG_REG_EAX);
548 c896fe29 bellard
        break;
549 c896fe29 bellard
    case 1 | 4:
550 c896fe29 bellard
        /* movswl */
551 c896fe29 bellard
        tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX);
552 c896fe29 bellard
        break;
553 c896fe29 bellard
    case 0:
554 c896fe29 bellard
    case 1:
555 c896fe29 bellard
    case 2:
556 c896fe29 bellard
    default:
557 c896fe29 bellard
        tcg_out_mov(s, data_reg, TCG_REG_EAX);
558 c896fe29 bellard
        break;
559 c896fe29 bellard
    case 3:
560 c896fe29 bellard
        if (data_reg == TCG_REG_EDX) {
561 c896fe29 bellard
            tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */
562 c896fe29 bellard
            tcg_out_mov(s, data_reg2, TCG_REG_EAX);
563 c896fe29 bellard
        } else {
564 c896fe29 bellard
            tcg_out_mov(s, data_reg, TCG_REG_EAX);
565 c896fe29 bellard
            tcg_out_mov(s, data_reg2, TCG_REG_EDX);
566 c896fe29 bellard
        }
567 c896fe29 bellard
        break;
568 c896fe29 bellard
    }
569 c896fe29 bellard
570 c896fe29 bellard
    /* jmp label2 */
571 c896fe29 bellard
    tcg_out8(s, 0xeb);
572 c896fe29 bellard
    label2_ptr = s->code_ptr;
573 c896fe29 bellard
    s->code_ptr++;
574 c896fe29 bellard
    
575 c896fe29 bellard
    /* label1: */
576 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
577 c896fe29 bellard
578 c896fe29 bellard
    /* add x(r1), r0 */
579 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) - 
580 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_read));
581 c896fe29 bellard
#else
582 c896fe29 bellard
    r0 = addr_reg;
583 c896fe29 bellard
#endif
584 c896fe29 bellard
585 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
586 c896fe29 bellard
    bswap = 1;
587 c896fe29 bellard
#else
588 c896fe29 bellard
    bswap = 0;
589 c896fe29 bellard
#endif
590 c896fe29 bellard
    switch(opc) {
591 c896fe29 bellard
    case 0:
592 c896fe29 bellard
        /* movzbl */
593 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0);
594 c896fe29 bellard
        break;
595 c896fe29 bellard
    case 0 | 4:
596 c896fe29 bellard
        /* movsbl */
597 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT, data_reg, r0, 0);
598 c896fe29 bellard
        break;
599 c896fe29 bellard
    case 1:
600 c896fe29 bellard
        /* movzwl */
601 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0);
602 c896fe29 bellard
        if (bswap) {
603 c896fe29 bellard
            /* rolw $8, data_reg */
604 c896fe29 bellard
            tcg_out8(s, 0x66); 
605 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
606 c896fe29 bellard
            tcg_out8(s, 8);
607 c896fe29 bellard
        }
608 c896fe29 bellard
        break;
609 c896fe29 bellard
    case 1 | 4:
610 c896fe29 bellard
        /* movswl */
611 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT, data_reg, r0, 0);
612 c896fe29 bellard
        if (bswap) {
613 c896fe29 bellard
            /* rolw $8, data_reg */
614 c896fe29 bellard
            tcg_out8(s, 0x66); 
615 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, data_reg);
616 c896fe29 bellard
            tcg_out8(s, 8);
617 c896fe29 bellard
618 c896fe29 bellard
            /* movswl data_reg, data_reg */
619 c896fe29 bellard
            tcg_out_modrm(s, 0xbf | P_EXT, data_reg, data_reg);
620 c896fe29 bellard
        }
621 c896fe29 bellard
        break;
622 c896fe29 bellard
    case 2:
623 c896fe29 bellard
        /* movl (r0), data_reg */
624 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
625 c896fe29 bellard
        if (bswap) {
626 c896fe29 bellard
            /* bswap */
627 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
628 c896fe29 bellard
        }
629 c896fe29 bellard
        break;
630 c896fe29 bellard
    case 3:
631 c896fe29 bellard
        /* XXX: could be nicer */
632 c896fe29 bellard
        if (r0 == data_reg) {
633 c896fe29 bellard
            r1 = TCG_REG_EDX;
634 c896fe29 bellard
            if (r1 == data_reg)
635 c896fe29 bellard
                r1 = TCG_REG_EAX;
636 c896fe29 bellard
            tcg_out_mov(s, r1, r0);
637 c896fe29 bellard
            r0 = r1;
638 c896fe29 bellard
        }
639 c896fe29 bellard
        if (!bswap) {
640 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0);
641 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 4);
642 c896fe29 bellard
        } else {
643 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 4);
644 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
645 c896fe29 bellard
646 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, 0);
647 c896fe29 bellard
            /* bswap */
648 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + data_reg2) | P_EXT);
649 c896fe29 bellard
        }
650 c896fe29 bellard
        break;
651 c896fe29 bellard
    default:
652 c896fe29 bellard
        tcg_abort();
653 c896fe29 bellard
    }
654 c896fe29 bellard
655 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
656 c896fe29 bellard
    /* label2: */
657 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
658 c896fe29 bellard
#endif
659 c896fe29 bellard
}
660 c896fe29 bellard
661 c896fe29 bellard
662 c896fe29 bellard
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
663 c896fe29 bellard
                            int opc)
664 c896fe29 bellard
{
665 c896fe29 bellard
    int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
666 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
667 c896fe29 bellard
    uint8_t *label1_ptr, *label2_ptr;
668 c896fe29 bellard
#endif
669 c896fe29 bellard
#if TARGET_LONG_BITS == 64
670 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
671 c896fe29 bellard
    uint8_t *label3_ptr;
672 c896fe29 bellard
#endif
673 c896fe29 bellard
    int addr_reg2;
674 c896fe29 bellard
#endif
675 c896fe29 bellard
676 c896fe29 bellard
    data_reg = *args++;
677 c896fe29 bellard
    if (opc == 3)
678 c896fe29 bellard
        data_reg2 = *args++;
679 c896fe29 bellard
    else
680 c896fe29 bellard
        data_reg2 = 0;
681 c896fe29 bellard
    addr_reg = *args++;
682 c896fe29 bellard
#if TARGET_LONG_BITS == 64
683 c896fe29 bellard
    addr_reg2 = *args++;
684 c896fe29 bellard
#endif
685 c896fe29 bellard
    mem_index = *args;
686 c896fe29 bellard
687 c896fe29 bellard
    s_bits = opc;
688 c896fe29 bellard
689 c896fe29 bellard
    r0 = TCG_REG_EAX;
690 c896fe29 bellard
    r1 = TCG_REG_EDX;
691 c896fe29 bellard
692 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
693 c896fe29 bellard
    tcg_out_mov(s, r1, addr_reg); 
694 c896fe29 bellard
695 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg); 
696 c896fe29 bellard
 
697 c896fe29 bellard
    tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */
698 c896fe29 bellard
    tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 
699 c896fe29 bellard
    
700 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */
701 c896fe29 bellard
    tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
702 c896fe29 bellard
    
703 c896fe29 bellard
    tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
704 c896fe29 bellard
    tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
705 c896fe29 bellard
706 c896fe29 bellard
    tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */
707 c896fe29 bellard
    tcg_out8(s, 0x80 | (r1 << 3) | 0x04);
708 c896fe29 bellard
    tcg_out8(s, (5 << 3) | r1);
709 c896fe29 bellard
    tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
710 c896fe29 bellard
711 c896fe29 bellard
    /* cmp 0(r1), r0 */
712 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, r0, r1, 0);
713 c896fe29 bellard
    
714 c896fe29 bellard
    tcg_out_mov(s, r0, addr_reg);
715 c896fe29 bellard
    
716 c896fe29 bellard
#if TARGET_LONG_BITS == 32
717 c896fe29 bellard
    /* je label1 */
718 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
719 c896fe29 bellard
    label1_ptr = s->code_ptr;
720 c896fe29 bellard
    s->code_ptr++;
721 c896fe29 bellard
#else
722 c896fe29 bellard
    /* jne label3 */
723 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JNE);
724 c896fe29 bellard
    label3_ptr = s->code_ptr;
725 c896fe29 bellard
    s->code_ptr++;
726 c896fe29 bellard
    
727 c896fe29 bellard
    /* cmp 4(r1), addr_reg2 */
728 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4);
729 c896fe29 bellard
730 c896fe29 bellard
    /* je label1 */
731 c896fe29 bellard
    tcg_out8(s, 0x70 + JCC_JE);
732 c896fe29 bellard
    label1_ptr = s->code_ptr;
733 c896fe29 bellard
    s->code_ptr++;
734 c896fe29 bellard
    
735 c896fe29 bellard
    /* label3: */
736 c896fe29 bellard
    *label3_ptr = s->code_ptr - label3_ptr - 1;
737 c896fe29 bellard
#endif
738 c896fe29 bellard
739 c896fe29 bellard
    /* XXX: move that code at the end of the TB */
740 c896fe29 bellard
#if TARGET_LONG_BITS == 32
741 c896fe29 bellard
    if (opc == 3) {
742 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_EDX, data_reg);
743 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_ECX, data_reg2);
744 c896fe29 bellard
        tcg_out8(s, 0x6a); /* push Ib */
745 c896fe29 bellard
        tcg_out8(s, mem_index);
746 c896fe29 bellard
        tcg_out8(s, 0xe8);
747 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
748 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
749 c896fe29 bellard
        tcg_out_addi(s, TCG_REG_ESP, 4);
750 c896fe29 bellard
    } else {
751 c896fe29 bellard
        switch(opc) {
752 c896fe29 bellard
        case 0:
753 c896fe29 bellard
            /* movzbl */
754 c896fe29 bellard
            tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_EDX, data_reg);
755 c896fe29 bellard
            break;
756 c896fe29 bellard
        case 1:
757 c896fe29 bellard
            /* movzwl */
758 c896fe29 bellard
            tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_EDX, data_reg);
759 c896fe29 bellard
            break;
760 c896fe29 bellard
        case 2:
761 c896fe29 bellard
            tcg_out_mov(s, TCG_REG_EDX, data_reg);
762 c896fe29 bellard
            break;
763 c896fe29 bellard
        }
764 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index);
765 c896fe29 bellard
        tcg_out8(s, 0xe8);
766 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
767 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
768 c896fe29 bellard
    }
769 c896fe29 bellard
#else
770 c896fe29 bellard
    if (opc == 3) {
771 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
772 c896fe29 bellard
        tcg_out8(s, 0x6a); /* push Ib */
773 c896fe29 bellard
        tcg_out8(s, mem_index);
774 c896fe29 bellard
        tcg_out_opc(s, 0x50 + data_reg2); /* push */
775 c896fe29 bellard
        tcg_out_opc(s, 0x50 + data_reg); /* push */
776 c896fe29 bellard
        tcg_out8(s, 0xe8);
777 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
778 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
779 c896fe29 bellard
        tcg_out_addi(s, TCG_REG_ESP, 12);
780 c896fe29 bellard
    } else {
781 c896fe29 bellard
        tcg_out_mov(s, TCG_REG_EDX, addr_reg2);
782 c896fe29 bellard
        switch(opc) {
783 c896fe29 bellard
        case 0:
784 c896fe29 bellard
            /* movzbl */
785 c896fe29 bellard
            tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_ECX, data_reg);
786 c896fe29 bellard
            break;
787 c896fe29 bellard
        case 1:
788 c896fe29 bellard
            /* movzwl */
789 c896fe29 bellard
            tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_ECX, data_reg);
790 c896fe29 bellard
            break;
791 c896fe29 bellard
        case 2:
792 c896fe29 bellard
            tcg_out_mov(s, TCG_REG_ECX, data_reg);
793 c896fe29 bellard
            break;
794 c896fe29 bellard
        }
795 c896fe29 bellard
        tcg_out8(s, 0x6a); /* push Ib */
796 c896fe29 bellard
        tcg_out8(s, mem_index);
797 c896fe29 bellard
        tcg_out8(s, 0xe8);
798 c896fe29 bellard
        tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - 
799 c896fe29 bellard
                  (tcg_target_long)s->code_ptr - 4);
800 c896fe29 bellard
        tcg_out_addi(s, TCG_REG_ESP, 4);
801 c896fe29 bellard
    }
802 c896fe29 bellard
#endif
803 c896fe29 bellard
    
804 c896fe29 bellard
    /* jmp label2 */
805 c896fe29 bellard
    tcg_out8(s, 0xeb);
806 c896fe29 bellard
    label2_ptr = s->code_ptr;
807 c896fe29 bellard
    s->code_ptr++;
808 c896fe29 bellard
    
809 c896fe29 bellard
    /* label1: */
810 c896fe29 bellard
    *label1_ptr = s->code_ptr - label1_ptr - 1;
811 c896fe29 bellard
812 c896fe29 bellard
    /* add x(r1), r0 */
813 c896fe29 bellard
    tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) - 
814 c896fe29 bellard
                         offsetof(CPUTLBEntry, addr_write));
815 c896fe29 bellard
#else
816 c896fe29 bellard
    r0 = addr_reg;
817 c896fe29 bellard
#endif
818 c896fe29 bellard
819 c896fe29 bellard
#ifdef TARGET_WORDS_BIGENDIAN
820 c896fe29 bellard
    bswap = 1;
821 c896fe29 bellard
#else
822 c896fe29 bellard
    bswap = 0;
823 c896fe29 bellard
#endif
824 c896fe29 bellard
    switch(opc) {
825 c896fe29 bellard
    case 0:
826 c896fe29 bellard
        /* movb */
827 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x88, data_reg, r0, 0);
828 c896fe29 bellard
        break;
829 c896fe29 bellard
    case 1:
830 c896fe29 bellard
        if (bswap) {
831 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
832 c896fe29 bellard
            tcg_out8(s, 0x66); /* rolw $8, %ecx */
833 c896fe29 bellard
            tcg_out_modrm(s, 0xc1, 0, r1);
834 c896fe29 bellard
            tcg_out8(s, 8);
835 c896fe29 bellard
            data_reg = r1;
836 c896fe29 bellard
        }
837 c896fe29 bellard
        /* movw */
838 c896fe29 bellard
        tcg_out8(s, 0x66);
839 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
840 c896fe29 bellard
        break;
841 c896fe29 bellard
    case 2:
842 c896fe29 bellard
        if (bswap) {
843 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
844 c896fe29 bellard
            /* bswap data_reg */
845 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT);
846 c896fe29 bellard
            data_reg = r1;
847 c896fe29 bellard
        }
848 c896fe29 bellard
        /* movl */
849 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
850 c896fe29 bellard
        break;
851 c896fe29 bellard
    case 3:
852 c896fe29 bellard
        if (bswap) {
853 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg2);
854 c896fe29 bellard
            /* bswap data_reg */
855 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT);
856 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, r1, r0, 0);
857 c896fe29 bellard
            tcg_out_mov(s, r1, data_reg);
858 c896fe29 bellard
            /* bswap data_reg */
859 c896fe29 bellard
            tcg_out_opc(s, (0xc8 + r1) | P_EXT);
860 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, r1, r0, 4);
861 c896fe29 bellard
        } else {
862 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0);
863 c896fe29 bellard
            tcg_out_modrm_offset(s, 0x89, data_reg2, r0, 4);
864 c896fe29 bellard
        }
865 c896fe29 bellard
        break;
866 c896fe29 bellard
    default:
867 c896fe29 bellard
        tcg_abort();
868 c896fe29 bellard
    }
869 c896fe29 bellard
870 c896fe29 bellard
#if defined(CONFIG_SOFTMMU)
871 c896fe29 bellard
    /* label2: */
872 c896fe29 bellard
    *label2_ptr = s->code_ptr - label2_ptr - 1;
873 c896fe29 bellard
#endif
874 c896fe29 bellard
}
875 c896fe29 bellard
876 c896fe29 bellard
static inline void tcg_out_op(TCGContext *s, int opc, 
877 c896fe29 bellard
                              const TCGArg *args, const int *const_args)
878 c896fe29 bellard
{
879 c896fe29 bellard
    int c;
880 c896fe29 bellard
    
881 c896fe29 bellard
    switch(opc) {
882 c896fe29 bellard
    case INDEX_op_exit_tb:
883 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
884 b03cce8e bellard
        tcg_out8(s, 0xe9); /* jmp tb_ret_addr */
885 b03cce8e bellard
        tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
886 c896fe29 bellard
        break;
887 c896fe29 bellard
    case INDEX_op_goto_tb:
888 c896fe29 bellard
        if (s->tb_jmp_offset) {
889 c896fe29 bellard
            /* direct jump method */
890 c896fe29 bellard
            tcg_out8(s, 0xe9); /* jmp im */
891 c896fe29 bellard
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
892 c896fe29 bellard
            tcg_out32(s, 0);
893 c896fe29 bellard
        } else {
894 c896fe29 bellard
            /* indirect jump method */
895 c896fe29 bellard
            /* jmp Ev */
896 c896fe29 bellard
            tcg_out_modrm_offset(s, 0xff, 4, -1, 
897 c896fe29 bellard
                                 (tcg_target_long)(s->tb_next + args[0]));
898 c896fe29 bellard
        }
899 c896fe29 bellard
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
900 c896fe29 bellard
        break;
901 c896fe29 bellard
    case INDEX_op_call:
902 c896fe29 bellard
        if (const_args[0]) {
903 c896fe29 bellard
            tcg_out8(s, 0xe8);
904 c896fe29 bellard
            tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
905 c896fe29 bellard
        } else {
906 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 2, args[0]);
907 c896fe29 bellard
        }
908 c896fe29 bellard
        break;
909 c896fe29 bellard
    case INDEX_op_jmp:
910 c896fe29 bellard
        if (const_args[0]) {
911 c896fe29 bellard
            tcg_out8(s, 0xe9);
912 c896fe29 bellard
            tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
913 c896fe29 bellard
        } else {
914 c896fe29 bellard
            tcg_out_modrm(s, 0xff, 4, args[0]);
915 c896fe29 bellard
        }
916 c896fe29 bellard
        break;
917 c896fe29 bellard
    case INDEX_op_br:
918 c896fe29 bellard
        tcg_out_jxx(s, JCC_JMP, args[0]);
919 c896fe29 bellard
        break;
920 c896fe29 bellard
    case INDEX_op_movi_i32:
921 c896fe29 bellard
        tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
922 c896fe29 bellard
        break;
923 c896fe29 bellard
    case INDEX_op_ld8u_i32:
924 c896fe29 bellard
        /* movzbl */
925 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
926 c896fe29 bellard
        break;
927 c896fe29 bellard
    case INDEX_op_ld8s_i32:
928 c896fe29 bellard
        /* movsbl */
929 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
930 c896fe29 bellard
        break;
931 c896fe29 bellard
    case INDEX_op_ld16u_i32:
932 c896fe29 bellard
        /* movzwl */
933 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
934 c896fe29 bellard
        break;
935 c896fe29 bellard
    case INDEX_op_ld16s_i32:
936 c896fe29 bellard
        /* movswl */
937 c896fe29 bellard
        tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
938 c896fe29 bellard
        break;
939 c896fe29 bellard
    case INDEX_op_ld_i32:
940 c896fe29 bellard
        /* movl */
941 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
942 c896fe29 bellard
        break;
943 c896fe29 bellard
    case INDEX_op_st8_i32:
944 c896fe29 bellard
        /* movb */
945 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]);
946 c896fe29 bellard
        break;
947 c896fe29 bellard
    case INDEX_op_st16_i32:
948 c896fe29 bellard
        /* movw */
949 c896fe29 bellard
        tcg_out8(s, 0x66);
950 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
951 c896fe29 bellard
        break;
952 c896fe29 bellard
    case INDEX_op_st_i32:
953 c896fe29 bellard
        /* movl */
954 c896fe29 bellard
        tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
955 c896fe29 bellard
        break;
956 c896fe29 bellard
    case INDEX_op_sub_i32:
957 c896fe29 bellard
        c = ARITH_SUB;
958 c896fe29 bellard
        goto gen_arith;
959 c896fe29 bellard
    case INDEX_op_and_i32:
960 c896fe29 bellard
        c = ARITH_AND;
961 c896fe29 bellard
        goto gen_arith;
962 c896fe29 bellard
    case INDEX_op_or_i32:
963 c896fe29 bellard
        c = ARITH_OR;
964 c896fe29 bellard
        goto gen_arith;
965 c896fe29 bellard
    case INDEX_op_xor_i32:
966 c896fe29 bellard
        c = ARITH_XOR;
967 c896fe29 bellard
        goto gen_arith;
968 c896fe29 bellard
    case INDEX_op_add_i32:
969 c896fe29 bellard
        c = ARITH_ADD;
970 c896fe29 bellard
    gen_arith:
971 c896fe29 bellard
        if (const_args[2]) {
972 c896fe29 bellard
            tgen_arithi(s, c, args[0], args[2]);
973 c896fe29 bellard
        } else {
974 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
975 c896fe29 bellard
        }
976 c896fe29 bellard
        break;
977 c896fe29 bellard
    case INDEX_op_mul_i32:
978 c896fe29 bellard
        if (const_args[2]) {
979 c896fe29 bellard
            int32_t val;
980 c896fe29 bellard
            val = args[2];
981 c896fe29 bellard
            if (val == (int8_t)val) {
982 c896fe29 bellard
                tcg_out_modrm(s, 0x6b, args[0], args[0]);
983 c896fe29 bellard
                tcg_out8(s, val);
984 c896fe29 bellard
            } else {
985 c896fe29 bellard
                tcg_out_modrm(s, 0x69, args[0], args[0]);
986 c896fe29 bellard
                tcg_out32(s, val);
987 c896fe29 bellard
            }
988 c896fe29 bellard
        } else {
989 c896fe29 bellard
            tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
990 c896fe29 bellard
        }
991 c896fe29 bellard
        break;
992 c896fe29 bellard
    case INDEX_op_mulu2_i32:
993 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 4, args[3]);
994 c896fe29 bellard
        break;
995 c896fe29 bellard
    case INDEX_op_div2_i32:
996 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 7, args[4]);
997 c896fe29 bellard
        break;
998 c896fe29 bellard
    case INDEX_op_divu2_i32:
999 c896fe29 bellard
        tcg_out_modrm(s, 0xf7, 6, args[4]);
1000 c896fe29 bellard
        break;
1001 c896fe29 bellard
    case INDEX_op_shl_i32:
1002 c896fe29 bellard
        c = SHIFT_SHL;
1003 c896fe29 bellard
    gen_shift32:
1004 c896fe29 bellard
        if (const_args[2]) {
1005 c896fe29 bellard
            if (args[2] == 1) {
1006 c896fe29 bellard
                tcg_out_modrm(s, 0xd1, c, args[0]);
1007 c896fe29 bellard
            } else {
1008 c896fe29 bellard
                tcg_out_modrm(s, 0xc1, c, args[0]);
1009 c896fe29 bellard
                tcg_out8(s, args[2]);
1010 c896fe29 bellard
            }
1011 c896fe29 bellard
        } else {
1012 c896fe29 bellard
            tcg_out_modrm(s, 0xd3, c, args[0]);
1013 c896fe29 bellard
        }
1014 c896fe29 bellard
        break;
1015 c896fe29 bellard
    case INDEX_op_shr_i32:
1016 c896fe29 bellard
        c = SHIFT_SHR;
1017 c896fe29 bellard
        goto gen_shift32;
1018 c896fe29 bellard
    case INDEX_op_sar_i32:
1019 c896fe29 bellard
        c = SHIFT_SAR;
1020 c896fe29 bellard
        goto gen_shift32;
1021 c896fe29 bellard
        
1022 c896fe29 bellard
    case INDEX_op_add2_i32:
1023 c896fe29 bellard
        if (const_args[4]) 
1024 c896fe29 bellard
            tgen_arithi(s, ARITH_ADD, args[0], args[4]);
1025 c896fe29 bellard
        else
1026 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_ADD << 3), args[4], args[0]);
1027 c896fe29 bellard
        if (const_args[5]) 
1028 c896fe29 bellard
            tgen_arithi(s, ARITH_ADC, args[1], args[5]);
1029 c896fe29 bellard
        else
1030 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_ADC << 3), args[5], args[1]);
1031 c896fe29 bellard
        break;
1032 c896fe29 bellard
    case INDEX_op_sub2_i32:
1033 c896fe29 bellard
        if (const_args[4]) 
1034 c896fe29 bellard
            tgen_arithi(s, ARITH_SUB, args[0], args[4]);
1035 c896fe29 bellard
        else
1036 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_SUB << 3), args[4], args[0]);
1037 c896fe29 bellard
        if (const_args[5]) 
1038 c896fe29 bellard
            tgen_arithi(s, ARITH_SBB, args[1], args[5]);
1039 c896fe29 bellard
        else
1040 c896fe29 bellard
            tcg_out_modrm(s, 0x01 | (ARITH_SBB << 3), args[5], args[1]);
1041 c896fe29 bellard
        break;
1042 c896fe29 bellard
    case INDEX_op_brcond_i32:
1043 c896fe29 bellard
        tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
1044 c896fe29 bellard
        break;
1045 c896fe29 bellard
    case INDEX_op_brcond2_i32:
1046 c896fe29 bellard
        tcg_out_brcond2(s, args, const_args);
1047 c896fe29 bellard
        break;
1048 c896fe29 bellard
1049 c896fe29 bellard
    case INDEX_op_qemu_ld8u:
1050 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0);
1051 c896fe29 bellard
        break;
1052 c896fe29 bellard
    case INDEX_op_qemu_ld8s:
1053 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 0 | 4);
1054 c896fe29 bellard
        break;
1055 c896fe29 bellard
    case INDEX_op_qemu_ld16u:
1056 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1);
1057 c896fe29 bellard
        break;
1058 c896fe29 bellard
    case INDEX_op_qemu_ld16s:
1059 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 1 | 4);
1060 c896fe29 bellard
        break;
1061 c896fe29 bellard
    case INDEX_op_qemu_ld32u:
1062 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 2);
1063 c896fe29 bellard
        break;
1064 c896fe29 bellard
    case INDEX_op_qemu_ld64:
1065 c896fe29 bellard
        tcg_out_qemu_ld(s, args, 3);
1066 c896fe29 bellard
        break;
1067 c896fe29 bellard
        
1068 c896fe29 bellard
    case INDEX_op_qemu_st8:
1069 c896fe29 bellard
        tcg_out_qemu_st(s, args, 0);
1070 c896fe29 bellard
        break;
1071 c896fe29 bellard
    case INDEX_op_qemu_st16:
1072 c896fe29 bellard
        tcg_out_qemu_st(s, args, 1);
1073 c896fe29 bellard
        break;
1074 c896fe29 bellard
    case INDEX_op_qemu_st32:
1075 c896fe29 bellard
        tcg_out_qemu_st(s, args, 2);
1076 c896fe29 bellard
        break;
1077 c896fe29 bellard
    case INDEX_op_qemu_st64:
1078 c896fe29 bellard
        tcg_out_qemu_st(s, args, 3);
1079 c896fe29 bellard
        break;
1080 c896fe29 bellard
1081 c896fe29 bellard
    default:
1082 c896fe29 bellard
        tcg_abort();
1083 c896fe29 bellard
    }
1084 c896fe29 bellard
}
1085 c896fe29 bellard
1086 c896fe29 bellard
static const TCGTargetOpDef x86_op_defs[] = {
1087 c896fe29 bellard
    { INDEX_op_exit_tb, { } },
1088 c896fe29 bellard
    { INDEX_op_goto_tb, { } },
1089 c896fe29 bellard
    { INDEX_op_call, { "ri" } },
1090 c896fe29 bellard
    { INDEX_op_jmp, { "ri" } },
1091 c896fe29 bellard
    { INDEX_op_br, { } },
1092 c896fe29 bellard
    { INDEX_op_mov_i32, { "r", "r" } },
1093 c896fe29 bellard
    { INDEX_op_movi_i32, { "r" } },
1094 c896fe29 bellard
    { INDEX_op_ld8u_i32, { "r", "r" } },
1095 c896fe29 bellard
    { INDEX_op_ld8s_i32, { "r", "r" } },
1096 c896fe29 bellard
    { INDEX_op_ld16u_i32, { "r", "r" } },
1097 c896fe29 bellard
    { INDEX_op_ld16s_i32, { "r", "r" } },
1098 c896fe29 bellard
    { INDEX_op_ld_i32, { "r", "r" } },
1099 c896fe29 bellard
    { INDEX_op_st8_i32, { "q", "r" } },
1100 c896fe29 bellard
    { INDEX_op_st16_i32, { "r", "r" } },
1101 c896fe29 bellard
    { INDEX_op_st_i32, { "r", "r" } },
1102 c896fe29 bellard
1103 c896fe29 bellard
    { INDEX_op_add_i32, { "r", "0", "ri" } },
1104 c896fe29 bellard
    { INDEX_op_sub_i32, { "r", "0", "ri" } },
1105 c896fe29 bellard
    { INDEX_op_mul_i32, { "r", "0", "ri" } },
1106 c896fe29 bellard
    { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
1107 c896fe29 bellard
    { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
1108 c896fe29 bellard
    { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
1109 c896fe29 bellard
    { INDEX_op_and_i32, { "r", "0", "ri" } },
1110 c896fe29 bellard
    { INDEX_op_or_i32, { "r", "0", "ri" } },
1111 c896fe29 bellard
    { INDEX_op_xor_i32, { "r", "0", "ri" } },
1112 c896fe29 bellard
1113 c896fe29 bellard
    { INDEX_op_shl_i32, { "r", "0", "ci" } },
1114 c896fe29 bellard
    { INDEX_op_shr_i32, { "r", "0", "ci" } },
1115 c896fe29 bellard
    { INDEX_op_sar_i32, { "r", "0", "ci" } },
1116 c896fe29 bellard
1117 c896fe29 bellard
    { INDEX_op_brcond_i32, { "r", "ri" } },
1118 c896fe29 bellard
1119 c896fe29 bellard
    { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1120 c896fe29 bellard
    { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
1121 c896fe29 bellard
    { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
1122 c896fe29 bellard
1123 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1124 c896fe29 bellard
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1125 c896fe29 bellard
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1126 c896fe29 bellard
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1127 c896fe29 bellard
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1128 c896fe29 bellard
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1129 c896fe29 bellard
    { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1130 c896fe29 bellard
1131 c896fe29 bellard
    { INDEX_op_qemu_st8, { "cb", "L" } },
1132 c896fe29 bellard
    { INDEX_op_qemu_st16, { "L", "L" } },
1133 c896fe29 bellard
    { INDEX_op_qemu_st32, { "L", "L" } },
1134 c896fe29 bellard
    { INDEX_op_qemu_st64, { "L", "L", "L" } },
1135 c896fe29 bellard
#else
1136 c896fe29 bellard
    { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1137 c896fe29 bellard
    { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1138 c896fe29 bellard
    { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1139 c896fe29 bellard
    { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1140 c896fe29 bellard
    { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1141 c896fe29 bellard
    { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
1142 c896fe29 bellard
1143 c896fe29 bellard
    { INDEX_op_qemu_st8, { "cb", "L", "L" } },
1144 c896fe29 bellard
    { INDEX_op_qemu_st16, { "L", "L", "L" } },
1145 c896fe29 bellard
    { INDEX_op_qemu_st32, { "L", "L", "L" } },
1146 c896fe29 bellard
    { INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
1147 c896fe29 bellard
#endif
1148 c896fe29 bellard
    { -1 },
1149 c896fe29 bellard
};
1150 c896fe29 bellard
1151 b03cce8e bellard
static int tcg_target_callee_save_regs[] = {
1152 b03cce8e bellard
    /*    TCG_REG_EBP, */ /* currently used for the global env, so no
1153 b03cce8e bellard
                             need to save */
1154 b03cce8e bellard
    TCG_REG_EBX,
1155 b03cce8e bellard
    TCG_REG_ESI,
1156 b03cce8e bellard
    TCG_REG_EDI,
1157 b03cce8e bellard
};
1158 b03cce8e bellard
1159 b03cce8e bellard
static inline void tcg_out_push(TCGContext *s, int reg)
1160 b03cce8e bellard
{
1161 b03cce8e bellard
    tcg_out_opc(s, 0x50 + reg);
1162 b03cce8e bellard
}
1163 b03cce8e bellard
1164 b03cce8e bellard
static inline void tcg_out_pop(TCGContext *s, int reg)
1165 b03cce8e bellard
{
1166 b03cce8e bellard
    tcg_out_opc(s, 0x58 + reg);
1167 b03cce8e bellard
}
1168 b03cce8e bellard
1169 b03cce8e bellard
/* Generate global QEMU prologue and epilogue code */
1170 b03cce8e bellard
void tcg_target_qemu_prologue(TCGContext *s)
1171 b03cce8e bellard
{
1172 b03cce8e bellard
    int i, frame_size, push_size, stack_addend;
1173 b03cce8e bellard
    
1174 b03cce8e bellard
    /* TB prologue */
1175 b03cce8e bellard
    /* save all callee saved registers */
1176 b03cce8e bellard
    for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1177 b03cce8e bellard
        tcg_out_push(s, tcg_target_callee_save_regs[i]);
1178 b03cce8e bellard
    }
1179 b03cce8e bellard
    /* reserve some stack space */
1180 b03cce8e bellard
    push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
1181 b03cce8e bellard
    frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
1182 b03cce8e bellard
    frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & 
1183 b03cce8e bellard
        ~(TCG_TARGET_STACK_ALIGN - 1);
1184 b03cce8e bellard
    stack_addend = frame_size - push_size;
1185 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
1186 b03cce8e bellard
1187 b03cce8e bellard
    tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp *%eax */
1188 b03cce8e bellard
    
1189 b03cce8e bellard
    /* TB epilogue */
1190 b03cce8e bellard
    tb_ret_addr = s->code_ptr;
1191 b03cce8e bellard
    tcg_out_addi(s, TCG_REG_ESP, stack_addend);
1192 b03cce8e bellard
    for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
1193 b03cce8e bellard
        tcg_out_pop(s, tcg_target_callee_save_regs[i]);
1194 b03cce8e bellard
    }
1195 b03cce8e bellard
    tcg_out8(s, 0xc3); /* ret */
1196 b03cce8e bellard
}
1197 b03cce8e bellard
1198 c896fe29 bellard
void tcg_target_init(TCGContext *s)
1199 c896fe29 bellard
{
1200 c896fe29 bellard
    /* fail safe */
1201 c896fe29 bellard
    if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1202 c896fe29 bellard
        tcg_abort();
1203 c896fe29 bellard
1204 c896fe29 bellard
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
1205 c896fe29 bellard
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1206 c896fe29 bellard
                     (1 << TCG_REG_EAX) | 
1207 c896fe29 bellard
                     (1 << TCG_REG_EDX) | 
1208 c896fe29 bellard
                     (1 << TCG_REG_ECX));
1209 c896fe29 bellard
    
1210 c896fe29 bellard
    tcg_regset_clear(s->reserved_regs);
1211 c896fe29 bellard
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
1212 c896fe29 bellard
1213 c896fe29 bellard
    tcg_add_target_add_op_defs(x86_op_defs);
1214 c896fe29 bellard
}