Revision b068d6a7 hw/ppc.c
b/hw/ppc.c | ||
---|---|---|
424 | 424 |
void *opaque; |
425 | 425 |
}; |
426 | 426 |
|
427 |
static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, int64_t tb_offset) |
|
427 |
static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, |
|
428 |
int64_t tb_offset) |
|
428 | 429 |
{ |
429 | 430 |
/* TB time in tb periods */ |
430 | 431 |
return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset, |
... | ... | |
446 | 447 |
return tb & 0xFFFFFFFF; |
447 | 448 |
} |
448 | 449 |
|
449 |
static inline uint32_t _cpu_ppc_load_tbu (CPUState *env) |
|
450 |
static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
|
|
450 | 451 |
{ |
451 | 452 |
ppc_tb_t *tb_env = env->tb_env; |
452 | 453 |
uint64_t tb; |
... | ... | |
466 | 467 |
return _cpu_ppc_load_tbu(env); |
467 | 468 |
} |
468 | 469 |
|
469 |
static inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, int64_t *tb_offsetp, |
|
470 |
uint64_t value) |
|
470 |
static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, |
|
471 |
int64_t *tb_offsetp, |
|
472 |
uint64_t value) |
|
471 | 473 |
{ |
472 | 474 |
*tb_offsetp = muldiv64(value, ticks_per_sec, tb_env->tb_freq) |
473 | 475 |
- qemu_get_clock(vm_clock); |
... | ... | |
489 | 491 |
cpu_ppc_store_tb(tb_env, &tb_env->tb_offset, tb | (uint64_t)value); |
490 | 492 |
} |
491 | 493 |
|
492 |
static inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
|
494 |
static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
|
493 | 495 |
{ |
494 | 496 |
ppc_tb_t *tb_env = env->tb_env; |
495 | 497 |
uint64_t tb; |
... | ... | |
556 | 558 |
((uint64_t)value << 32) | tb); |
557 | 559 |
} |
558 | 560 |
|
559 |
static inline uint32_t _cpu_ppc_load_decr (CPUState *env, uint64_t *next) |
|
561 |
static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, |
|
562 |
uint64_t *next) |
|
560 | 563 |
{ |
561 | 564 |
ppc_tb_t *tb_env = env->tb_env; |
562 | 565 |
uint32_t decr; |
... | ... | |
605 | 608 |
/* When decrementer expires, |
606 | 609 |
* all we need to do is generate or queue a CPU exception |
607 | 610 |
*/ |
608 |
static inline void cpu_ppc_decr_excp (CPUState *env) |
|
611 |
static always_inline void cpu_ppc_decr_excp (CPUState *env)
|
|
609 | 612 |
{ |
610 | 613 |
/* Raise it */ |
611 | 614 |
#ifdef PPC_DEBUG_TB |
... | ... | |
616 | 619 |
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); |
617 | 620 |
} |
618 | 621 |
|
619 |
static inline void cpu_ppc_hdecr_excp (CPUState *env) |
|
622 |
static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
|
|
620 | 623 |
{ |
621 | 624 |
/* Raise it */ |
622 | 625 |
#ifdef PPC_DEBUG_TB |
... | ... | |
657 | 660 |
(*raise_excp)(env); |
658 | 661 |
} |
659 | 662 |
|
660 |
|
|
661 |
static inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
|
662 |
uint32_t value, int is_excp) |
|
663 |
static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
|
664 |
uint32_t value, int is_excp) |
|
663 | 665 |
{ |
664 | 666 |
ppc_tb_t *tb_env = env->tb_env; |
665 | 667 |
|
... | ... | |
678 | 680 |
} |
679 | 681 |
|
680 | 682 |
#if defined(TARGET_PPC64H) |
681 |
static inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr, |
|
682 |
uint32_t value, int is_excp) |
|
683 |
static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
|
|
684 |
uint32_t value, int is_excp)
|
|
683 | 685 |
{ |
684 | 686 |
ppc_tb_t *tb_env = env->tb_env; |
685 | 687 |
|
Also available in: Unified diff