Revision b068d6a7 target-ppc/translate.c

b/target-ppc/translate.c
53 53

  
54 54
#include "gen-op.h"
55 55

  
56
static inline void gen_set_T0 (target_ulong val)
56
static always_inline void gen_set_T0 (target_ulong val)
57 57
{
58 58
#if defined(TARGET_PPC64)
59 59
    if (val >> 32)
......
63 63
        gen_op_set_T0(val);
64 64
}
65 65

  
66
static inline void gen_set_T1 (target_ulong val)
66
static always_inline void gen_set_T1 (target_ulong val)
67 67
{
68 68
#if defined(TARGET_PPC64)
69 69
    if (val >> 32)
......
78 78
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
79 79
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
80 80
};                                                                            \
81
static inline void func(int n)                                                \
81
static always_inline void func (int n)                                        \
82 82
{                                                                             \
83 83
    NAME ## _table[n]();                                                      \
84 84
}
......
90 90
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
91 91
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
92 92
};                                                                            \
93
static inline void func(int n)                                                \
93
static always_inline void func (int n)                                        \
94 94
{                                                                             \
95 95
    NAME ## _table[n]();                                                      \
96 96
}
......
106 106
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
107 107
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
108 108
};                                                                            \
109
static inline void func(int n)                                                \
109
static always_inline void func (int n)                                        \
110 110
{                                                                             \
111 111
    NAME ## _table[n]();                                                      \
112 112
}
......
121 121
GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
122 122
GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
123 123
GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
124
static inline void gen_op_store_T0_fpscri (int n, uint8_t param)
124
static always_inline void gen_op_store_T0_fpscri (int n, uint8_t param)
125 125
{
126 126
    gen_op_set_T0(param);
127 127
    gen_op_store_T0_fpscr(n);
......
187 187
#endif
188 188
};
189 189

  
190
static inline void gen_set_Rc0 (DisasContext *ctx)
190
static always_inline void gen_set_Rc0 (DisasContext *ctx)
191 191
{
192 192
#if defined(TARGET_PPC64)
193 193
    if (ctx->sf_mode)
......
198 198
    gen_op_set_Rc0();
199 199
}
200 200

  
201
static inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
201
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
202 202
{
203 203
#if defined(TARGET_PPC64)
204 204
    if (ctx->sf_mode)
......
236 236
GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
237 237

  
238 238
/* Stop translation */
239
static inline void GEN_STOP (DisasContext *ctx)
239
static always_inline void GEN_STOP (DisasContext *ctx)
240 240
{
241 241
    gen_update_nip(ctx, ctx->nip);
242 242
    ctx->exception = POWERPC_EXCP_STOP;
243 243
}
244 244

  
245 245
/* No need to update nip here, as execution flow will change */
246
static inline void GEN_SYNC (DisasContext *ctx)
246
static always_inline void GEN_SYNC (DisasContext *ctx)
247 247
{
248 248
    ctx->exception = POWERPC_EXCP_SYNC;
249 249
}
......
267 267
/*****************************************************************************/
268 268
/***                           Instruction decoding                        ***/
269 269
#define EXTRACT_HELPER(name, shift, nb)                                       \
270
static inline uint32_t name (uint32_t opcode)                                 \
270
static always_inline uint32_t name (uint32_t opcode)                          \
271 271
{                                                                             \
272 272
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
273 273
}
274 274

  
275 275
#define EXTRACT_SHELPER(name, shift, nb)                                      \
276
static inline int32_t name (uint32_t opcode)                                  \
276
static always_inline int32_t name (uint32_t opcode)                           \
277 277
{                                                                             \
278 278
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
279 279
}
......
304 304
EXTRACT_HELPER(crbB, 11, 5);
305 305
/* SPR / TBL */
306 306
EXTRACT_HELPER(_SPR, 11, 10);
307
static inline uint32_t SPR (uint32_t opcode)
307
static always_inline uint32_t SPR (uint32_t opcode)
308 308
{
309 309
    uint32_t sprn = _SPR(opcode);
310 310

  
......
336 336
/* Displacement */
337 337
EXTRACT_SHELPER(d, 0, 16);
338 338
/* Immediate address */
339
static inline target_ulong LI (uint32_t opcode)
339
static always_inline target_ulong LI (uint32_t opcode)
340 340
{
341 341
    return (opcode >> 0) & 0x03FFFFFC;
342 342
}
343 343

  
344
static inline uint32_t BD (uint32_t opcode)
344
static always_inline uint32_t BD (uint32_t opcode)
345 345
{
346 346
    return (opcode >> 0) & 0xFFFC;
347 347
}
......
354 354
EXTRACT_HELPER(LK, 0, 1);
355 355

  
356 356
/* Create a mask between <start> and <end> bits */
357
static inline target_ulong MASK (uint32_t start, uint32_t end)
357
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
358 358
{
359 359
    target_ulong ret;
360 360

  
......
694 694
#endif
695 695

  
696 696
/* add    add.    addo    addo.    */
697
static inline void gen_op_addo (void)
697
static always_inline void gen_op_addo (void)
698 698
{
699 699
    gen_op_move_T2_T0();
700 700
    gen_op_add();
......
702 702
}
703 703
#if defined(TARGET_PPC64)
704 704
#define gen_op_add_64 gen_op_add
705
static inline void gen_op_addo_64 (void)
705
static always_inline void gen_op_addo_64 (void)
706 706
{
707 707
    gen_op_move_T2_T0();
708 708
    gen_op_add();
......
711 711
#endif
712 712
GEN_INT_ARITH2_64 (add,    0x1F, 0x0A, 0x08, PPC_INTEGER);
713 713
/* addc   addc.   addco   addco.   */
714
static inline void gen_op_addc (void)
714
static always_inline void gen_op_addc (void)
715 715
{
716 716
    gen_op_move_T2_T0();
717 717
    gen_op_add();
718 718
    gen_op_check_addc();
719 719
}
720
static inline void gen_op_addco (void)
720
static always_inline void gen_op_addco (void)
721 721
{
722 722
    gen_op_move_T2_T0();
723 723
    gen_op_add();
......
725 725
    gen_op_check_addo();
726 726
}
727 727
#if defined(TARGET_PPC64)
728
static inline void gen_op_addc_64 (void)
728
static always_inline void gen_op_addc_64 (void)
729 729
{
730 730
    gen_op_move_T2_T0();
731 731
    gen_op_add();
732 732
    gen_op_check_addc_64();
733 733
}
734
static inline void gen_op_addco_64 (void)
734
static always_inline void gen_op_addco_64 (void)
735 735
{
736 736
    gen_op_move_T2_T0();
737 737
    gen_op_add();
......
741 741
#endif
742 742
GEN_INT_ARITH2_64 (addc,   0x1F, 0x0A, 0x00, PPC_INTEGER);
743 743
/* adde   adde.   addeo   addeo.   */
744
static inline void gen_op_addeo (void)
744
static always_inline void gen_op_addeo (void)
745 745
{
746 746
    gen_op_move_T2_T0();
747 747
    gen_op_adde();
748 748
    gen_op_check_addo();
749 749
}
750 750
#if defined(TARGET_PPC64)
751
static inline void gen_op_addeo_64 (void)
751
static always_inline void gen_op_addeo_64 (void)
752 752
{
753 753
    gen_op_move_T2_T0();
754 754
    gen_op_adde_64();
......
757 757
#endif
758 758
GEN_INT_ARITH2_64 (adde,   0x1F, 0x0A, 0x04, PPC_INTEGER);
759 759
/* addme  addme.  addmeo  addmeo.  */
760
static inline void gen_op_addme (void)
760
static always_inline void gen_op_addme (void)
761 761
{
762 762
    gen_op_move_T1_T0();
763 763
    gen_op_add_me();
764 764
}
765 765
#if defined(TARGET_PPC64)
766
static inline void gen_op_addme_64 (void)
766
static always_inline void gen_op_addme_64 (void)
767 767
{
768 768
    gen_op_move_T1_T0();
769 769
    gen_op_add_me_64();
......
771 771
#endif
772 772
GEN_INT_ARITH1_64 (addme,  0x1F, 0x0A, 0x07, PPC_INTEGER);
773 773
/* addze  addze.  addzeo  addzeo.  */
774
static inline void gen_op_addze (void)
774
static always_inline void gen_op_addze (void)
775 775
{
776 776
    gen_op_move_T2_T0();
777 777
    gen_op_add_ze();
778 778
    gen_op_check_addc();
779 779
}
780
static inline void gen_op_addzeo (void)
780
static always_inline void gen_op_addzeo (void)
781 781
{
782 782
    gen_op_move_T2_T0();
783 783
    gen_op_add_ze();
......
785 785
    gen_op_check_addo();
786 786
}
787 787
#if defined(TARGET_PPC64)
788
static inline void gen_op_addze_64 (void)
788
static always_inline void gen_op_addze_64 (void)
789 789
{
790 790
    gen_op_move_T2_T0();
791 791
    gen_op_add_ze();
792 792
    gen_op_check_addc_64();
793 793
}
794
static inline void gen_op_addzeo_64 (void)
794
static always_inline void gen_op_addzeo_64 (void)
795 795
{
796 796
    gen_op_move_T2_T0();
797 797
    gen_op_add_ze();
......
813 813
/* neg    neg.    nego    nego.    */
814 814
GEN_INT_ARITH1_64 (neg,    0x1F, 0x08, 0x03, PPC_INTEGER);
815 815
/* subf   subf.   subfo   subfo.   */
816
static inline void gen_op_subfo (void)
816
static always_inline void gen_op_subfo (void)
817 817
{
818 818
    gen_op_move_T2_T0();
819 819
    gen_op_subf();
......
821 821
}
822 822
#if defined(TARGET_PPC64)
823 823
#define gen_op_subf_64 gen_op_subf
824
static inline void gen_op_subfo_64 (void)
824
static always_inline void gen_op_subfo_64 (void)
825 825
{
826 826
    gen_op_move_T2_T0();
827 827
    gen_op_subf();
......
830 830
#endif
831 831
GEN_INT_ARITH2_64 (subf,   0x1F, 0x08, 0x01, PPC_INTEGER);
832 832
/* subfc  subfc.  subfco  subfco.  */
833
static inline void gen_op_subfc (void)
833
static always_inline void gen_op_subfc (void)
834 834
{
835 835
    gen_op_subf();
836 836
    gen_op_check_subfc();
837 837
}
838
static inline void gen_op_subfco (void)
838
static always_inline void gen_op_subfco (void)
839 839
{
840 840
    gen_op_move_T2_T0();
841 841
    gen_op_subf();
......
843 843
    gen_op_check_subfo();
844 844
}
845 845
#if defined(TARGET_PPC64)
846
static inline void gen_op_subfc_64 (void)
846
static always_inline void gen_op_subfc_64 (void)
847 847
{
848 848
    gen_op_subf();
849 849
    gen_op_check_subfc_64();
850 850
}
851
static inline void gen_op_subfco_64 (void)
851
static always_inline void gen_op_subfco_64 (void)
852 852
{
853 853
    gen_op_move_T2_T0();
854 854
    gen_op_subf();
......
858 858
#endif
859 859
GEN_INT_ARITH2_64 (subfc,  0x1F, 0x08, 0x00, PPC_INTEGER);
860 860
/* subfe  subfe.  subfeo  subfeo.  */
861
static inline void gen_op_subfeo (void)
861
static always_inline void gen_op_subfeo (void)
862 862
{
863 863
    gen_op_move_T2_T0();
864 864
    gen_op_subfe();
......
866 866
}
867 867
#if defined(TARGET_PPC64)
868 868
#define gen_op_subfe_64 gen_op_subfe
869
static inline void gen_op_subfeo_64 (void)
869
static always_inline void gen_op_subfeo_64 (void)
870 870
{
871 871
    gen_op_move_T2_T0();
872 872
    gen_op_subfe_64();
......
1407 1407
    gen_##name(ctx, 1, 1);                                                    \
1408 1408
}
1409 1409

  
1410
static inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1410
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1411 1411
{
1412 1412
    if (mask >> 32)
1413 1413
        gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
......
1415 1415
        gen_op_andi_T0(mask);
1416 1416
}
1417 1417

  
1418
static inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1418
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1419 1419
{
1420 1420
    if (mask >> 32)
1421 1421
        gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
......
1423 1423
        gen_op_andi_T1(mask);
1424 1424
}
1425 1425

  
1426
static inline void gen_rldinm (DisasContext *ctx, uint32_t mb, uint32_t me,
1427
                               uint32_t sh)
1426
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1427
                                      uint32_t me, uint32_t sh)
1428 1428
{
1429 1429
    gen_op_load_gpr_T0(rS(ctx->opcode));
1430 1430
    if (likely(sh == 0)) {
......
1453 1453
        gen_set_Rc0(ctx);
1454 1454
}
1455 1455
/* rldicl - rldicl. */
1456
static inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1456
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1457 1457
{
1458 1458
    uint32_t sh, mb;
1459 1459

  
......
1463 1463
}
1464 1464
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1465 1465
/* rldicr - rldicr. */
1466
static inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1466
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1467 1467
{
1468 1468
    uint32_t sh, me;
1469 1469

  
......
1473 1473
}
1474 1474
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1475 1475
/* rldic - rldic. */
1476
static inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1476
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1477 1477
{
1478 1478
    uint32_t sh, mb;
1479 1479

  
......
1483 1483
}
1484 1484
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1485 1485

  
1486
static inline void gen_rldnm (DisasContext *ctx, uint32_t mb, uint32_t me)
1486
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1487
                                     uint32_t me)
1487 1488
{
1488 1489
    gen_op_load_gpr_T0(rS(ctx->opcode));
1489 1490
    gen_op_load_gpr_T1(rB(ctx->opcode));
......
1497 1498
}
1498 1499

  
1499 1500
/* rldcl - rldcl. */
1500
static inline void gen_rldcl (DisasContext *ctx, int mbn)
1501
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1501 1502
{
1502 1503
    uint32_t mb;
1503 1504

  
......
1506 1507
}
1507 1508
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1508 1509
/* rldcr - rldcr. */
1509
static inline void gen_rldcr (DisasContext *ctx, int men)
1510
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1510 1511
{
1511 1512
    uint32_t me;
1512 1513

  
......
1515 1516
}
1516 1517
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1517 1518
/* rldimi - rldimi. */
1518
static inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1519
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1519 1520
{
1520 1521
    uint64_t mask;
1521 1522
    uint32_t sh, mb;
......
1583 1584
/* srad & srad. */
1584 1585
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1585 1586
/* sradi & sradi. */
1586
static inline void gen_sradi (DisasContext *ctx, int n)
1587
static always_inline void gen_sradi (DisasContext *ctx, int n)
1587 1588
{
1588 1589
    uint64_t mask;
1589 1590
    int sh, mb, me;
......
1937 1938

  
1938 1939
/***                           Addressing modes                            ***/
1939 1940
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
1940
static inline void gen_addr_imm_index (DisasContext *ctx, target_long maskl)
1941
static always_inline void gen_addr_imm_index (DisasContext *ctx,
1942
                                              target_long maskl)
1941 1943
{
1942 1944
    target_long simm = SIMM(ctx->opcode);
1943 1945

  
......
1954 1956
#endif
1955 1957
}
1956 1958

  
1957
static inline void gen_addr_reg_index (DisasContext *ctx)
1959
static always_inline void gen_addr_reg_index (DisasContext *ctx)
1958 1960
{
1959 1961
    if (rA(ctx->opcode) == 0) {
1960 1962
        gen_op_load_gpr_T0(rB(ctx->opcode));
......
1968 1970
#endif
1969 1971
}
1970 1972

  
1971
static inline void gen_addr_register (DisasContext *ctx)
1973
static always_inline void gen_addr_register (DisasContext *ctx)
1972 1974
{
1973 1975
    if (rA(ctx->opcode) == 0) {
1974 1976
        gen_op_reset_T0();
......
2964 2966
GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2965 2967

  
2966 2968
/***                                Branch                                 ***/
2967
static inline void gen_goto_tb (DisasContext *ctx, int n, target_ulong dest)
2969
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2970
                                       target_ulong dest)
2968 2971
{
2969 2972
    TranslationBlock *tb;
2970 2973
    tb = ctx->tb;
......
2999 3002
    }
3000 3003
}
3001 3004

  
3002
static inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3005
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3003 3006
{
3004 3007
#if defined(TARGET_PPC64)
3005 3008
    if (ctx->sf_mode != 0 && (nip >> 32))
......
3039 3042
#define BCOND_LR  1
3040 3043
#define BCOND_CTR 2
3041 3044

  
3042
static inline void gen_bcond (DisasContext *ctx, int type)
3045
static always_inline void gen_bcond (DisasContext *ctx, int type)
3043 3046
{
3044 3047
    target_ulong target = 0;
3045 3048
    target_ulong li;
......
3399 3402
#endif
3400 3403

  
3401 3404
/* mfspr */
3402
static inline void gen_op_mfspr (DisasContext *ctx)
3405
static always_inline void gen_op_mfspr (DisasContext *ctx)
3403 3406
{
3404 3407
    void (*read_cb)(void *opaque, int sprn);
3405 3408
    uint32_t sprn = SPR(ctx->opcode);
......
3765 3768
#endif
3766 3769
#endif
3767 3770

  
3768
static inline void handler_dcbz (DisasContext *ctx, int dcache_line_size)
3771
static always_inline void handler_dcbz (DisasContext *ctx,
3772
                                        int dcache_line_size)
3769 3773
{
3770 3774
    int n;
3771 3775

  
......
4913 4917
}
4914 4918

  
4915 4919
/* All 405 MAC instructions are translated here */
4916
static inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3,
4917
                                         int ra, int rb, int rt, int Rc)
4920
static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4921
                                                int opc2, int opc3,
4922
                                                int ra, int rb, int rt, int Rc)
4918 4923
{
4919 4924
    gen_op_load_gpr_T0(ra);
4920 4925
    gen_op_load_gpr_T1(rb);
......
5551 5556
}
5552 5557

  
5553 5558
/* Handler for undefined SPE opcodes */
5554
static inline void gen_speundef (DisasContext *ctx)
5559
static always_inline void gen_speundef (DisasContext *ctx)
5555 5560
{
5556 5561
    GEN_EXCP_INVAL(ctx);
5557 5562
}
5558 5563

  
5559 5564
/* SPE load and stores */
5560
static inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5565
static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5561 5566
{
5562 5567
    target_long simm = rB(ctx->opcode);
5563 5568

  
......
5678 5683
#endif /* defined(CONFIG_USER_ONLY) */
5679 5684

  
5680 5685
#define GEN_SPE_LD(name, sh)                                                  \
5681
static inline void gen_evl##name (DisasContext *ctx)                          \
5686
static always_inline void gen_evl##name (DisasContext *ctx)                   \
5682 5687
{                                                                             \
5683 5688
    if (unlikely(!ctx->spe_enabled)) {                                        \
5684 5689
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5690 5695
}
5691 5696

  
5692 5697
#define GEN_SPE_LDX(name)                                                     \
5693
static inline void gen_evl##name##x (DisasContext *ctx)                       \
5698
static always_inline void gen_evl##name##x (DisasContext *ctx)                \
5694 5699
{                                                                             \
5695 5700
    if (unlikely(!ctx->spe_enabled)) {                                        \
5696 5701
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5707 5712
GEN_SPE_LDX(name)
5708 5713

  
5709 5714
#define GEN_SPE_ST(name, sh)                                                  \
5710
static inline void gen_evst##name (DisasContext *ctx)                         \
5715
static always_inline void gen_evst##name (DisasContext *ctx)                  \
5711 5716
{                                                                             \
5712 5717
    if (unlikely(!ctx->spe_enabled)) {                                        \
5713 5718
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5719 5724
}
5720 5725

  
5721 5726
#define GEN_SPE_STX(name)                                                     \
5722
static inline void gen_evst##name##x (DisasContext *ctx)                      \
5727
static always_inline void gen_evst##name##x (DisasContext *ctx)               \
5723 5728
{                                                                             \
5724 5729
    if (unlikely(!ctx->spe_enabled)) {                                        \
5725 5730
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5741 5746

  
5742 5747
/* SPE arithmetic and logic */
5743 5748
#define GEN_SPEOP_ARITH2(name)                                                \
5744
static inline void gen_##name (DisasContext *ctx)                             \
5749
static always_inline void gen_##name (DisasContext *ctx)                      \
5745 5750
{                                                                             \
5746 5751
    if (unlikely(!ctx->spe_enabled)) {                                        \
5747 5752
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5754 5759
}
5755 5760

  
5756 5761
#define GEN_SPEOP_ARITH1(name)                                                \
5757
static inline void gen_##name (DisasContext *ctx)                             \
5762
static always_inline void gen_##name (DisasContext *ctx)                      \
5758 5763
{                                                                             \
5759 5764
    if (unlikely(!ctx->spe_enabled)) {                                        \
5760 5765
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5766 5771
}
5767 5772

  
5768 5773
#define GEN_SPEOP_COMP(name)                                                  \
5769
static inline void gen_##name (DisasContext *ctx)                             \
5774
static always_inline void gen_##name (DisasContext *ctx)                      \
5770 5775
{                                                                             \
5771 5776
    if (unlikely(!ctx->spe_enabled)) {                                        \
5772 5777
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5806 5811
GEN_SPEOP_ARITH1(evrndw);
5807 5812
GEN_SPEOP_ARITH1(evcntlzw);
5808 5813
GEN_SPEOP_ARITH1(evcntlsw);
5809
static inline void gen_brinc (DisasContext *ctx)
5814
static always_inline void gen_brinc (DisasContext *ctx)
5810 5815
{
5811 5816
    /* Note: brinc is usable even if SPE is disabled */
5812 5817
    gen_op_load_gpr64_T0(rA(ctx->opcode));
......
5816 5821
}
5817 5822

  
5818 5823
#define GEN_SPEOP_ARITH_IMM2(name)                                            \
5819
static inline void gen_##name##i (DisasContext *ctx)                          \
5824
static always_inline void gen_##name##i (DisasContext *ctx)                   \
5820 5825
{                                                                             \
5821 5826
    if (unlikely(!ctx->spe_enabled)) {                                        \
5822 5827
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5829 5834
}
5830 5835

  
5831 5836
#define GEN_SPEOP_LOGIC_IMM2(name)                                            \
5832
static inline void gen_##name##i (DisasContext *ctx)                          \
5837
static always_inline void gen_##name##i (DisasContext *ctx)                   \
5833 5838
{                                                                             \
5834 5839
    if (unlikely(!ctx->spe_enabled)) {                                        \
5835 5840
        GEN_EXCP_NO_AP(ctx);                                                  \
......
5852 5857
#define gen_evsrwiu gen_evsrwui
5853 5858
GEN_SPEOP_LOGIC_IMM2(evrlw);
5854 5859

  
5855
static inline void gen_evsplati (DisasContext *ctx)
5860
static always_inline void gen_evsplati (DisasContext *ctx)
5856 5861
{
5857 5862
    int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5858 5863

  
......
5860 5865
    gen_op_store_T0_gpr64(rD(ctx->opcode));
5861 5866
}
5862 5867

  
5863
static inline void gen_evsplatfi (DisasContext *ctx)
5868
static always_inline void gen_evsplatfi (DisasContext *ctx)
5864 5869
{
5865 5870
    uint32_t imm = rA(ctx->opcode) << 27;
5866 5871

  
......
5901 5906
GEN_SPE(evcmpltu,       evcmplts,      0x19, 0x08, 0x00600000, PPC_SPE); ////
5902 5907
GEN_SPE(evcmpeq,        speundef,      0x1A, 0x08, 0x00600000, PPC_SPE); ////
5903 5908

  
5904
static inline void gen_evsel (DisasContext *ctx)
5909
static always_inline void gen_evsel (DisasContext *ctx)
5905 5910
{
5906 5911
    if (unlikely(!ctx->spe_enabled)) {
5907 5912
        GEN_EXCP_NO_AP(ctx);
......
5991 5996
#endif
5992 5997
#endif
5993 5998
#define _GEN_OP_SPE_STWWE(suffix)                                             \
5994
static inline void gen_op_spe_stwwe_##suffix (void)                           \
5999
static always_inline void gen_op_spe_stwwe_##suffix (void)                    \
5995 6000
{                                                                             \
5996 6001
    gen_op_srli32_T1_64();                                                    \
5997 6002
    gen_op_spe_stwwo_##suffix();                                              \
5998 6003
}
5999 6004
#define _GEN_OP_SPE_STWWE_LE(suffix)                                          \
6000
static inline void gen_op_spe_stwwe_le_##suffix (void)                        \
6005
static always_inline void gen_op_spe_stwwe_le_##suffix (void)                 \
6001 6006
{                                                                             \
6002 6007
    gen_op_srli32_T1_64();                                                    \
6003 6008
    gen_op_spe_stwwo_le_##suffix();                                           \
......
6006 6011
#define GEN_OP_SPE_STWWE(suffix)                                              \
6007 6012
_GEN_OP_SPE_STWWE(suffix);                                                    \
6008 6013
_GEN_OP_SPE_STWWE_LE(suffix);                                                 \
6009
static inline void gen_op_spe_stwwe_64_##suffix (void)                        \
6014
static always_inline void gen_op_spe_stwwe_64_##suffix (void)                 \
6010 6015
{                                                                             \
6011 6016
    gen_op_srli32_T1_64();                                                    \
6012 6017
    gen_op_spe_stwwo_64_##suffix();                                           \
6013 6018
}                                                                             \
6014
static inline void gen_op_spe_stwwe_le_64_##suffix (void)                     \
6019
static always_inline void gen_op_spe_stwwe_le_64_##suffix (void)              \
6015 6020
{                                                                             \
6016 6021
    gen_op_srli32_T1_64();                                                    \
6017 6022
    gen_op_spe_stwwo_le_64_##suffix();                                        \
......
6031 6036
GEN_SPEOP_ST(wwo, 2);
6032 6037

  
6033 6038
#define GEN_SPE_LDSPLAT(name, op, suffix)                                     \
6034
static inline void gen_op_spe_l##name##_##suffix (void)                       \
6039
static always_inline void gen_op_spe_l##name##_##suffix (void)                \
6035 6040
{                                                                             \
6036 6041
    gen_op_##op##_##suffix();                                                 \
6037 6042
    gen_op_splatw_T1_64();                                                    \
6038 6043
}
6039 6044

  
6040 6045
#define GEN_OP_SPE_LHE(suffix)                                                \
6041
static inline void gen_op_spe_lhe_##suffix (void)                             \
6046
static always_inline void gen_op_spe_lhe_##suffix (void)                      \
6042 6047
{                                                                             \
6043 6048
    gen_op_spe_lh_##suffix();                                                 \
6044 6049
    gen_op_sli16_T1_64();                                                     \
6045 6050
}
6046 6051

  
6047 6052
#define GEN_OP_SPE_LHX(suffix)                                                \
6048
static inline void gen_op_spe_lhx_##suffix (void)                             \
6053
static always_inline void gen_op_spe_lhx_##suffix (void)                      \
6049 6054
{                                                                             \
6050 6055
    gen_op_spe_lh_##suffix();                                                 \
6051 6056
    gen_op_extsh_T1_64();                                                     \
......
6221 6226

  
6222 6227
/***                      SPE floating-point extension                     ***/
6223 6228
#define GEN_SPEFPUOP_CONV(name)                                               \
6224
static inline void gen_##name (DisasContext *ctx)                             \
6229
static always_inline void gen_##name (DisasContext *ctx)                      \
6225 6230
{                                                                             \
6226 6231
    gen_op_load_gpr64_T0(rB(ctx->opcode));                                    \
6227 6232
    gen_op_##name();                                                          \
......
6376 6381

  
6377 6382
/*****************************************************************************/
6378 6383
/* Misc PowerPC helpers */
6379
static inline uint32_t load_xer (CPUState *env)
6384
static always_inline uint32_t load_xer (CPUState *env)
6380 6385
{
6381 6386
    return (xer_so << XER_SO) |
6382 6387
        (xer_ov << XER_OV) |
......
6507 6512
}
6508 6513

  
6509 6514
/*****************************************************************************/
6510
static inline int gen_intermediate_code_internal (CPUState *env,
6511
                                                  TranslationBlock *tb,
6512
                                                  int search_pc)
6515
static always_inline int gen_intermediate_code_internal (CPUState *env,
6516
                                                         TranslationBlock *tb,
6517
                                                         int search_pc)
6513 6518
{
6514 6519
    DisasContext ctx, *ctxp = &ctx;
6515 6520
    opc_handler_t **table, *handler;

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