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1
/*
2
 *  PowerPC emulation helpers for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include <stdarg.h>
21
#include <stdlib.h>
22
#include <stdio.h>
23
#include <string.h>
24
#include <inttypes.h>
25
#include <signal.h>
26
#include <assert.h>
27

    
28
#include "cpu.h"
29
#include "exec-all.h"
30

    
31
//#define DEBUG_MMU
32
//#define DEBUG_BATS
33
//#define DEBUG_SOFTWARE_TLB
34
//#define DEBUG_EXCEPTIONS
35
//#define FLUSH_ALL_TLBS
36

    
37
/*****************************************************************************/
38
/* PowerPC MMU emulation */
39

    
40
#if defined(CONFIG_USER_ONLY)
41
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42
                              int is_user, int is_softmmu)
43
{
44
    int exception, error_code;
45

    
46
    if (rw == 2) {
47
        exception = POWERPC_EXCP_ISI;
48
        error_code = 0x40000000;
49
    } else {
50
        exception = POWERPC_EXCP_DSI;
51
        error_code = 0x40000000;
52
        if (rw)
53
            error_code |= 0x02000000;
54
        env->spr[SPR_DAR] = address;
55
        env->spr[SPR_DSISR] = error_code;
56
    }
57
    env->exception_index = exception;
58
    env->error_code = error_code;
59

    
60
    return 1;
61
}
62

    
63
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64
{
65
    return addr;
66
}
67

    
68
#else
69
/* Common routines used by software and hardware TLBs emulation */
70
static always_inline int pte_is_valid (target_ulong pte0)
71
{
72
    return pte0 & 0x80000000 ? 1 : 0;
73
}
74

    
75
static always_inline void pte_invalidate (target_ulong *pte0)
76
{
77
    *pte0 &= ~0x80000000;
78
}
79

    
80
#if defined(TARGET_PPC64)
81
static always_inline int pte64_is_valid (target_ulong pte0)
82
{
83
    return pte0 & 0x0000000000000001ULL ? 1 : 0;
84
}
85

    
86
static always_inline void pte64_invalidate (target_ulong *pte0)
87
{
88
    *pte0 &= ~0x0000000000000001ULL;
89
}
90
#endif
91

    
92
#define PTE_PTEM_MASK 0x7FFFFFBF
93
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
94
#if defined(TARGET_PPC64)
95
#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97
#endif
98

    
99
static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
100
                                     target_ulong pte0, target_ulong pte1,
101
                                     int h, int rw)
102
{
103
    target_ulong ptem, mmask;
104
    int access, ret, pteh, ptev;
105

    
106
    access = 0;
107
    ret = -1;
108
    /* Check validity and table match */
109
#if defined(TARGET_PPC64)
110
    if (is_64b) {
111
        ptev = pte64_is_valid(pte0);
112
        pteh = (pte0 >> 1) & 1;
113
    } else
114
#endif
115
    {
116
        ptev = pte_is_valid(pte0);
117
        pteh = (pte0 >> 6) & 1;
118
    }
119
    if (ptev && h == pteh) {
120
        /* Check vsid & api */
121
#if defined(TARGET_PPC64)
122
        if (is_64b) {
123
            ptem = pte0 & PTE64_PTEM_MASK;
124
            mmask = PTE64_CHECK_MASK;
125
        } else
126
#endif
127
        {
128
            ptem = pte0 & PTE_PTEM_MASK;
129
            mmask = PTE_CHECK_MASK;
130
        }
131
        if (ptem == ctx->ptem) {
132
            if (ctx->raddr != (target_ulong)-1) {
133
                /* all matches should have equal RPN, WIMG & PP */
134
                if ((ctx->raddr & mmask) != (pte1 & mmask)) {
135
                    if (loglevel != 0)
136
                        fprintf(logfile, "Bad RPN/WIMG/PP\n");
137
                    return -3;
138
                }
139
            }
140
            /* Compute access rights */
141
            if (ctx->key == 0) {
142
                access = PAGE_READ;
143
                if ((pte1 & 0x00000003) != 0x3)
144
                    access |= PAGE_WRITE;
145
            } else {
146
                switch (pte1 & 0x00000003) {
147
                case 0x0:
148
                    access = 0;
149
                    break;
150
                case 0x1:
151
                case 0x3:
152
                    access = PAGE_READ;
153
                    break;
154
                case 0x2:
155
                    access = PAGE_READ | PAGE_WRITE;
156
                    break;
157
                }
158
            }
159
            /* Keep the matching PTE informations */
160
            ctx->raddr = pte1;
161
            ctx->prot = access;
162
            if ((rw == 0 && (access & PAGE_READ)) ||
163
                (rw == 1 && (access & PAGE_WRITE))) {
164
                /* Access granted */
165
#if defined (DEBUG_MMU)
166
                if (loglevel != 0)
167
                    fprintf(logfile, "PTE access granted !\n");
168
#endif
169
                ret = 0;
170
            } else {
171
                /* Access right violation */
172
#if defined (DEBUG_MMU)
173
                if (loglevel != 0)
174
                    fprintf(logfile, "PTE access rejected\n");
175
#endif
176
                ret = -2;
177
            }
178
        }
179
    }
180

    
181
    return ret;
182
}
183

    
184
static int pte32_check (mmu_ctx_t *ctx,
185
                        target_ulong pte0, target_ulong pte1, int h, int rw)
186
{
187
    return _pte_check(ctx, 0, pte0, pte1, h, rw);
188
}
189

    
190
#if defined(TARGET_PPC64)
191
static int pte64_check (mmu_ctx_t *ctx,
192
                        target_ulong pte0, target_ulong pte1, int h, int rw)
193
{
194
    return _pte_check(ctx, 1, pte0, pte1, h, rw);
195
}
196
#endif
197

    
198
static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
199
                             int ret, int rw)
200
{
201
    int store = 0;
202

    
203
    /* Update page flags */
204
    if (!(*pte1p & 0x00000100)) {
205
        /* Update accessed flag */
206
        *pte1p |= 0x00000100;
207
        store = 1;
208
    }
209
    if (!(*pte1p & 0x00000080)) {
210
        if (rw == 1 && ret == 0) {
211
            /* Update changed flag */
212
            *pte1p |= 0x00000080;
213
            store = 1;
214
        } else {
215
            /* Force page fault for first write access */
216
            ctx->prot &= ~PAGE_WRITE;
217
        }
218
    }
219

    
220
    return store;
221
}
222

    
223
/* Software driven TLB helpers */
224
static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
225
                              int way, int is_code)
226
{
227
    int nr;
228

    
229
    /* Select TLB num in a way from address */
230
    nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
231
    /* Select TLB way */
232
    nr += env->tlb_per_way * way;
233
    /* 6xx have separate TLBs for instructions and data */
234
    if (is_code && env->id_tlbs == 1)
235
        nr += env->nb_tlb;
236

    
237
    return nr;
238
}
239

    
240
static void ppc6xx_tlb_invalidate_all (CPUState *env)
241
{
242
    ppc6xx_tlb_t *tlb;
243
    int nr, max;
244

    
245
#if defined (DEBUG_SOFTWARE_TLB) && 0
246
    if (loglevel != 0) {
247
        fprintf(logfile, "Invalidate all TLBs\n");
248
    }
249
#endif
250
    /* Invalidate all defined software TLB */
251
    max = env->nb_tlb;
252
    if (env->id_tlbs == 1)
253
        max *= 2;
254
    for (nr = 0; nr < max; nr++) {
255
        tlb = &env->tlb[nr].tlb6;
256
        pte_invalidate(&tlb->pte0);
257
    }
258
    tlb_flush(env, 1);
259
}
260

    
261
static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
262
                                                        target_ulong eaddr,
263
                                                        int is_code,
264
                                                        int match_epn)
265
{
266
#if !defined(FLUSH_ALL_TLBS)
267
    ppc6xx_tlb_t *tlb;
268
    int way, nr;
269

    
270
    /* Invalidate ITLB + DTLB, all ways */
271
    for (way = 0; way < env->nb_ways; way++) {
272
        nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
273
        tlb = &env->tlb[nr].tlb6;
274
        if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
275
#if defined (DEBUG_SOFTWARE_TLB)
276
            if (loglevel != 0) {
277
                fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
278
                        nr, env->nb_tlb, eaddr);
279
            }
280
#endif
281
            pte_invalidate(&tlb->pte0);
282
            tlb_flush_page(env, tlb->EPN);
283
        }
284
    }
285
#else
286
    /* XXX: PowerPC specification say this is valid as well */
287
    ppc6xx_tlb_invalidate_all(env);
288
#endif
289
}
290

    
291
static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
292
                                        int is_code)
293
{
294
    __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
295
}
296

    
297
void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
298
                       target_ulong pte0, target_ulong pte1)
299
{
300
    ppc6xx_tlb_t *tlb;
301
    int nr;
302

    
303
    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
304
    tlb = &env->tlb[nr].tlb6;
305
#if defined (DEBUG_SOFTWARE_TLB)
306
    if (loglevel != 0) {
307
        fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
308
                " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
309
    }
310
#endif
311
    /* Invalidate any pending reference in Qemu for this virtual address */
312
    __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
313
    tlb->pte0 = pte0;
314
    tlb->pte1 = pte1;
315
    tlb->EPN = EPN;
316
    /* Store last way for LRU mechanism */
317
    env->last_way = way;
318
}
319

    
320
static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
321
                             target_ulong eaddr, int rw, int access_type)
322
{
323
    ppc6xx_tlb_t *tlb;
324
    int nr, best, way;
325
    int ret;
326

    
327
    best = -1;
328
    ret = -1; /* No TLB found */
329
    for (way = 0; way < env->nb_ways; way++) {
330
        nr = ppc6xx_tlb_getnum(env, eaddr, way,
331
                               access_type == ACCESS_CODE ? 1 : 0);
332
        tlb = &env->tlb[nr].tlb6;
333
        /* This test "emulates" the PTE index match for hardware TLBs */
334
        if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
335
#if defined (DEBUG_SOFTWARE_TLB)
336
            if (loglevel != 0) {
337
                fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
338
                        "] <> " ADDRX "\n",
339
                        nr, env->nb_tlb,
340
                        pte_is_valid(tlb->pte0) ? "valid" : "inval",
341
                        tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
342
            }
343
#endif
344
            continue;
345
        }
346
#if defined (DEBUG_SOFTWARE_TLB)
347
        if (loglevel != 0) {
348
            fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
349
                    " %c %c\n",
350
                    nr, env->nb_tlb,
351
                    pte_is_valid(tlb->pte0) ? "valid" : "inval",
352
                    tlb->EPN, eaddr, tlb->pte1,
353
                    rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
354
        }
355
#endif
356
        switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
357
        case -3:
358
            /* TLB inconsistency */
359
            return -1;
360
        case -2:
361
            /* Access violation */
362
            ret = -2;
363
            best = nr;
364
            break;
365
        case -1:
366
        default:
367
            /* No match */
368
            break;
369
        case 0:
370
            /* access granted */
371
            /* XXX: we should go on looping to check all TLBs consistency
372
             *      but we can speed-up the whole thing as the
373
             *      result would be undefined if TLBs are not consistent.
374
             */
375
            ret = 0;
376
            best = nr;
377
            goto done;
378
        }
379
    }
380
    if (best != -1) {
381
    done:
382
#if defined (DEBUG_SOFTWARE_TLB)
383
        if (loglevel != 0) {
384
            fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
385
                    ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
386
        }
387
#endif
388
        /* Update page flags */
389
        pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
390
    }
391

    
392
    return ret;
393
}
394

    
395
/* Perform BAT hit & translation */
396
static int get_bat (CPUState *env, mmu_ctx_t *ctx,
397
                    target_ulong virtual, int rw, int type)
398
{
399
    target_ulong *BATlt, *BATut, *BATu, *BATl;
400
    target_ulong base, BEPIl, BEPIu, bl;
401
    int i;
402
    int ret = -1;
403

    
404
#if defined (DEBUG_BATS)
405
    if (loglevel != 0) {
406
        fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
407
                type == ACCESS_CODE ? 'I' : 'D', virtual);
408
    }
409
#endif
410
    switch (type) {
411
    case ACCESS_CODE:
412
        BATlt = env->IBAT[1];
413
        BATut = env->IBAT[0];
414
        break;
415
    default:
416
        BATlt = env->DBAT[1];
417
        BATut = env->DBAT[0];
418
        break;
419
    }
420
#if defined (DEBUG_BATS)
421
    if (loglevel != 0) {
422
        fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
423
                type == ACCESS_CODE ? 'I' : 'D', virtual);
424
    }
425
#endif
426
    base = virtual & 0xFFFC0000;
427
    for (i = 0; i < 4; i++) {
428
        BATu = &BATut[i];
429
        BATl = &BATlt[i];
430
        BEPIu = *BATu & 0xF0000000;
431
        BEPIl = *BATu & 0x0FFE0000;
432
        bl = (*BATu & 0x00001FFC) << 15;
433
#if defined (DEBUG_BATS)
434
        if (loglevel != 0) {
435
            fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
436
                    " BATl 0x" ADDRX "\n",
437
                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
438
                    *BATu, *BATl);
439
        }
440
#endif
441
        if ((virtual & 0xF0000000) == BEPIu &&
442
            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
443
            /* BAT matches */
444
            if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
445
                (msr_pr == 1 && (*BATu & 0x00000001))) {
446
                /* Get physical address */
447
                ctx->raddr = (*BATl & 0xF0000000) |
448
                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
449
                    (virtual & 0x0001F000);
450
                if (*BATl & 0x00000001)
451
                    ctx->prot = PAGE_READ;
452
                if (*BATl & 0x00000002)
453
                    ctx->prot = PAGE_WRITE | PAGE_READ;
454
#if defined (DEBUG_BATS)
455
                if (loglevel != 0) {
456
                    fprintf(logfile, "BAT %d match: r 0x" PADDRX
457
                            " prot=%c%c\n",
458
                            i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
459
                            ctx->prot & PAGE_WRITE ? 'W' : '-');
460
                }
461
#endif
462
                ret = 0;
463
                break;
464
            }
465
        }
466
    }
467
    if (ret < 0) {
468
#if defined (DEBUG_BATS)
469
        if (loglevel != 0) {
470
            fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
471
            for (i = 0; i < 4; i++) {
472
                BATu = &BATut[i];
473
                BATl = &BATlt[i];
474
                BEPIu = *BATu & 0xF0000000;
475
                BEPIl = *BATu & 0x0FFE0000;
476
                bl = (*BATu & 0x00001FFC) << 15;
477
                fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
478
                        " BATl 0x" ADDRX " \n\t"
479
                        "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
480
                        __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
481
                        *BATu, *BATl, BEPIu, BEPIl, bl);
482
            }
483
        }
484
#endif
485
    }
486
    /* No hit */
487
    return ret;
488
}
489

    
490
/* PTE table lookup */
491
static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
492
{
493
    target_ulong base, pte0, pte1;
494
    int i, good = -1;
495
    int ret, r;
496

    
497
    ret = -1; /* No entry found */
498
    base = ctx->pg_addr[h];
499
    for (i = 0; i < 8; i++) {
500
#if defined(TARGET_PPC64)
501
        if (is_64b) {
502
            pte0 = ldq_phys(base + (i * 16));
503
            pte1 =  ldq_phys(base + (i * 16) + 8);
504
            r = pte64_check(ctx, pte0, pte1, h, rw);
505
#if defined (DEBUG_MMU)
506
            if (loglevel != 0) {
507
                fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
508
                        " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
509
                        base + (i * 16), pte0, pte1,
510
                        (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
511
                        ctx->ptem);
512
            }
513
#endif
514
        } else
515
#endif
516
        {
517
            pte0 = ldl_phys(base + (i * 8));
518
            pte1 =  ldl_phys(base + (i * 8) + 4);
519
            r = pte32_check(ctx, pte0, pte1, h, rw);
520
#if defined (DEBUG_MMU)
521
            if (loglevel != 0) {
522
                fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
523
                        " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
524
                        base + (i * 8), pte0, pte1,
525
                        (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
526
                        ctx->ptem);
527
            }
528
#endif
529
        }
530
        switch (r) {
531
        case -3:
532
            /* PTE inconsistency */
533
            return -1;
534
        case -2:
535
            /* Access violation */
536
            ret = -2;
537
            good = i;
538
            break;
539
        case -1:
540
        default:
541
            /* No PTE match */
542
            break;
543
        case 0:
544
            /* access granted */
545
            /* XXX: we should go on looping to check all PTEs consistency
546
             *      but if we can speed-up the whole thing as the
547
             *      result would be undefined if PTEs are not consistent.
548
             */
549
            ret = 0;
550
            good = i;
551
            goto done;
552
        }
553
    }
554
    if (good != -1) {
555
    done:
556
#if defined (DEBUG_MMU)
557
        if (loglevel != 0) {
558
            fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
559
                    "ret=%d\n",
560
                    ctx->raddr, ctx->prot, ret);
561
        }
562
#endif
563
        /* Update page flags */
564
        pte1 = ctx->raddr;
565
        if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
566
#if defined(TARGET_PPC64)
567
            if (is_64b) {
568
                stq_phys_notdirty(base + (good * 16) + 8, pte1);
569
            } else
570
#endif
571
            {
572
                stl_phys_notdirty(base + (good * 8) + 4, pte1);
573
            }
574
        }
575
    }
576

    
577
    return ret;
578
}
579

    
580
static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
581
{
582
    return _find_pte(ctx, 0, h, rw);
583
}
584

    
585
#if defined(TARGET_PPC64)
586
static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
587
{
588
    return _find_pte(ctx, 1, h, rw);
589
}
590
#endif
591

    
592
static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
593
                                   int h, int rw)
594
{
595
#if defined(TARGET_PPC64)
596
    if (env->mmu_model == POWERPC_MMU_64B)
597
        return find_pte64(ctx, h, rw);
598
#endif
599

    
600
    return find_pte32(ctx, h, rw);
601
}
602

    
603
#if defined(TARGET_PPC64)
604
static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
605
                       target_ulong *vsid, target_ulong *page_mask, int *attr)
606
{
607
    target_phys_addr_t sr_base;
608
    target_ulong mask;
609
    uint64_t tmp64;
610
    uint32_t tmp;
611
    int n, ret;
612
    int slb_nr;
613

    
614
    ret = -5;
615
    sr_base = env->spr[SPR_ASR];
616
#if defined(DEBUG_SLB)
617
    if (loglevel != 0) {
618
        fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
619
                __func__, eaddr, sr_base);
620
    }
621
#endif
622
    mask = 0x0000000000000000ULL; /* Avoid gcc warning */
623
    slb_nr = env->slb_nr;
624
    for (n = 0; n < slb_nr; n++) {
625
        tmp64 = ldq_phys(sr_base);
626
        tmp = ldl_phys(sr_base + 8);
627
#if defined(DEBUG_SLB)
628
        if (loglevel != 0) {
629
        fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08" PRIx32 "\n",
630
                __func__, n, sr_base, tmp64, tmp);
631
        }
632
#endif
633
        if (tmp64 & 0x0000000008000000ULL) {
634
            /* SLB entry is valid */
635
            switch (tmp64 & 0x0000000006000000ULL) {
636
            case 0x0000000000000000ULL:
637
                /* 256 MB segment */
638
                mask = 0xFFFFFFFFF0000000ULL;
639
                break;
640
            case 0x0000000002000000ULL:
641
                /* 1 TB segment */
642
                mask = 0xFFFF000000000000ULL;
643
                break;
644
            case 0x0000000004000000ULL:
645
            case 0x0000000006000000ULL:
646
                /* Reserved => segment is invalid */
647
                continue;
648
            }
649
            if ((eaddr & mask) == (tmp64 & mask)) {
650
                /* SLB match */
651
                *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
652
                *page_mask = ~mask;
653
                *attr = tmp & 0xFF;
654
                ret = 0;
655
                break;
656
            }
657
        }
658
        sr_base += 12;
659
    }
660

    
661
    return ret;
662
}
663

    
664
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
665
{
666
    target_phys_addr_t sr_base;
667
    target_ulong rt;
668
    uint64_t tmp64;
669
    uint32_t tmp;
670

    
671
    sr_base = env->spr[SPR_ASR];
672
    sr_base += 12 * slb_nr;
673
    tmp64 = ldq_phys(sr_base);
674
    tmp = ldl_phys(sr_base + 8);
675
    if (tmp64 & 0x0000000008000000ULL) {
676
        /* SLB entry is valid */
677
        /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
678
        rt = tmp >> 8;             /* 65:88 => 40:63 */
679
        rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
680
        /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
681
        rt |= ((tmp >> 4) & 0xF) << 27;
682
    } else {
683
        rt = 0;
684
    }
685
#if defined(DEBUG_SLB)
686
    if (loglevel != 0) {
687
        fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
688
                ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
689
    }
690
#endif
691

    
692
    return rt;
693
}
694

    
695
void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
696
{
697
    target_phys_addr_t sr_base;
698
    uint64_t tmp64;
699
    uint32_t tmp;
700

    
701
    sr_base = env->spr[SPR_ASR];
702
    sr_base += 12 * slb_nr;
703
    /* Copy Rs bits 37:63 to SLB 62:88 */
704
    tmp = rs << 8;
705
    tmp64 = (rs >> 24) & 0x7;
706
    /* Copy Rs bits 33:36 to SLB 89:92 */
707
    tmp |= ((rs >> 27) & 0xF) << 4;
708
    /* Set the valid bit */
709
    tmp64 |= 1 << 27;
710
    /* Set ESID */
711
    tmp64 |= (uint32_t)slb_nr << 28;
712
#if defined(DEBUG_SLB)
713
    if (loglevel != 0) {
714
        fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08"
715
                PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);
716
    }
717
#endif
718
    /* Write SLB entry to memory */
719
    stq_phys(sr_base, tmp64);
720
    stl_phys(sr_base + 8, tmp);
721
}
722
#endif /* defined(TARGET_PPC64) */
723

    
724
/* Perform segment based translation */
725
static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
726
                                                    int sdr_sh,
727
                                                    target_phys_addr_t hash,
728
                                                    target_phys_addr_t mask)
729
{
730
    return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
731
}
732

    
733
static int get_segment (CPUState *env, mmu_ctx_t *ctx,
734
                        target_ulong eaddr, int rw, int type)
735
{
736
    target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
737
    target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
738
#if defined(TARGET_PPC64)
739
    int attr;
740
#endif
741
    int ds, nx, vsid_sh, sdr_sh;
742
    int ret, ret2;
743

    
744
#if defined(TARGET_PPC64)
745
    if (env->mmu_model == POWERPC_MMU_64B) {
746
#if defined (DEBUG_MMU)
747
        if (loglevel != 0) {
748
            fprintf(logfile, "Check SLBs\n");
749
        }
750
#endif
751
        ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
752
        if (ret < 0)
753
            return ret;
754
        ctx->key = ((attr & 0x40) && msr_pr == 1) ||
755
            ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
756
        ds = 0;
757
        nx = attr & 0x20 ? 1 : 0;
758
        vsid_mask = 0x00003FFFFFFFFF80ULL;
759
        vsid_sh = 7;
760
        sdr_sh = 18;
761
        sdr_mask = 0x3FF80;
762
    } else
763
#endif /* defined(TARGET_PPC64) */
764
    {
765
        sr = env->sr[eaddr >> 28];
766
        page_mask = 0x0FFFFFFF;
767
        ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
768
                    ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
769
        ds = sr & 0x80000000 ? 1 : 0;
770
        nx = sr & 0x10000000 ? 1 : 0;
771
        vsid = sr & 0x00FFFFFF;
772
        vsid_mask = 0x01FFFFC0;
773
        vsid_sh = 6;
774
        sdr_sh = 16;
775
        sdr_mask = 0xFFC0;
776
#if defined (DEBUG_MMU)
777
        if (loglevel != 0) {
778
            fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
779
                    " nip=0x" ADDRX " lr=0x" ADDRX
780
                    " ir=%d dr=%d pr=%d %d t=%d\n",
781
                    eaddr, (int)(eaddr >> 28), sr, env->nip,
782
                    env->lr, msr_ir, msr_dr, msr_pr, rw, type);
783
        }
784
#endif
785
    }
786
#if defined (DEBUG_MMU)
787
    if (loglevel != 0) {
788
        fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
789
                ctx->key, ds, nx, vsid);
790
    }
791
#endif
792
    ret = -1;
793
    if (!ds) {
794
        /* Check if instruction fetch is allowed, if needed */
795
        if (type != ACCESS_CODE || nx == 0) {
796
            /* Page address translation */
797
            /* Primary table address */
798
            sdr = env->sdr1;
799
            pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
800
#if defined(TARGET_PPC64)
801
            if (env->mmu_model == POWERPC_MMU_64B) {
802
                htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
803
                /* XXX: this is false for 1 TB segments */
804
                hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
805
            } else
806
#endif
807
            {
808
                htab_mask = sdr & 0x000001FF;
809
                hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
810
            }
811
            mask = (htab_mask << sdr_sh) | sdr_mask;
812
#if defined (DEBUG_MMU)
813
            if (loglevel != 0) {
814
                fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
815
                        PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask,
816
                        page_mask);
817
            }
818
#endif
819
            ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
820
            /* Secondary table address */
821
            hash = (~hash) & vsid_mask;
822
#if defined (DEBUG_MMU)
823
            if (loglevel != 0) {
824
                fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
825
                        PADDRX "\n", sdr, sdr_sh, hash, mask);
826
            }
827
#endif
828
            ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
829
#if defined(TARGET_PPC64)
830
            if (env->mmu_model == POWERPC_MMU_64B) {
831
                /* Only 5 bits of the page index are used in the AVPN */
832
                ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
833
            } else
834
#endif
835
            {
836
                ctx->ptem = (vsid << 7) | (pgidx >> 10);
837
            }
838
            /* Initialize real address with an invalid value */
839
            ctx->raddr = (target_ulong)-1;
840
            if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
841
                         env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
842
                /* Software TLB search */
843
                ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
844
            } else {
845
#if defined (DEBUG_MMU)
846
                if (loglevel != 0) {
847
                    fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
848
                            "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
849
                            sdr, (uint32_t)vsid, (uint32_t)pgidx,
850
                            (uint32_t)hash, ctx->pg_addr[0]);
851
                }
852
#endif
853
                /* Primary table lookup */
854
                ret = find_pte(env, ctx, 0, rw);
855
                if (ret < 0) {
856
                    /* Secondary table lookup */
857
#if defined (DEBUG_MMU)
858
                    if (eaddr != 0xEFFFFFFF && loglevel != 0) {
859
                        fprintf(logfile,
860
                                "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
861
                                "hash=0x%05x pg_addr=0x" PADDRX "\n",
862
                                sdr, (uint32_t)vsid, (uint32_t)pgidx,
863
                                (uint32_t)hash, ctx->pg_addr[1]);
864
                    }
865
#endif
866
                    ret2 = find_pte(env, ctx, 1, rw);
867
                    if (ret2 != -1)
868
                        ret = ret2;
869
                }
870
            }
871
#if defined (DEBUG_MMU)
872
                    if (loglevel != 0) {
873
                        target_phys_addr_t curaddr;
874
                        uint32_t a0, a1, a2, a3;
875
                        fprintf(logfile,
876
                                "Page table: " PADDRX " len " PADDRX "\n",
877
                                sdr, mask + 0x80);
878
                        for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
879
                             curaddr += 16) {
880
                            a0 = ldl_phys(curaddr);
881
                            a1 = ldl_phys(curaddr + 4);
882
                            a2 = ldl_phys(curaddr + 8);
883
                            a3 = ldl_phys(curaddr + 12);
884
                            if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
885
                                fprintf(logfile,
886
                                        PADDRX ": %08x %08x %08x %08x\n",
887
                                        curaddr, a0, a1, a2, a3);
888
                            }
889
                        }
890
                    }
891
#endif
892
        } else {
893
#if defined (DEBUG_MMU)
894
            if (loglevel != 0)
895
                fprintf(logfile, "No access allowed\n");
896
#endif
897
            ret = -3;
898
        }
899
    } else {
900
#if defined (DEBUG_MMU)
901
        if (loglevel != 0)
902
            fprintf(logfile, "direct store...\n");
903
#endif
904
        /* Direct-store segment : absolutely *BUGGY* for now */
905
        switch (type) {
906
        case ACCESS_INT:
907
            /* Integer load/store : only access allowed */
908
            break;
909
        case ACCESS_CODE:
910
            /* No code fetch is allowed in direct-store areas */
911
            return -4;
912
        case ACCESS_FLOAT:
913
            /* Floating point load/store */
914
            return -4;
915
        case ACCESS_RES:
916
            /* lwarx, ldarx or srwcx. */
917
            return -4;
918
        case ACCESS_CACHE:
919
            /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
920
            /* Should make the instruction do no-op.
921
             * As it already do no-op, it's quite easy :-)
922
             */
923
            ctx->raddr = eaddr;
924
            return 0;
925
        case ACCESS_EXT:
926
            /* eciwx or ecowx */
927
            return -4;
928
        default:
929
            if (logfile) {
930
                fprintf(logfile, "ERROR: instruction should not need "
931
                        "address translation\n");
932
            }
933
            return -4;
934
        }
935
        if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
936
            ctx->raddr = eaddr;
937
            ret = 2;
938
        } else {
939
            ret = -2;
940
        }
941
    }
942

    
943
    return ret;
944
}
945

    
946
/* Generic TLB check function for embedded PowerPC implementations */
947
static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
948
                             target_phys_addr_t *raddrp,
949
                             target_ulong address,
950
                             uint32_t pid, int ext, int i)
951
{
952
    target_ulong mask;
953

    
954
    /* Check valid flag */
955
    if (!(tlb->prot & PAGE_VALID)) {
956
        if (loglevel != 0)
957
            fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
958
        return -1;
959
    }
960
    mask = ~(tlb->size - 1);
961
#if defined (DEBUG_SOFTWARE_TLB)
962
    if (loglevel != 0) {
963
        fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
964
                ADDRX " " ADDRX " %d\n",
965
                __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
966
    }
967
#endif
968
    /* Check PID */
969
    if (tlb->PID != 0 && tlb->PID != pid)
970
        return -1;
971
    /* Check effective address */
972
    if ((address & mask) != tlb->EPN)
973
        return -1;
974
    *raddrp = (tlb->RPN & mask) | (address & ~mask);
975
#if (TARGET_PHYS_ADDR_BITS >= 36)
976
    if (ext) {
977
        /* Extend the physical address to 36 bits */
978
        *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
979
    }
980
#endif
981

    
982
    return 0;
983
}
984

    
985
/* Generic TLB search function for PowerPC embedded implementations */
986
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
987
{
988
    ppcemb_tlb_t *tlb;
989
    target_phys_addr_t raddr;
990
    int i, ret;
991

    
992
    /* Default return value is no match */
993
    ret = -1;
994
    for (i = 0; i < env->nb_tlb; i++) {
995
        tlb = &env->tlb[i].tlbe;
996
        if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
997
            ret = i;
998
            break;
999
        }
1000
    }
1001

    
1002
    return ret;
1003
}
1004

    
1005
/* Helpers specific to PowerPC 40x implementations */
1006
static void ppc4xx_tlb_invalidate_all (CPUState *env)
1007
{
1008
    ppcemb_tlb_t *tlb;
1009
    int i;
1010

    
1011
    for (i = 0; i < env->nb_tlb; i++) {
1012
        tlb = &env->tlb[i].tlbe;
1013
        tlb->prot &= ~PAGE_VALID;
1014
    }
1015
    tlb_flush(env, 1);
1016
}
1017

    
1018
static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
1019
                                        uint32_t pid)
1020
{
1021
#if !defined(FLUSH_ALL_TLBS)
1022
    ppcemb_tlb_t *tlb;
1023
    target_phys_addr_t raddr;
1024
    target_ulong page, end;
1025
    int i;
1026

    
1027
    for (i = 0; i < env->nb_tlb; i++) {
1028
        tlb = &env->tlb[i].tlbe;
1029
        if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1030
            end = tlb->EPN + tlb->size;
1031
            for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1032
                tlb_flush_page(env, page);
1033
            tlb->prot &= ~PAGE_VALID;
1034
            break;
1035
        }
1036
    }
1037
#else
1038
    ppc4xx_tlb_invalidate_all(env);
1039
#endif
1040
}
1041

    
1042
int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1043
                                 target_ulong address, int rw, int access_type)
1044
{
1045
    ppcemb_tlb_t *tlb;
1046
    target_phys_addr_t raddr;
1047
    int i, ret, zsel, zpr;
1048

    
1049
    ret = -1;
1050
    raddr = -1;
1051
    for (i = 0; i < env->nb_tlb; i++) {
1052
        tlb = &env->tlb[i].tlbe;
1053
        if (ppcemb_tlb_check(env, tlb, &raddr, address,
1054
                             env->spr[SPR_40x_PID], 0, i) < 0)
1055
            continue;
1056
        zsel = (tlb->attr >> 4) & 0xF;
1057
        zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
1058
#if defined (DEBUG_SOFTWARE_TLB)
1059
        if (loglevel != 0) {
1060
            fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1061
                    __func__, i, zsel, zpr, rw, tlb->attr);
1062
        }
1063
#endif
1064
        if (access_type == ACCESS_CODE) {
1065
            /* Check execute enable bit */
1066
            switch (zpr) {
1067
            case 0x2:
1068
                if (msr_pr)
1069
                    goto check_exec_perm;
1070
                goto exec_granted;
1071
            case 0x0:
1072
                if (msr_pr) {
1073
                    ctx->prot = 0;
1074
                    ret = -3;
1075
                    break;
1076
                }
1077
                /* No break here */
1078
            case 0x1:
1079
            check_exec_perm:
1080
                /* Check from TLB entry */
1081
                if (!(tlb->prot & PAGE_EXEC)) {
1082
                    ret = -3;
1083
                } else {
1084
                    if (tlb->prot & PAGE_WRITE) {
1085
                        ctx->prot = PAGE_READ | PAGE_WRITE;
1086
                    } else {
1087
                        ctx->prot = PAGE_READ;
1088
                    }
1089
                    ret = 0;
1090
                }
1091
                break;
1092
            case 0x3:
1093
            exec_granted:
1094
                /* All accesses granted */
1095
                ctx->prot = PAGE_READ | PAGE_WRITE;
1096
                ret = 0;
1097
                break;
1098
            }
1099
        } else {
1100
            switch (zpr) {
1101
            case 0x2:
1102
                if (msr_pr)
1103
                    goto check_rw_perm;
1104
                goto rw_granted;
1105
            case 0x0:
1106
                if (msr_pr) {
1107
                    ctx->prot = 0;
1108
                    ret = -2;
1109
                    break;
1110
                }
1111
                /* No break here */
1112
            case 0x1:
1113
            check_rw_perm:
1114
                /* Check from TLB entry */
1115
                /* Check write protection bit */
1116
                if (tlb->prot & PAGE_WRITE) {
1117
                    ctx->prot = PAGE_READ | PAGE_WRITE;
1118
                    ret = 0;
1119
                } else {
1120
                    ctx->prot = PAGE_READ;
1121
                    if (rw)
1122
                        ret = -2;
1123
                    else
1124
                        ret = 0;
1125
                }
1126
                break;
1127
            case 0x3:
1128
            rw_granted:
1129
                /* All accesses granted */
1130
                ctx->prot = PAGE_READ | PAGE_WRITE;
1131
                ret = 0;
1132
                break;
1133
            }
1134
        }
1135
        if (ret >= 0) {
1136
            ctx->raddr = raddr;
1137
#if defined (DEBUG_SOFTWARE_TLB)
1138
            if (loglevel != 0) {
1139
                fprintf(logfile, "%s: access granted " ADDRX " => " REGX
1140
                        " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1141
                        ret);
1142
            }
1143
#endif
1144
            return 0;
1145
        }
1146
    }
1147
#if defined (DEBUG_SOFTWARE_TLB)
1148
    if (loglevel != 0) {
1149
        fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1150
                " %d %d\n", __func__, address, raddr, ctx->prot,
1151
                ret);
1152
    }
1153
#endif
1154

    
1155
    return ret;
1156
}
1157

    
1158
void store_40x_sler (CPUPPCState *env, uint32_t val)
1159
{
1160
    /* XXX: TO BE FIXED */
1161
    if (val != 0x00000000) {
1162
        cpu_abort(env, "Little-endian regions are not supported by now\n");
1163
    }
1164
    env->spr[SPR_405_SLER] = val;
1165
}
1166

    
1167
int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1168
                                   target_ulong address, int rw,
1169
                                   int access_type)
1170
{
1171
    ppcemb_tlb_t *tlb;
1172
    target_phys_addr_t raddr;
1173
    int i, prot, ret;
1174

    
1175
    ret = -1;
1176
    raddr = -1;
1177
    for (i = 0; i < env->nb_tlb; i++) {
1178
        tlb = &env->tlb[i].tlbe;
1179
        if (ppcemb_tlb_check(env, tlb, &raddr, address,
1180
                             env->spr[SPR_BOOKE_PID], 1, i) < 0)
1181
            continue;
1182
        if (msr_pr)
1183
            prot = tlb->prot & 0xF;
1184
        else
1185
            prot = (tlb->prot >> 4) & 0xF;
1186
        /* Check the address space */
1187
        if (access_type == ACCESS_CODE) {
1188
            if (msr_ir != (tlb->attr & 1))
1189
                continue;
1190
            ctx->prot = prot;
1191
            if (prot & PAGE_EXEC) {
1192
                ret = 0;
1193
                break;
1194
            }
1195
            ret = -3;
1196
        } else {
1197
            if (msr_dr != (tlb->attr & 1))
1198
                continue;
1199
            ctx->prot = prot;
1200
            if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1201
                ret = 0;
1202
                break;
1203
            }
1204
            ret = -2;
1205
        }
1206
    }
1207
    if (ret >= 0)
1208
        ctx->raddr = raddr;
1209

    
1210
    return ret;
1211
}
1212

    
1213
static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1214
                           target_ulong eaddr, int rw)
1215
{
1216
    int in_plb, ret;
1217

    
1218
    ctx->raddr = eaddr;
1219
    ctx->prot = PAGE_READ;
1220
    ret = 0;
1221
    switch (env->mmu_model) {
1222
    case POWERPC_MMU_32B:
1223
    case POWERPC_MMU_SOFT_6xx:
1224
    case POWERPC_MMU_SOFT_74xx:
1225
    case POWERPC_MMU_601:
1226
    case POWERPC_MMU_SOFT_4xx:
1227
    case POWERPC_MMU_REAL_4xx:
1228
    case POWERPC_MMU_BOOKE:
1229
        ctx->prot |= PAGE_WRITE;
1230
        break;
1231
#if defined(TARGET_PPC64)
1232
    case POWERPC_MMU_64B:
1233
        /* Real address are 60 bits long */
1234
        ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1235
        ctx->prot |= PAGE_WRITE;
1236
        break;
1237
#endif
1238
    case POWERPC_MMU_SOFT_4xx_Z:
1239
        if (unlikely(msr_pe != 0)) {
1240
            /* 403 family add some particular protections,
1241
             * using PBL/PBU registers for accesses with no translation.
1242
             */
1243
            in_plb =
1244
                /* Check PLB validity */
1245
                (env->pb[0] < env->pb[1] &&
1246
                 /* and address in plb area */
1247
                 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1248
                (env->pb[2] < env->pb[3] &&
1249
                 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1250
            if (in_plb ^ msr_px) {
1251
                /* Access in protected area */
1252
                if (rw == 1) {
1253
                    /* Access is not allowed */
1254
                    ret = -2;
1255
                }
1256
            } else {
1257
                /* Read-write access is allowed */
1258
                ctx->prot |= PAGE_WRITE;
1259
            }
1260
        }
1261
        break;
1262
    case POWERPC_MMU_BOOKE_FSL:
1263
        /* XXX: TODO */
1264
        cpu_abort(env, "BookE FSL MMU model not implemented\n");
1265
        break;
1266
    default:
1267
        cpu_abort(env, "Unknown or invalid MMU model\n");
1268
        return -1;
1269
    }
1270

    
1271
    return ret;
1272
}
1273

    
1274
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1275
                          int rw, int access_type, int check_BATs)
1276
{
1277
    int ret;
1278
#if 0
1279
    if (loglevel != 0) {
1280
        fprintf(logfile, "%s\n", __func__);
1281
    }
1282
#endif
1283
    if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1284
        (access_type != ACCESS_CODE && msr_dr == 0)) {
1285
        /* No address translation */
1286
        ret = check_physical(env, ctx, eaddr, rw);
1287
    } else {
1288
        ret = -1;
1289
        switch (env->mmu_model) {
1290
        case POWERPC_MMU_32B:
1291
        case POWERPC_MMU_SOFT_6xx:
1292
        case POWERPC_MMU_SOFT_74xx:
1293
            /* Try to find a BAT */
1294
            if (check_BATs)
1295
                ret = get_bat(env, ctx, eaddr, rw, access_type);
1296
            /* No break here */
1297
#if defined(TARGET_PPC64)
1298
        case POWERPC_MMU_64B:
1299
#endif
1300
            if (ret < 0) {
1301
                /* We didn't match any BAT entry or don't have BATs */
1302
                ret = get_segment(env, ctx, eaddr, rw, access_type);
1303
            }
1304
            break;
1305
        case POWERPC_MMU_SOFT_4xx:
1306
        case POWERPC_MMU_SOFT_4xx_Z:
1307
            ret = mmu40x_get_physical_address(env, ctx, eaddr,
1308
                                              rw, access_type);
1309
            break;
1310
        case POWERPC_MMU_601:
1311
            /* XXX: TODO */
1312
            cpu_abort(env, "601 MMU model not implemented\n");
1313
            return -1;
1314
        case POWERPC_MMU_BOOKE:
1315
            ret = mmubooke_get_physical_address(env, ctx, eaddr,
1316
                                                rw, access_type);
1317
            break;
1318
        case POWERPC_MMU_BOOKE_FSL:
1319
            /* XXX: TODO */
1320
            cpu_abort(env, "BookE FSL MMU model not implemented\n");
1321
            return -1;
1322
        case POWERPC_MMU_REAL_4xx:
1323
            cpu_abort(env, "PowerPC 401 does not do any translation\n");
1324
            return -1;
1325
        default:
1326
            cpu_abort(env, "Unknown or invalid MMU model\n");
1327
            return -1;
1328
        }
1329
    }
1330
#if 0
1331
    if (loglevel != 0) {
1332
        fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
1333
                __func__, eaddr, ret, ctx->raddr);
1334
    }
1335
#endif
1336

    
1337
    return ret;
1338
}
1339

    
1340
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1341
{
1342
    mmu_ctx_t ctx;
1343

    
1344
    if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
1345
        return -1;
1346

    
1347
    return ctx.raddr & TARGET_PAGE_MASK;
1348
}
1349

    
1350
/* Perform address translation */
1351
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1352
                              int is_user, int is_softmmu)
1353
{
1354
    mmu_ctx_t ctx;
1355
    int access_type;
1356
    int ret = 0;
1357

    
1358
    if (rw == 2) {
1359
        /* code access */
1360
        rw = 0;
1361
        access_type = ACCESS_CODE;
1362
    } else {
1363
        /* data access */
1364
        /* XXX: put correct access by using cpu_restore_state()
1365
           correctly */
1366
        access_type = ACCESS_INT;
1367
        //        access_type = env->access_type;
1368
    }
1369
    ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
1370
    if (ret == 0) {
1371
        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
1372
                           ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1373
                           is_user, is_softmmu);
1374
    } else if (ret < 0) {
1375
#if defined (DEBUG_MMU)
1376
        if (loglevel != 0)
1377
            cpu_dump_state(env, logfile, fprintf, 0);
1378
#endif
1379
        if (access_type == ACCESS_CODE) {
1380
            switch (ret) {
1381
            case -1:
1382
                /* No matches in page tables or TLB */
1383
                switch (env->mmu_model) {
1384
                case POWERPC_MMU_SOFT_6xx:
1385
                    env->exception_index = POWERPC_EXCP_IFTLB;
1386
                    env->error_code = 1 << 18;
1387
                    env->spr[SPR_IMISS] = address;
1388
                    env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1389
                    goto tlb_miss;
1390
                case POWERPC_MMU_SOFT_74xx:
1391
                    env->exception_index = POWERPC_EXCP_IFTLB;
1392
                    goto tlb_miss_74xx;
1393
                case POWERPC_MMU_SOFT_4xx:
1394
                case POWERPC_MMU_SOFT_4xx_Z:
1395
                    env->exception_index = POWERPC_EXCP_ITLB;
1396
                    env->error_code = 0;
1397
                    env->spr[SPR_40x_DEAR] = address;
1398
                    env->spr[SPR_40x_ESR] = 0x00000000;
1399
                    break;
1400
                case POWERPC_MMU_32B:
1401
#if defined(TARGET_PPC64)
1402
                case POWERPC_MMU_64B:
1403
#endif
1404
                    env->exception_index = POWERPC_EXCP_ISI;
1405
                    env->error_code = 0x40000000;
1406
                    break;
1407
                case POWERPC_MMU_601:
1408
                    /* XXX: TODO */
1409
                    cpu_abort(env, "MMU model not implemented\n");
1410
                    return -1;
1411
                case POWERPC_MMU_BOOKE:
1412
                    /* XXX: TODO */
1413
                    cpu_abort(env, "MMU model not implemented\n");
1414
                    return -1;
1415
                case POWERPC_MMU_BOOKE_FSL:
1416
                    /* XXX: TODO */
1417
                    cpu_abort(env, "MMU model not implemented\n");
1418
                    return -1;
1419
                case POWERPC_MMU_REAL_4xx:
1420
                    cpu_abort(env, "PowerPC 401 should never raise any MMU "
1421
                              "exceptions\n");
1422
                    return -1;
1423
                default:
1424
                    cpu_abort(env, "Unknown or invalid MMU model\n");
1425
                    return -1;
1426
                }
1427
                break;
1428
            case -2:
1429
                /* Access rights violation */
1430
                env->exception_index = POWERPC_EXCP_ISI;
1431
                env->error_code = 0x08000000;
1432
                break;
1433
            case -3:
1434
                /* No execute protection violation */
1435
                env->exception_index = POWERPC_EXCP_ISI;
1436
                env->error_code = 0x10000000;
1437
                break;
1438
            case -4:
1439
                /* Direct store exception */
1440
                /* No code fetch is allowed in direct-store areas */
1441
                env->exception_index = POWERPC_EXCP_ISI;
1442
                env->error_code = 0x10000000;
1443
                break;
1444
#if defined(TARGET_PPC64)
1445
            case -5:
1446
                /* No match in segment table */
1447
                env->exception_index = POWERPC_EXCP_ISEG;
1448
                env->error_code = 0;
1449
                break;
1450
#endif
1451
            }
1452
        } else {
1453
            switch (ret) {
1454
            case -1:
1455
                /* No matches in page tables or TLB */
1456
                switch (env->mmu_model) {
1457
                case POWERPC_MMU_SOFT_6xx:
1458
                    if (rw == 1) {
1459
                        env->exception_index = POWERPC_EXCP_DSTLB;
1460
                        env->error_code = 1 << 16;
1461
                    } else {
1462
                        env->exception_index = POWERPC_EXCP_DLTLB;
1463
                        env->error_code = 0;
1464
                    }
1465
                    env->spr[SPR_DMISS] = address;
1466
                    env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1467
                tlb_miss:
1468
                    env->error_code |= ctx.key << 19;
1469
                    env->spr[SPR_HASH1] = ctx.pg_addr[0];
1470
                    env->spr[SPR_HASH2] = ctx.pg_addr[1];
1471
                    break;
1472
                case POWERPC_MMU_SOFT_74xx:
1473
                    if (rw == 1) {
1474
                        env->exception_index = POWERPC_EXCP_DSTLB;
1475
                    } else {
1476
                        env->exception_index = POWERPC_EXCP_DLTLB;
1477
                    }
1478
                tlb_miss_74xx:
1479
                    /* Implement LRU algorithm */
1480
                    env->error_code = ctx.key << 19;
1481
                    env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1482
                        ((env->last_way + 1) & (env->nb_ways - 1));
1483
                    env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1484
                    break;
1485
                case POWERPC_MMU_SOFT_4xx:
1486
                case POWERPC_MMU_SOFT_4xx_Z:
1487
                    env->exception_index = POWERPC_EXCP_DTLB;
1488
                    env->error_code = 0;
1489
                    env->spr[SPR_40x_DEAR] = address;
1490
                    if (rw)
1491
                        env->spr[SPR_40x_ESR] = 0x00800000;
1492
                    else
1493
                        env->spr[SPR_40x_ESR] = 0x00000000;
1494
                    break;
1495
                case POWERPC_MMU_32B:
1496
#if defined(TARGET_PPC64)
1497
                case POWERPC_MMU_64B:
1498
#endif
1499
                    env->exception_index = POWERPC_EXCP_DSI;
1500
                    env->error_code = 0;
1501
                    env->spr[SPR_DAR] = address;
1502
                    if (rw == 1)
1503
                        env->spr[SPR_DSISR] = 0x42000000;
1504
                    else
1505
                        env->spr[SPR_DSISR] = 0x40000000;
1506
                    break;
1507
                case POWERPC_MMU_601:
1508
                    /* XXX: TODO */
1509
                    cpu_abort(env, "MMU model not implemented\n");
1510
                    return -1;
1511
                case POWERPC_MMU_BOOKE:
1512
                    /* XXX: TODO */
1513
                    cpu_abort(env, "MMU model not implemented\n");
1514
                    return -1;
1515
                case POWERPC_MMU_BOOKE_FSL:
1516
                    /* XXX: TODO */
1517
                    cpu_abort(env, "MMU model not implemented\n");
1518
                    return -1;
1519
                case POWERPC_MMU_REAL_4xx:
1520
                    cpu_abort(env, "PowerPC 401 should never raise any MMU "
1521
                              "exceptions\n");
1522
                    return -1;
1523
                default:
1524
                    cpu_abort(env, "Unknown or invalid MMU model\n");
1525
                    return -1;
1526
                }
1527
                break;
1528
            case -2:
1529
                /* Access rights violation */
1530
                env->exception_index = POWERPC_EXCP_DSI;
1531
                env->error_code = 0;
1532
                env->spr[SPR_DAR] = address;
1533
                if (rw == 1)
1534
                    env->spr[SPR_DSISR] = 0x0A000000;
1535
                else
1536
                    env->spr[SPR_DSISR] = 0x08000000;
1537
                break;
1538
            case -4:
1539
                /* Direct store exception */
1540
                switch (access_type) {
1541
                case ACCESS_FLOAT:
1542
                    /* Floating point load/store */
1543
                    env->exception_index = POWERPC_EXCP_ALIGN;
1544
                    env->error_code = POWERPC_EXCP_ALIGN_FP;
1545
                    env->spr[SPR_DAR] = address;
1546
                    break;
1547
                case ACCESS_RES:
1548
                    /* lwarx, ldarx or stwcx. */
1549
                    env->exception_index = POWERPC_EXCP_DSI;
1550
                    env->error_code = 0;
1551
                    env->spr[SPR_DAR] = address;
1552
                    if (rw == 1)
1553
                        env->spr[SPR_DSISR] = 0x06000000;
1554
                    else
1555
                        env->spr[SPR_DSISR] = 0x04000000;
1556
                    break;
1557
                case ACCESS_EXT:
1558
                    /* eciwx or ecowx */
1559
                    env->exception_index = POWERPC_EXCP_DSI;
1560
                    env->error_code = 0;
1561
                    env->spr[SPR_DAR] = address;
1562
                    if (rw == 1)
1563
                        env->spr[SPR_DSISR] = 0x06100000;
1564
                    else
1565
                        env->spr[SPR_DSISR] = 0x04100000;
1566
                    break;
1567
                default:
1568
                    printf("DSI: invalid exception (%d)\n", ret);
1569
                    env->exception_index = POWERPC_EXCP_PROGRAM;
1570
                    env->error_code =
1571
                        POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1572
                    env->spr[SPR_DAR] = address;
1573
                    break;
1574
                }
1575
                break;
1576
#if defined(TARGET_PPC64)
1577
            case -5:
1578
                /* No match in segment table */
1579
                env->exception_index = POWERPC_EXCP_DSEG;
1580
                env->error_code = 0;
1581
                env->spr[SPR_DAR] = address;
1582
                break;
1583
#endif
1584
            }
1585
        }
1586
#if 0
1587
        printf("%s: set exception to %d %02x\n", __func__,
1588
               env->exception, env->error_code);
1589
#endif
1590
        ret = 1;
1591
    }
1592

    
1593
    return ret;
1594
}
1595

    
1596
/*****************************************************************************/
1597
/* BATs management */
1598
#if !defined(FLUSH_ALL_TLBS)
1599
static always_inline void do_invalidate_BAT (CPUPPCState *env,
1600
                                             target_ulong BATu,
1601
                                             target_ulong mask)
1602
{
1603
    target_ulong base, end, page;
1604

    
1605
    base = BATu & ~0x0001FFFF;
1606
    end = base + mask + 0x00020000;
1607
#if defined (DEBUG_BATS)
1608
    if (loglevel != 0) {
1609
        fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1610
                base, end, mask);
1611
    }
1612
#endif
1613
    for (page = base; page != end; page += TARGET_PAGE_SIZE)
1614
        tlb_flush_page(env, page);
1615
#if defined (DEBUG_BATS)
1616
    if (loglevel != 0)
1617
        fprintf(logfile, "Flush done\n");
1618
#endif
1619
}
1620
#endif
1621

    
1622
static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1623
                                          int ul, int nr, target_ulong value)
1624
{
1625
#if defined (DEBUG_BATS)
1626
    if (loglevel != 0) {
1627
        fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1628
                ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1629
    }
1630
#endif
1631
}
1632

    
1633
target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1634
{
1635
    return env->IBAT[0][nr];
1636
}
1637

    
1638
target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1639
{
1640
    return env->IBAT[1][nr];
1641
}
1642

    
1643
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1644
{
1645
    target_ulong mask;
1646

    
1647
    dump_store_bat(env, 'I', 0, nr, value);
1648
    if (env->IBAT[0][nr] != value) {
1649
        mask = (value << 15) & 0x0FFE0000UL;
1650
#if !defined(FLUSH_ALL_TLBS)
1651
        do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1652
#endif
1653
        /* When storing valid upper BAT, mask BEPI and BRPN
1654
         * and invalidate all TLBs covered by this BAT
1655
         */
1656
        mask = (value << 15) & 0x0FFE0000UL;
1657
        env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1658
            (value & ~0x0001FFFFUL & ~mask);
1659
        env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1660
            (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1661
#if !defined(FLUSH_ALL_TLBS)
1662
        do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1663
#else
1664
        tlb_flush(env, 1);
1665
#endif
1666
    }
1667
}
1668

    
1669
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1670
{
1671
    dump_store_bat(env, 'I', 1, nr, value);
1672
    env->IBAT[1][nr] = value;
1673
}
1674

    
1675
target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1676
{
1677
    return env->DBAT[0][nr];
1678
}
1679

    
1680
target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1681
{
1682
    return env->DBAT[1][nr];
1683
}
1684

    
1685
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1686
{
1687
    target_ulong mask;
1688

    
1689
    dump_store_bat(env, 'D', 0, nr, value);
1690
    if (env->DBAT[0][nr] != value) {
1691
        /* When storing valid upper BAT, mask BEPI and BRPN
1692
         * and invalidate all TLBs covered by this BAT
1693
         */
1694
        mask = (value << 15) & 0x0FFE0000UL;
1695
#if !defined(FLUSH_ALL_TLBS)
1696
        do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1697
#endif
1698
        mask = (value << 15) & 0x0FFE0000UL;
1699
        env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1700
            (value & ~0x0001FFFFUL & ~mask);
1701
        env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1702
            (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1703
#if !defined(FLUSH_ALL_TLBS)
1704
        do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1705
#else
1706
        tlb_flush(env, 1);
1707
#endif
1708
    }
1709
}
1710

    
1711
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1712
{
1713
    dump_store_bat(env, 'D', 1, nr, value);
1714
    env->DBAT[1][nr] = value;
1715
}
1716

    
1717

    
1718
/*****************************************************************************/
1719
/* TLB management */
1720
void ppc_tlb_invalidate_all (CPUPPCState *env)
1721
{
1722
    switch (env->mmu_model) {
1723
    case POWERPC_MMU_SOFT_6xx:
1724
    case POWERPC_MMU_SOFT_74xx:
1725
        ppc6xx_tlb_invalidate_all(env);
1726
        break;
1727
    case POWERPC_MMU_SOFT_4xx:
1728
    case POWERPC_MMU_SOFT_4xx_Z:
1729
        ppc4xx_tlb_invalidate_all(env);
1730
        break;
1731
    case POWERPC_MMU_REAL_4xx:
1732
        cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1733
        break;
1734
    case POWERPC_MMU_BOOKE:
1735
        /* XXX: TODO */
1736
        cpu_abort(env, "MMU model not implemented\n");
1737
        break;
1738
    case POWERPC_MMU_BOOKE_FSL:
1739
        /* XXX: TODO */
1740
        cpu_abort(env, "MMU model not implemented\n");
1741
        break;
1742
    case POWERPC_MMU_601:
1743
        /* XXX: TODO */
1744
        cpu_abort(env, "MMU model not implemented\n");
1745
        break;
1746
    case POWERPC_MMU_32B:
1747
#if defined(TARGET_PPC64)
1748
    case POWERPC_MMU_64B:
1749
#endif /* defined(TARGET_PPC64) */
1750
        tlb_flush(env, 1);
1751
        break;
1752
    default:
1753
        /* XXX: TODO */
1754
        cpu_abort(env, "Unknown MMU model\n");
1755
        break;
1756
    }
1757
}
1758

    
1759
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1760
{
1761
#if !defined(FLUSH_ALL_TLBS)
1762
    addr &= TARGET_PAGE_MASK;
1763
    switch (env->mmu_model) {
1764
    case POWERPC_MMU_SOFT_6xx:
1765
    case POWERPC_MMU_SOFT_74xx:
1766
        ppc6xx_tlb_invalidate_virt(env, addr, 0);
1767
        if (env->id_tlbs == 1)
1768
            ppc6xx_tlb_invalidate_virt(env, addr, 1);
1769
        break;
1770
    case POWERPC_MMU_SOFT_4xx:
1771
    case POWERPC_MMU_SOFT_4xx_Z:
1772
        ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1773
        break;
1774
    case POWERPC_MMU_REAL_4xx:
1775
        cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1776
        break;
1777
    case POWERPC_MMU_BOOKE:
1778
        /* XXX: TODO */
1779
        cpu_abort(env, "MMU model not implemented\n");
1780
        break;
1781
    case POWERPC_MMU_BOOKE_FSL:
1782
        /* XXX: TODO */
1783
        cpu_abort(env, "MMU model not implemented\n");
1784
        break;
1785
    case POWERPC_MMU_601:
1786
        /* XXX: TODO */
1787
        cpu_abort(env, "MMU model not implemented\n");
1788
        break;
1789
    case POWERPC_MMU_32B:
1790
        /* tlbie invalidate TLBs for all segments */
1791
        addr &= ~((target_ulong)-1 << 28);
1792
        /* XXX: this case should be optimized,
1793
         * giving a mask to tlb_flush_page
1794
         */
1795
        tlb_flush_page(env, addr | (0x0 << 28));
1796
        tlb_flush_page(env, addr | (0x1 << 28));
1797
        tlb_flush_page(env, addr | (0x2 << 28));
1798
        tlb_flush_page(env, addr | (0x3 << 28));
1799
        tlb_flush_page(env, addr | (0x4 << 28));
1800
        tlb_flush_page(env, addr | (0x5 << 28));
1801
        tlb_flush_page(env, addr | (0x6 << 28));
1802
        tlb_flush_page(env, addr | (0x7 << 28));
1803
        tlb_flush_page(env, addr | (0x8 << 28));
1804
        tlb_flush_page(env, addr | (0x9 << 28));
1805
        tlb_flush_page(env, addr | (0xA << 28));
1806
        tlb_flush_page(env, addr | (0xB << 28));
1807
        tlb_flush_page(env, addr | (0xC << 28));
1808
        tlb_flush_page(env, addr | (0xD << 28));
1809
        tlb_flush_page(env, addr | (0xE << 28));
1810
        tlb_flush_page(env, addr | (0xF << 28));
1811
        break;
1812
#if defined(TARGET_PPC64)
1813
    case POWERPC_MMU_64B:
1814
        /* tlbie invalidate TLBs for all segments */
1815
        /* XXX: given the fact that there are too many segments to invalidate,
1816
         *      and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1817
         *      we just invalidate all TLBs
1818
         */
1819
        tlb_flush(env, 1);
1820
        break;
1821
#endif /* defined(TARGET_PPC64) */
1822
    default:
1823
        /* XXX: TODO */
1824
        cpu_abort(env, "Unknown MMU model\n");
1825
        break;
1826
    }
1827
#else
1828
    ppc_tlb_invalidate_all(env);
1829
#endif
1830
}
1831

    
1832
#if defined(TARGET_PPC64)
1833
void ppc_slb_invalidate_all (CPUPPCState *env)
1834
{
1835
    /* XXX: TODO */
1836
    tlb_flush(env, 1);
1837
}
1838

    
1839
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
1840
{
1841
    /* XXX: TODO */
1842
    tlb_flush(env, 1);
1843
}
1844
#endif
1845

    
1846

    
1847
/*****************************************************************************/
1848
/* Special registers manipulation */
1849
#if defined(TARGET_PPC64)
1850
target_ulong ppc_load_asr (CPUPPCState *env)
1851
{
1852
    return env->asr;
1853
}
1854

    
1855
void ppc_store_asr (CPUPPCState *env, target_ulong value)
1856
{
1857
    if (env->asr != value) {
1858
        env->asr = value;
1859
        tlb_flush(env, 1);
1860
    }
1861
}
1862
#endif
1863

    
1864
target_ulong do_load_sdr1 (CPUPPCState *env)
1865
{
1866
    return env->sdr1;
1867
}
1868

    
1869
void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1870
{
1871
#if defined (DEBUG_MMU)
1872
    if (loglevel != 0) {
1873
        fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
1874
    }
1875
#endif
1876
    if (env->sdr1 != value) {
1877
        /* XXX: for PowerPC 64, should check that the HTABSIZE value
1878
         *      is <= 28
1879
         */
1880
        env->sdr1 = value;
1881
        tlb_flush(env, 1);
1882
    }
1883
}
1884

    
1885
#if 0 // Unused
1886
target_ulong do_load_sr (CPUPPCState *env, int srnum)
1887
{
1888
    return env->sr[srnum];
1889
}
1890
#endif
1891

    
1892
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1893
{
1894
#if defined (DEBUG_MMU)
1895
    if (loglevel != 0) {
1896
        fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1897
                __func__, srnum, value, env->sr[srnum]);
1898
    }
1899
#endif
1900
    if (env->sr[srnum] != value) {
1901
        env->sr[srnum] = value;
1902
#if !defined(FLUSH_ALL_TLBS) && 0
1903
        {
1904
            target_ulong page, end;
1905
            /* Invalidate 256 MB of virtual memory */
1906
            page = (16 << 20) * srnum;
1907
            end = page + (16 << 20);
1908
            for (; page != end; page += TARGET_PAGE_SIZE)
1909
                tlb_flush_page(env, page);
1910
        }
1911
#else
1912
        tlb_flush(env, 1);
1913
#endif
1914
    }
1915
}
1916
#endif /* !defined (CONFIG_USER_ONLY) */
1917

    
1918
target_ulong ppc_load_xer (CPUPPCState *env)
1919
{
1920
    return (xer_so << XER_SO) |
1921
        (xer_ov << XER_OV) |
1922
        (xer_ca << XER_CA) |
1923
        (xer_bc << XER_BC) |
1924
        (xer_cmp << XER_CMP);
1925
}
1926

    
1927
void ppc_store_xer (CPUPPCState *env, target_ulong value)
1928
{
1929
    xer_so = (value >> XER_SO) & 0x01;
1930
    xer_ov = (value >> XER_OV) & 0x01;
1931
    xer_ca = (value >> XER_CA) & 0x01;
1932
    xer_cmp = (value >> XER_CMP) & 0xFF;
1933
    xer_bc = (value >> XER_BC) & 0x7F;
1934
}
1935

    
1936
/* Swap temporary saved registers with GPRs */
1937
static always_inline void swap_gpr_tgpr (CPUPPCState *env)
1938
{
1939
    ppc_gpr_t tmp;
1940

    
1941
    tmp = env->gpr[0];
1942
    env->gpr[0] = env->tgpr[0];
1943
    env->tgpr[0] = tmp;
1944
    tmp = env->gpr[1];
1945
    env->gpr[1] = env->tgpr[1];
1946
    env->tgpr[1] = tmp;
1947
    tmp = env->gpr[2];
1948
    env->gpr[2] = env->tgpr[2];
1949
    env->tgpr[2] = tmp;
1950
    tmp = env->gpr[3];
1951
    env->gpr[3] = env->tgpr[3];
1952
    env->tgpr[3] = tmp;
1953
}
1954

    
1955
/* GDBstub can read and write MSR... */
1956
target_ulong do_load_msr (CPUPPCState *env)
1957
{
1958
    return
1959
#if defined (TARGET_PPC64)
1960
        ((target_ulong)msr_sf   << MSR_SF)   |
1961
        ((target_ulong)msr_isf  << MSR_ISF)  |
1962
        ((target_ulong)msr_hv   << MSR_HV)   |
1963
#endif
1964
        ((target_ulong)msr_ucle << MSR_UCLE) |
1965
        ((target_ulong)msr_vr   << MSR_VR)   | /* VR / SPE */
1966
        ((target_ulong)msr_ap   << MSR_AP)   |
1967
        ((target_ulong)msr_sa   << MSR_SA)   |
1968
        ((target_ulong)msr_key  << MSR_KEY)  |
1969
        ((target_ulong)msr_pow  << MSR_POW)  | /* POW / WE */
1970
        ((target_ulong)msr_tgpr << MSR_TGPR) | /* TGPR / CE */
1971
        ((target_ulong)msr_ile  << MSR_ILE)  |
1972
        ((target_ulong)msr_ee   << MSR_EE)   |
1973
        ((target_ulong)msr_pr   << MSR_PR)   |
1974
        ((target_ulong)msr_fp   << MSR_FP)   |
1975
        ((target_ulong)msr_me   << MSR_ME)   |
1976
        ((target_ulong)msr_fe0  << MSR_FE0)  |
1977
        ((target_ulong)msr_se   << MSR_SE)   | /* SE / DWE / UBLE */
1978
        ((target_ulong)msr_be   << MSR_BE)   | /* BE / DE */
1979
        ((target_ulong)msr_fe1  << MSR_FE1)  |
1980
        ((target_ulong)msr_al   << MSR_AL)   |
1981
        ((target_ulong)msr_ip   << MSR_IP)   |
1982
        ((target_ulong)msr_ir   << MSR_IR)   | /* IR / IS */
1983
        ((target_ulong)msr_dr   << MSR_DR)   | /* DR / DS */
1984
        ((target_ulong)msr_pe   << MSR_PE)   | /* PE / EP */
1985
        ((target_ulong)msr_px   << MSR_PX)   | /* PX / PMM */
1986
        ((target_ulong)msr_ri   << MSR_RI)   |
1987
        ((target_ulong)msr_le   << MSR_LE);
1988
}
1989

    
1990
int do_store_msr (CPUPPCState *env, target_ulong value)
1991
{
1992
    int enter_pm;
1993

    
1994
    value &= env->msr_mask;
1995
    if (((value >> MSR_IR) & 1) != msr_ir ||
1996
        ((value >> MSR_DR) & 1) != msr_dr) {
1997
        /* Flush all tlb when changing translation mode */
1998
        tlb_flush(env, 1);
1999
        env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2000
    }
2001
#if 0
2002
    if (loglevel != 0) {
2003
        fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
2004
    }
2005
#endif
2006
    if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
2007
                 ((value >> MSR_TGPR) & 1) != msr_tgpr)) {
2008
        /* Swap temporary saved registers with GPRs */
2009
        swap_gpr_tgpr(env);
2010
    }
2011
#if defined (TARGET_PPC64)
2012
    msr_sf   = (value >> MSR_SF)   & 1;
2013
    msr_isf  = (value >> MSR_ISF)  & 1;
2014
    msr_hv   = (value >> MSR_HV)   & 1;
2015
#endif
2016
    msr_ucle = (value >> MSR_UCLE) & 1;
2017
    msr_vr   = (value >> MSR_VR)   & 1; /* VR / SPE */
2018
    msr_ap   = (value >> MSR_AP)   & 1;
2019
    msr_sa   = (value >> MSR_SA)   & 1;
2020
    msr_key  = (value >> MSR_KEY)  & 1;
2021
    msr_pow  = (value >> MSR_POW)  & 1; /* POW / WE */
2022
    msr_tgpr = (value >> MSR_TGPR) & 1; /* TGPR / CE */
2023
    msr_ile  = (value >> MSR_ILE)  & 1;
2024
    msr_ee   = (value >> MSR_EE)   & 1;
2025
    msr_pr   = (value >> MSR_PR)   & 1;
2026
    msr_fp   = (value >> MSR_FP)   & 1;
2027
    msr_me   = (value >> MSR_ME)   & 1;
2028
    msr_fe0  = (value >> MSR_FE0)  & 1;
2029
    msr_se   = (value >> MSR_SE)   & 1; /* SE / DWE / UBLE */
2030
    msr_be   = (value >> MSR_BE)   & 1; /* BE / DE */
2031
    msr_fe1  = (value >> MSR_FE1)  & 1;
2032
    msr_al   = (value >> MSR_AL)   & 1;
2033
    msr_ip   = (value >> MSR_IP)   & 1;
2034
    msr_ir   = (value >> MSR_IR)   & 1; /* IR / IS */
2035
    msr_dr   = (value >> MSR_DR)   & 1; /* DR / DS */
2036
    msr_pe   = (value >> MSR_PE)   & 1; /* PE / EP */
2037
    msr_px   = (value >> MSR_PX)   & 1; /* PX / PMM */
2038
    msr_ri   = (value >> MSR_RI)   & 1;
2039
    msr_le   = (value >> MSR_LE)   & 1;
2040
    do_compute_hflags(env);
2041

    
2042
    enter_pm = 0;
2043
    switch (env->excp_model) {
2044
    case POWERPC_EXCP_603:
2045
    case POWERPC_EXCP_603E:
2046
    case POWERPC_EXCP_G2:
2047
        /* Don't handle SLEEP mode: we should disable all clocks...
2048
         * No dynamic power-management.
2049
         */
2050
        if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
2051
            enter_pm = 1;
2052
        break;
2053
    case POWERPC_EXCP_604:
2054
        if (msr_pow == 1)
2055
            enter_pm = 1;
2056
        break;
2057
    case POWERPC_EXCP_7x0:
2058
        if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
2059
            enter_pm = 1;
2060
        break;
2061
    default:
2062
        break;
2063
    }
2064

    
2065
    return enter_pm;
2066
}
2067

    
2068
#if defined(TARGET_PPC64)
2069
int ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
2070
{
2071
    return do_store_msr(env, (do_load_msr(env) & ~0xFFFFFFFFULL) |
2072
                        (value & 0xFFFFFFFF));
2073
}
2074
#endif
2075

    
2076
void do_compute_hflags (CPUPPCState *env)
2077
{
2078
    /* Compute current hflags */
2079
    env->hflags = (msr_vr << MSR_VR) |
2080
        (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
2081
        (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
2082
        (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
2083
#if defined (TARGET_PPC64)
2084
    env->hflags |= msr_cm << MSR_CM;
2085
    env->hflags |= (uint64_t)msr_sf << MSR_SF;
2086
    env->hflags |= (uint64_t)msr_hv << MSR_HV;
2087
#endif
2088
}
2089

    
2090
/*****************************************************************************/
2091
/* Exception processing */
2092
#if defined (CONFIG_USER_ONLY)
2093
void do_interrupt (CPUState *env)
2094
{
2095
    env->exception_index = POWERPC_EXCP_NONE;
2096
    env->error_code = 0;
2097
}
2098

    
2099
void ppc_hw_interrupt (CPUState *env)
2100
{
2101
    env->exception_index = POWERPC_EXCP_NONE;
2102
    env->error_code = 0;
2103
}
2104
#else /* defined (CONFIG_USER_ONLY) */
2105
static void dump_syscall (CPUState *env)
2106
{
2107
    fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
2108
            " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
2109
            env->gpr[0], env->gpr[3], env->gpr[4],
2110
            env->gpr[5], env->gpr[6], env->nip);
2111
}
2112

    
2113
/* Note that this function should be greatly optimized
2114
 * when called with a constant excp, from ppc_hw_interrupt
2115
 */
2116
static always_inline void powerpc_excp (CPUState *env,
2117
                                        int excp_model, int excp)
2118
{
2119
    target_ulong msr, vector;
2120
    int srr0, srr1, asrr0, asrr1;
2121

    
2122
    if (loglevel & CPU_LOG_INT) {
2123
        fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
2124
                env->nip, excp, env->error_code);
2125
    }
2126
    msr = do_load_msr(env);
2127
    srr0 = SPR_SRR0;
2128
    srr1 = SPR_SRR1;
2129
    asrr0 = -1;
2130
    asrr1 = -1;
2131
    msr &= ~((target_ulong)0x783F0000);
2132
    switch (excp) {
2133
    case POWERPC_EXCP_NONE:
2134
        /* Should never happen */
2135
        return;
2136
    case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
2137
        msr_ri = 0; /* XXX: check this */
2138
        switch (excp_model) {
2139
        case POWERPC_EXCP_40x:
2140
            srr0 = SPR_40x_SRR2;
2141
            srr1 = SPR_40x_SRR3;
2142
            break;
2143
        case POWERPC_EXCP_BOOKE:
2144
            srr0 = SPR_BOOKE_CSRR0;
2145
            srr1 = SPR_BOOKE_CSRR1;
2146
            break;
2147
        case POWERPC_EXCP_G2:
2148
            break;
2149
        default:
2150
            goto excp_invalid;
2151
        }
2152
        goto store_next;
2153
    case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
2154
        if (msr_me == 0) {
2155
            /* Machine check exception is not enabled */
2156
            /* XXX: we may just stop the processor here, to allow debugging */
2157
            excp = POWERPC_EXCP_RESET;
2158
            goto excp_reset;
2159
        }
2160
        msr_ri = 0;
2161
        msr_me = 0;
2162
#if defined(TARGET_PPC64H)
2163
        msr_hv = 1;
2164
#endif
2165
        /* XXX: should also have something loaded in DAR / DSISR */
2166
        switch (excp_model) {
2167
        case POWERPC_EXCP_40x:
2168
            srr0 = SPR_40x_SRR2;
2169
            srr1 = SPR_40x_SRR3;
2170
            break;
2171
        case POWERPC_EXCP_BOOKE:
2172
            srr0 = SPR_BOOKE_MCSRR0;
2173
            srr1 = SPR_BOOKE_MCSRR1;
2174
            asrr0 = SPR_BOOKE_CSRR0;
2175
            asrr1 = SPR_BOOKE_CSRR1;
2176
            break;
2177
        default:
2178
            break;
2179
        }
2180
        goto store_next;
2181
    case POWERPC_EXCP_DSI:       /* Data storage exception                   */
2182
#if defined (DEBUG_EXCEPTIONS)
2183
        if (loglevel != 0) {
2184
            fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
2185
                    "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2186
        }
2187
#endif
2188
        msr_ri = 0;
2189
#if defined(TARGET_PPC64H)
2190
        if (lpes1 == 0)
2191
            msr_hv = 1;
2192
#endif
2193
        goto store_next;
2194
    case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
2195
#if defined (DEBUG_EXCEPTIONS)
2196
        if (loglevel != 0) {
2197
            fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
2198
                    "\n", msr, env->nip);
2199
        }
2200
#endif
2201
        msr_ri = 0;
2202
#if defined(TARGET_PPC64H)
2203
        if (lpes1 == 0)
2204
            msr_hv = 1;
2205
#endif
2206
        msr |= env->error_code;
2207
        goto store_next;
2208
    case POWERPC_EXCP_EXTERNAL:  /* External input                           */
2209
        msr_ri = 0;
2210
#if defined(TARGET_PPC64H)
2211
        if (lpes0 == 1)
2212
            msr_hv = 1;
2213
#endif
2214
        goto store_next;
2215
    case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
2216
        msr_ri = 0;
2217
#if defined(TARGET_PPC64H)
2218
        if (lpes1 == 0)
2219
            msr_hv = 1;
2220
#endif
2221
        /* XXX: this is false */
2222
        /* Get rS/rD and rA from faulting opcode */
2223
        env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2224
        goto store_current;
2225
    case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
2226
        switch (env->error_code & ~0xF) {
2227
        case POWERPC_EXCP_FP:
2228
            if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2229
#if defined (DEBUG_EXCEPTIONS)
2230
                if (loglevel != 0) {
2231
                    fprintf(logfile, "Ignore floating point exception\n");
2232
                }
2233
#endif
2234
                return;
2235
            }
2236
            msr_ri = 0;
2237
#if defined(TARGET_PPC64H)
2238
            if (lpes1 == 0)
2239
                msr_hv = 1;
2240
#endif
2241
            msr |= 0x00100000;
2242
            /* Set FX */
2243
            env->fpscr[7] |= 0x8;
2244
            /* Finally, update FEX */
2245
            if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
2246
                ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
2247
                env->fpscr[7] |= 0x4;
2248
            if (msr_fe0 != msr_fe1) {
2249
                msr |= 0x00010000;
2250
                goto store_current;
2251
            }
2252
            break;
2253
        case POWERPC_EXCP_INVAL:
2254
#if defined (DEBUG_EXCEPTIONS)
2255
            if (loglevel != 0) {
2256
                fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
2257
                        env->nip);
2258
            }
2259
#endif
2260
            msr_ri = 0;
2261
#if defined(TARGET_PPC64H)
2262
            if (lpes1 == 0)
2263
                msr_hv = 1;
2264
#endif
2265
            msr |= 0x00080000;
2266
            break;
2267
        case POWERPC_EXCP_PRIV:
2268
            msr_ri = 0;
2269
#if defined(TARGET_PPC64H)
2270
            if (lpes1 == 0)
2271
                msr_hv = 1;
2272
#endif
2273
            msr |= 0x00040000;
2274
            break;
2275
        case POWERPC_EXCP_TRAP:
2276
            msr_ri = 0;
2277
#if defined(TARGET_PPC64H)
2278
            if (lpes1 == 0)
2279
                msr_hv = 1;
2280
#endif
2281
            msr |= 0x00020000;
2282
            break;
2283
        default:
2284
            /* Should never occur */
2285
            cpu_abort(env, "Invalid program exception %d. Aborting\n",
2286
                      env->error_code);
2287
            break;
2288
        }
2289
        goto store_next;
2290
    case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
2291
        msr_ri = 0;
2292
#if defined(TARGET_PPC64H)
2293
        if (lpes1 == 0)
2294
            msr_hv = 1;
2295
#endif
2296
        goto store_current;
2297
    case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
2298
        /* NOTE: this is a temporary hack to support graphics OSI
2299
           calls from the MOL driver */
2300
        /* XXX: To be removed */
2301
        if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2302
            env->osi_call) {
2303
            if (env->osi_call(env) != 0)
2304
                return;
2305
        }
2306
        if (loglevel & CPU_LOG_INT) {
2307
            dump_syscall(env);
2308
        }
2309
        msr_ri = 0;
2310
#if defined(TARGET_PPC64H)
2311
        if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2312
            msr_hv = 1;
2313
#endif
2314
        goto store_next;
2315
    case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
2316
        msr_ri = 0;
2317
        goto store_current;
2318
    case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
2319
        msr_ri = 0;
2320
#if defined(TARGET_PPC64H)
2321
        if (lpes1 == 0)
2322
            msr_hv = 1;
2323
#endif
2324
        goto store_next;
2325
    case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
2326
        /* FIT on 4xx */
2327
#if defined (DEBUG_EXCEPTIONS)
2328
        if (loglevel != 0)
2329
            fprintf(logfile, "FIT exception\n");
2330
#endif
2331
        msr_ri = 0; /* XXX: check this */
2332
        goto store_next;
2333
    case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
2334
#if defined (DEBUG_EXCEPTIONS)
2335
        if (loglevel != 0)
2336
            fprintf(logfile, "WDT exception\n");
2337
#endif
2338
        switch (excp_model) {
2339
        case POWERPC_EXCP_BOOKE:
2340
            srr0 = SPR_BOOKE_CSRR0;
2341
            srr1 = SPR_BOOKE_CSRR1;
2342
            break;
2343
        default:
2344
            break;
2345
        }
2346
        msr_ri = 0; /* XXX: check this */
2347
        goto store_next;
2348
    case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
2349
        msr_ri = 0; /* XXX: check this */
2350
        goto store_next;
2351
    case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
2352
        msr_ri = 0; /* XXX: check this */
2353
        goto store_next;
2354
    case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
2355
        switch (excp_model) {
2356
        case POWERPC_EXCP_BOOKE:
2357
            srr0 = SPR_BOOKE_DSRR0;
2358
            srr1 = SPR_BOOKE_DSRR1;
2359
            asrr0 = SPR_BOOKE_CSRR0;
2360
            asrr1 = SPR_BOOKE_CSRR1;
2361
            break;
2362
        default:
2363
            break;
2364
        }
2365
        /* XXX: TODO */
2366
        cpu_abort(env, "Debug exception is not implemented yet !\n");
2367
        goto store_next;
2368
#if defined(TARGET_PPCEMB)
2369
    case POWERPC_EXCP_SPEU:      /* SPE/embedded floating-point unavailable  */
2370
        msr_ri = 0; /* XXX: check this */
2371
        goto store_current;
2372
    case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
2373
        /* XXX: TODO */
2374
        cpu_abort(env, "Embedded floating point data exception "
2375
                  "is not implemented yet !\n");
2376
        goto store_next;
2377
    case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
2378
        /* XXX: TODO */
2379
        cpu_abort(env, "Embedded floating point round exception "
2380
                  "is not implemented yet !\n");
2381
        goto store_next;
2382
    case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
2383
        msr_ri = 0;
2384
        /* XXX: TODO */
2385
        cpu_abort(env,
2386
                  "Performance counter exception is not implemented yet !\n");
2387
        goto store_next;
2388
    case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
2389
        /* XXX: TODO */
2390
        cpu_abort(env,
2391
                  "Embedded doorbell interrupt is not implemented yet !\n");
2392
        goto store_next;
2393
    case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
2394
        switch (excp_model) {
2395
        case POWERPC_EXCP_BOOKE:
2396
            srr0 = SPR_BOOKE_CSRR0;
2397
            srr1 = SPR_BOOKE_CSRR1;
2398
            break;
2399
        default:
2400
            break;
2401
        }
2402
        /* XXX: TODO */
2403
        cpu_abort(env, "Embedded doorbell critical interrupt "
2404
                  "is not implemented yet !\n");
2405
        goto store_next;
2406
#endif /* defined(TARGET_PPCEMB) */
2407
    case POWERPC_EXCP_RESET:     /* System reset exception                   */
2408
        msr_ri = 0;
2409
#if defined(TARGET_PPC64H)
2410
        msr_hv = 1;
2411
#endif
2412
    excp_reset:
2413
        goto store_next;
2414
#if defined(TARGET_PPC64)
2415
    case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
2416
        msr_ri = 0;
2417
#if defined(TARGET_PPC64H)
2418
        if (lpes1 == 0)
2419
            msr_hv = 1;
2420
#endif
2421
        goto store_next;
2422
    case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
2423
        msr_ri = 0;
2424
#if defined(TARGET_PPC64H)
2425
        if (lpes1 == 0)
2426
            msr_hv = 1;
2427
#endif
2428
        goto store_next;
2429
#endif /* defined(TARGET_PPC64) */
2430
#if defined(TARGET_PPC64H)
2431
    case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
2432
        srr0 = SPR_HSRR0;
2433
        srr1 = SPR_HSSR1;
2434
        msr_hv = 1;
2435
        goto store_next;
2436
#endif
2437
    case POWERPC_EXCP_TRACE:     /* Trace exception                          */
2438
        msr_ri = 0;
2439
#if defined(TARGET_PPC64H)
2440
        if (lpes1 == 0)
2441
            msr_hv = 1;
2442
#endif
2443
        goto store_next;
2444
#if defined(TARGET_PPC64H)
2445
    case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
2446
        srr0 = SPR_HSRR0;
2447
        srr1 = SPR_HSSR1;
2448
        msr_hv = 1;
2449
        goto store_next;
2450
    case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
2451
        srr0 = SPR_HSRR0;
2452
        srr1 = SPR_HSSR1;
2453
        msr_hv = 1;
2454
        /* XXX: TODO */
2455
        cpu_abort(env, "Hypervisor instruction storage exception "
2456
                  "is not implemented yet !\n");
2457
        goto store_next;
2458
    case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
2459
        srr0 = SPR_HSRR0;
2460
        srr1 = SPR_HSSR1;
2461
        msr_hv = 1;
2462
        goto store_next;
2463
    case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
2464
        srr0 = SPR_HSRR0;
2465
        srr1 = SPR_HSSR1;
2466
        msr_hv = 1;
2467
        goto store_next;
2468
#endif /* defined(TARGET_PPC64H) */
2469
    case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
2470
        msr_ri = 0;
2471
#if defined(TARGET_PPC64H)
2472
        if (lpes1 == 0)
2473
            msr_hv = 1;
2474
#endif
2475
        goto store_current;
2476
    case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
2477
#if defined (DEBUG_EXCEPTIONS)
2478
        if (loglevel != 0)
2479
            fprintf(logfile, "PIT exception\n");
2480
#endif
2481
        msr_ri = 0; /* XXX: check this */
2482
        goto store_next;
2483
    case POWERPC_EXCP_IO:        /* IO error exception                       */
2484
        /* XXX: TODO */
2485
        cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2486
        goto store_next;
2487
    case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
2488
        /* XXX: TODO */
2489
        cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2490
        goto store_next;
2491
    case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
2492
        /* XXX: TODO */
2493
        cpu_abort(env, "602 emulation trap exception "
2494
                  "is not implemented yet !\n");
2495
        goto store_next;
2496
    case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
2497
        msr_ri = 0; /* XXX: check this */
2498
#if defined(TARGET_PPC64H) /* XXX: check this */
2499
        if (lpes1 == 0)
2500
            msr_hv = 1;
2501
#endif
2502
        switch (excp_model) {
2503
        case POWERPC_EXCP_602:
2504
        case POWERPC_EXCP_603:
2505
        case POWERPC_EXCP_603E:
2506
        case POWERPC_EXCP_G2:
2507
            goto tlb_miss_tgpr;
2508
        case POWERPC_EXCP_7x5:
2509
            goto tlb_miss;
2510
        case POWERPC_EXCP_74xx:
2511
            goto tlb_miss_74xx;
2512
        default:
2513
            cpu_abort(env, "Invalid instruction TLB miss exception\n");
2514
            break;
2515
        }
2516
        break;
2517
    case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
2518
        msr_ri = 0; /* XXX: check this */
2519
#if defined(TARGET_PPC64H) /* XXX: check this */
2520
        if (lpes1 == 0)
2521
            msr_hv = 1;
2522
#endif
2523
        switch (excp_model) {
2524
        case POWERPC_EXCP_602:
2525
        case POWERPC_EXCP_603:
2526
        case POWERPC_EXCP_603E:
2527
        case POWERPC_EXCP_G2:
2528
            goto tlb_miss_tgpr;
2529
        case POWERPC_EXCP_7x5:
2530
            goto tlb_miss;
2531
        case POWERPC_EXCP_74xx:
2532
            goto tlb_miss_74xx;
2533
        default:
2534
            cpu_abort(env, "Invalid data load TLB miss exception\n");
2535
            break;
2536
        }
2537
        break;
2538
    case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
2539
        msr_ri = 0; /* XXX: check this */
2540
#if defined(TARGET_PPC64H) /* XXX: check this */
2541
        if (lpes1 == 0)
2542
            msr_hv = 1;
2543
#endif
2544
        switch (excp_model) {
2545
        case POWERPC_EXCP_602:
2546
        case POWERPC_EXCP_603:
2547
        case POWERPC_EXCP_603E:
2548
        case POWERPC_EXCP_G2:
2549
        tlb_miss_tgpr:
2550
            /* Swap temporary saved registers with GPRs */
2551
            swap_gpr_tgpr(env);
2552
            msr_tgpr = 1;
2553
            goto tlb_miss;
2554
        case POWERPC_EXCP_7x5:
2555
        tlb_miss:
2556
#if defined (DEBUG_SOFTWARE_TLB)
2557
            if (loglevel != 0) {
2558
                const unsigned char *es;
2559
                target_ulong *miss, *cmp;
2560
                int en;
2561
                if (excp == POWERPC_EXCP_IFTLB) {
2562
                    es = "I";
2563
                    en = 'I';
2564
                    miss = &env->spr[SPR_IMISS];
2565
                    cmp = &env->spr[SPR_ICMP];
2566
                } else {
2567
                    if (excp == POWERPC_EXCP_DLTLB)
2568
                        es = "DL";
2569
                    else
2570
                        es = "DS";
2571
                    en = 'D';
2572
                    miss = &env->spr[SPR_DMISS];
2573
                    cmp = &env->spr[SPR_DCMP];
2574
                }
2575
                fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2576
                        " H1 " ADDRX " H2 " ADDRX " %08x\n",
2577
                        es, en, *miss, en, *cmp,
2578
                        env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2579
                        env->error_code);
2580
            }
2581
#endif
2582
            msr |= env->crf[0] << 28;
2583
            msr |= env->error_code; /* key, D/I, S/L bits */
2584
            /* Set way using a LRU mechanism */
2585
            msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2586
            break;
2587
        case POWERPC_EXCP_74xx:
2588
        tlb_miss_74xx:
2589
#if defined (DEBUG_SOFTWARE_TLB)
2590
            if (loglevel != 0) {
2591
                const unsigned char *es;
2592
                target_ulong *miss, *cmp;
2593
                int en;
2594
                if (excp == POWERPC_EXCP_IFTLB) {
2595
                    es = "I";
2596
                    en = 'I';
2597
                    miss = &env->spr[SPR_IMISS];
2598
                    cmp = &env->spr[SPR_ICMP];
2599
                } else {
2600
                    if (excp == POWERPC_EXCP_DLTLB)
2601
                        es = "DL";
2602
                    else
2603
                        es = "DS";
2604
                    en = 'D';
2605
                    miss = &env->spr[SPR_TLBMISS];
2606
                    cmp = &env->spr[SPR_PTEHI];
2607
                }
2608
                fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2609
                        " %08x\n",
2610
                        es, en, *miss, en, *cmp, env->error_code);
2611
            }
2612
#endif
2613
            msr |= env->error_code; /* key bit */
2614
            break;
2615
        default:
2616
            cpu_abort(env, "Invalid data store TLB miss exception\n");
2617
            break;
2618
        }
2619
        goto store_next;
2620
    case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
2621
        /* XXX: TODO */
2622
        cpu_abort(env, "Floating point assist exception "
2623
                  "is not implemented yet !\n");
2624
        goto store_next;
2625
    case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
2626
        /* XXX: TODO */
2627
        cpu_abort(env, "IABR exception is not implemented yet !\n");
2628
        goto store_next;
2629
    case POWERPC_EXCP_SMI:       /* System management interrupt              */
2630
        /* XXX: TODO */
2631
        cpu_abort(env, "SMI exception is not implemented yet !\n");
2632
        goto store_next;
2633
    case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
2634
        /* XXX: TODO */
2635
        cpu_abort(env, "Thermal management exception "
2636
                  "is not implemented yet !\n");
2637
        goto store_next;
2638
    case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
2639
        msr_ri = 0;
2640
#if defined(TARGET_PPC64H)
2641
        if (lpes1 == 0)
2642
            msr_hv = 1;
2643
#endif
2644
        /* XXX: TODO */
2645
        cpu_abort(env,
2646
                  "Performance counter exception is not implemented yet !\n");
2647
        goto store_next;
2648
    case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
2649
        /* XXX: TODO */
2650
        cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2651
        goto store_next;
2652
    case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
2653
        /* XXX: TODO */
2654
        cpu_abort(env,
2655
                  "970 soft-patch exception is not implemented yet !\n");
2656
        goto store_next;
2657
    case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
2658
        /* XXX: TODO */
2659
        cpu_abort(env,
2660
                  "970 maintenance exception is not implemented yet !\n");
2661
        goto store_next;
2662
    default:
2663
    excp_invalid:
2664
        cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2665
        break;
2666
    store_current:
2667
        /* save current instruction location */
2668
        env->spr[srr0] = env->nip - 4;
2669
        break;
2670
    store_next:
2671
        /* save next instruction location */
2672
        env->spr[srr0] = env->nip;
2673
        break;
2674
    }
2675
    /* Save MSR */
2676
    env->spr[srr1] = msr;
2677
    /* If any alternate SRR register are defined, duplicate saved values */
2678
    if (asrr0 != -1)
2679
        env->spr[asrr0] = env->spr[srr0];
2680
    if (asrr1 != -1)
2681
        env->spr[asrr1] = env->spr[srr1];
2682
    /* If we disactivated any translation, flush TLBs */
2683
    if (msr_ir || msr_dr)
2684
        tlb_flush(env, 1);
2685
    /* reload MSR with correct bits */
2686
    msr_ee = 0;
2687
    msr_pr = 0;
2688
    msr_fp = 0;
2689
    msr_fe0 = 0;
2690
    msr_se = 0;
2691
    msr_be = 0;
2692
    msr_fe1 = 0;
2693
    msr_ir = 0;
2694
    msr_dr = 0;
2695
#if 0 /* Fix this: not on all targets */
2696
    msr_pmm = 0;
2697
#endif
2698
    msr_le = msr_ile;
2699
    do_compute_hflags(env);
2700
    /* Jump to handler */
2701
    vector = env->excp_vectors[excp];
2702
    if (vector == (target_ulong)-1) {
2703
        cpu_abort(env, "Raised an exception without defined vector %d\n",
2704
                  excp);
2705
    }
2706
    vector |= env->excp_prefix;
2707
#if defined(TARGET_PPC64)
2708
    if (excp_model == POWERPC_EXCP_BOOKE) {
2709
        msr_cm = msr_icm;
2710
        if (!msr_cm)
2711
            vector = (uint32_t)vector;
2712
    } else {
2713
        msr_sf = msr_isf;
2714
        if (!msr_sf)
2715
            vector = (uint32_t)vector;
2716
    }
2717
#endif
2718
    env->nip = vector;
2719
    /* Reset exception state */
2720
    env->exception_index = POWERPC_EXCP_NONE;
2721
    env->error_code = 0;
2722
}
2723

    
2724
void do_interrupt (CPUState *env)
2725
{
2726
    powerpc_excp(env, env->excp_model, env->exception_index);
2727
}
2728

    
2729
void ppc_hw_interrupt (CPUPPCState *env)
2730
{
2731
#if 1
2732
    if (loglevel & CPU_LOG_INT) {
2733
        fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2734
                __func__, env, env->pending_interrupts,
2735
                env->interrupt_request, msr_me, msr_ee);
2736
    }
2737
#endif
2738
    /* External reset */
2739
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2740
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2741
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2742
        return;
2743
    }
2744
    /* Machine check exception */
2745
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2746
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2747
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2748
        return;
2749
    }
2750
#if 0 /* TODO */
2751
    /* External debug exception */
2752
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2753
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2754
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2755
        return;
2756
    }
2757
#endif
2758
#if defined(TARGET_PPC64H)
2759
    if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
2760
        /* Hypervisor decrementer exception */
2761
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2762
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2763
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2764
            return;
2765
        }
2766
    }
2767
#endif
2768
    if (msr_ce != 0) {
2769
        /* External critical interrupt */
2770
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2771
            /* Taking a critical external interrupt does not clear the external
2772
             * critical interrupt status
2773
             */
2774
#if 0
2775
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2776
#endif
2777
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2778
            return;
2779
        }
2780
    }
2781
    if (msr_ee != 0) {
2782
        /* Watchdog timer on embedded PowerPC */
2783
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2784
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2785
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2786
            return;
2787
        }
2788
#if defined(TARGET_PPCEMB)
2789
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2790
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2791
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2792
            return;
2793
        }
2794
#endif
2795
#if defined(TARGET_PPCEMB)
2796
        /* External interrupt */
2797
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2798
            /* Taking an external interrupt does not clear the external
2799
             * interrupt status
2800
             */
2801
#if 0
2802
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2803
#endif
2804
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2805
            return;
2806
        }
2807
#endif
2808
        /* Fixed interval timer on embedded PowerPC */
2809
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2810
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2811
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2812
            return;
2813
        }
2814
        /* Programmable interval timer on embedded PowerPC */
2815
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2816
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2817
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2818
            return;
2819
        }
2820
        /* Decrementer exception */
2821
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2822
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2823
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2824
            return;
2825
        }
2826
#if !defined(TARGET_PPCEMB)
2827
        /* External interrupt */
2828
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2829
            /* Taking an external interrupt does not clear the external
2830
             * interrupt status
2831
             */
2832
#if 0
2833
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2834
#endif
2835
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2836
            return;
2837
        }
2838
#endif
2839
#if defined(TARGET_PPCEMB)
2840
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2841
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2842
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2843
            return;
2844
        }
2845
#endif
2846
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2847
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2848
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2849
            return;
2850
        }
2851
        /* Thermal interrupt */
2852
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2853
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2854
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2855
            return;
2856
        }
2857
    }
2858
}
2859
#endif /* !CONFIG_USER_ONLY */
2860

    
2861
void cpu_dump_EA (target_ulong EA)
2862
{
2863
    FILE *f;
2864

    
2865
    if (logfile) {
2866
        f = logfile;
2867
    } else {
2868
        f = stdout;
2869
        return;
2870
    }
2871
    fprintf(f, "Memory access at address " ADDRX "\n", EA);
2872
}
2873

    
2874
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2875
{
2876
    FILE *f;
2877

    
2878
    if (logfile) {
2879
        f = logfile;
2880
    } else {
2881
        f = stdout;
2882
        return;
2883
    }
2884
    fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2885
            RA, msr);
2886
}
2887

    
2888
void cpu_ppc_reset (void *opaque)
2889
{
2890
    CPUPPCState *env;
2891
    int i;
2892

    
2893
    env = opaque;
2894
    /* XXX: some of those flags initialisation values could depend
2895
     *      on the actual PowerPC implementation
2896
     */
2897
    for (i = 0; i < 63; i++)
2898
        env->msr[i] = 0;
2899
#if defined(TARGET_PPC64)
2900
    msr_hv = 0; /* Should be 1... */
2901
#endif
2902
    msr_ap = 0; /* TO BE CHECKED */
2903
    msr_sa = 0; /* TO BE CHECKED */
2904
    msr_ip = 0; /* TO BE CHECKED */
2905
#if defined (DO_SINGLE_STEP) && 0
2906
    /* Single step trace mode */
2907
    msr_se = 1;
2908
    msr_be = 1;
2909
#endif
2910
#if defined(CONFIG_USER_ONLY)
2911
    msr_fp = 1; /* Allow floating point exceptions */
2912
    msr_pr = 1;
2913
#else
2914
    env->nip = env->hreset_vector | env->excp_prefix;
2915
    ppc_tlb_invalidate_all(env);
2916
#endif
2917
    do_compute_hflags(env);
2918
    env->reserve = -1;
2919
    /* Be sure no exception or interrupt is pending */
2920
    env->pending_interrupts = 0;
2921
    env->exception_index = POWERPC_EXCP_NONE;
2922
    env->error_code = 0;
2923
    /* Flush all TLBs */
2924
    tlb_flush(env, 1);
2925
}
2926

    
2927
CPUPPCState *cpu_ppc_init (void)
2928
{
2929
    CPUPPCState *env;
2930

    
2931
    env = qemu_mallocz(sizeof(CPUPPCState));
2932
    if (!env)
2933
        return NULL;
2934
    cpu_exec_init(env);
2935

    
2936
    return env;
2937
}
2938

    
2939
void cpu_ppc_close (CPUPPCState *env)
2940
{
2941
    /* Should also remove all opcode tables... */
2942
    free(env);
2943
}