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root / target-ppc @ b068d6a7

Name Size
STATUS 9 kB
cpu.h 46.3 kB
exec.h 3.5 kB
helper.c 92.5 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 652 Bytes
op.c 49.6 kB
op_helper.c 61.1 kB
op_helper.h 11.2 kB
op_helper_mem.h 13.8 kB
op_mem.h 39.9 kB
op_template.h 3.8 kB
translate.c 226.1 kB
translate_init.c 246.9 kB

Latest revisions

# Date Author Comment
b068d6a7 10/07/2007 08:13 pm j_mayer

PowerPC target optimisations: make intensive use of always_inline.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3347 c046a42c-6fe2-441c-8c8c-71466251a162

f2e63a42 10/07/2007 06:43 pm j_mayer

Reorganize the CPUPPCState structure to group features.
Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets....

d26bfc9a 10/07/2007 05:41 pm j_mayer

Add MSR bits signification per PowerPC implementation flags (to be continued).
As a side effect, single step and branch step are available again.
Remove irrelevant MSR bits definitions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3342 c046a42c-6fe2-441c-8c8c-71466251a162

12de9a39 10/06/2007 01:06 am j_mayer

Full implementation of PowerPC 64 MMU, just missing support for 1 TB
memory segments.
Remove the PowerPC 64 "bridge" MMU model and implement segment registers
emulation using SLB entries instead.
Make SLB area size implementation dependant.
Improve TLB & SLB search debug traces....

65f9ee8d 10/05/2007 04:11 pm j_mayer

Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3333 c046a42c-6fe2-441c-8c8c-71466251a162

1c27f8fb 10/05/2007 04:09 pm j_mayer

PowerPC hardware reset vector is now considered as part of the exception model.
Use it at CPU initialisation time.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3332 c046a42c-6fe2-441c-8c8c-71466251a162

e57448f1 10/04/2007 04:50 am j_mayer More cache tuning fixes:
  • fix the tunable cache line size probe for PowerPC 970.
  • initialize HID5 so cache line is 32 bytes long when running in user-mode only

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3322 c046a42c-6fe2-441c-8c8c-71466251a162

d63001d1 10/04/2007 03:51 am j_mayer

Make PowerPC cache line size implementation dependant.
Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162

06403421 10/03/2007 11:27 pm j_mayer

HID0 is a write-clear register on 970 (DBSR).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3320 c046a42c-6fe2-441c-8c8c-71466251a162

8f793433 10/03/2007 11:19 pm j_mayer

Enable PowerPC 64 MMU model and exceptions.
Cleanups in MMU exceptions generation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3319 c046a42c-6fe2-441c-8c8c-71466251a162

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