Revision b0a21b53 hw/vga.c
b/hw/vga.c | ||
---|---|---|
1578 | 1578 |
vga_mem_writel, |
1579 | 1579 |
}; |
1580 | 1580 |
|
1581 |
static void vga_save(QEMUFile *f, void *opaque) |
|
1582 |
{ |
|
1583 |
VGAState *s = opaque; |
|
1584 |
int i; |
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1585 |
|
|
1586 |
qemu_put_be32s(f, &s->latch); |
|
1587 |
qemu_put_8s(f, &s->sr_index); |
|
1588 |
qemu_put_buffer(f, s->sr, 8); |
|
1589 |
qemu_put_8s(f, &s->gr_index); |
|
1590 |
qemu_put_buffer(f, s->gr, 16); |
|
1591 |
qemu_put_8s(f, &s->ar_index); |
|
1592 |
qemu_put_buffer(f, s->ar, 21); |
|
1593 |
qemu_put_be32s(f, &s->ar_flip_flop); |
|
1594 |
qemu_put_8s(f, &s->cr_index); |
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1595 |
qemu_put_buffer(f, s->cr, 256); |
|
1596 |
qemu_put_8s(f, &s->msr); |
|
1597 |
qemu_put_8s(f, &s->fcr); |
|
1598 |
qemu_put_8s(f, &s->st00); |
|
1599 |
qemu_put_8s(f, &s->st01); |
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1600 |
|
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1601 |
qemu_put_8s(f, &s->dac_state); |
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1602 |
qemu_put_8s(f, &s->dac_sub_index); |
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1603 |
qemu_put_8s(f, &s->dac_read_index); |
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1604 |
qemu_put_8s(f, &s->dac_write_index); |
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1605 |
qemu_put_buffer(f, s->dac_cache, 3); |
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1606 |
qemu_put_buffer(f, s->palette, 768); |
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1607 |
|
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1608 |
qemu_put_be32s(f, &s->bank_offset); |
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1609 |
#ifdef CONFIG_BOCHS_VBE |
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1610 |
qemu_put_byte(f, 1); |
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1611 |
qemu_put_be16s(f, &s->vbe_index); |
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1612 |
for(i = 0; i < VBE_DISPI_INDEX_NB; i++) |
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1613 |
qemu_put_be16s(f, &s->vbe_regs[i]); |
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1614 |
qemu_put_be32s(f, &s->vbe_start_addr); |
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1615 |
qemu_put_be32s(f, &s->vbe_line_offset); |
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1616 |
qemu_put_be32s(f, &s->vbe_bank_mask); |
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1617 |
#else |
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1618 |
qemu_put_byte(f, 0); |
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1619 |
#endif |
|
1620 |
} |
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1621 |
|
|
1622 |
static int vga_load(QEMUFile *f, void *opaque, int version_id) |
|
1623 |
{ |
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1624 |
VGAState *s = opaque; |
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1625 |
int is_vbe, i; |
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1626 |
|
|
1627 |
if (version_id != 1) |
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1628 |
return -EINVAL; |
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1629 |
|
|
1630 |
qemu_get_be32s(f, &s->latch); |
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1631 |
qemu_get_8s(f, &s->sr_index); |
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1632 |
qemu_get_buffer(f, s->sr, 8); |
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1633 |
qemu_get_8s(f, &s->gr_index); |
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1634 |
qemu_get_buffer(f, s->gr, 16); |
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1635 |
qemu_get_8s(f, &s->ar_index); |
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1636 |
qemu_get_buffer(f, s->ar, 21); |
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1637 |
qemu_get_be32s(f, &s->ar_flip_flop); |
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1638 |
qemu_get_8s(f, &s->cr_index); |
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1639 |
qemu_get_buffer(f, s->cr, 256); |
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1640 |
qemu_get_8s(f, &s->msr); |
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1641 |
qemu_get_8s(f, &s->fcr); |
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1642 |
qemu_get_8s(f, &s->st00); |
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1643 |
qemu_get_8s(f, &s->st01); |
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1644 |
|
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1645 |
qemu_get_8s(f, &s->dac_state); |
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1646 |
qemu_get_8s(f, &s->dac_sub_index); |
|
1647 |
qemu_get_8s(f, &s->dac_read_index); |
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1648 |
qemu_get_8s(f, &s->dac_write_index); |
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1649 |
qemu_get_buffer(f, s->dac_cache, 3); |
|
1650 |
qemu_get_buffer(f, s->palette, 768); |
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1651 |
|
|
1652 |
qemu_get_be32s(f, &s->bank_offset); |
|
1653 |
is_vbe = qemu_get_byte(f); |
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1654 |
#ifdef CONFIG_BOCHS_VBE |
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1655 |
if (!is_vbe) |
|
1656 |
return -EINVAL; |
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1657 |
qemu_get_be16s(f, &s->vbe_index); |
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1658 |
for(i = 0; i < VBE_DISPI_INDEX_NB; i++) |
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1659 |
qemu_get_be16s(f, &s->vbe_regs[i]); |
|
1660 |
qemu_get_be32s(f, &s->vbe_start_addr); |
|
1661 |
qemu_get_be32s(f, &s->vbe_line_offset); |
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1662 |
qemu_get_be32s(f, &s->vbe_bank_mask); |
|
1663 |
#else |
|
1664 |
if (is_vbe) |
|
1665 |
return -EINVAL; |
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1666 |
#endif |
|
1667 |
|
|
1668 |
/* force refresh */ |
|
1669 |
s->graphic_mode = -1; |
|
1670 |
return 0; |
|
1671 |
} |
|
1672 |
|
|
1581 | 1673 |
int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base, |
1582 | 1674 |
unsigned long vga_ram_offset, int vga_ram_size) |
1583 | 1675 |
{ |
... | ... | |
1614 | 1706 |
s->vram_size = vga_ram_size; |
1615 | 1707 |
s->ds = ds; |
1616 | 1708 |
|
1709 |
register_savevm("vga", 0, 1, vga_save, vga_load, s); |
|
1710 |
|
|
1617 | 1711 |
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); |
1618 | 1712 |
|
1619 | 1713 |
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s); |
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