Revision b14ef7c9
b/exec-all.h | ||
---|---|---|
323 | 323 |
pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
324 | 324 |
if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
325 | 325 |
#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC) |
326 |
do_unassigned_access(addr, 0, 1, 0, 4);
|
|
326 |
cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
|
|
327 | 327 |
#else |
328 | 328 |
cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
329 | 329 |
#endif |
b/exec.c | ||
---|---|---|
3238 | 3238 |
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
3239 | 3239 |
#endif |
3240 | 3240 |
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
3241 |
do_unassigned_access(addr, 0, 0, 0, 1);
|
|
3241 |
cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 1);
|
|
3242 | 3242 |
#endif |
3243 | 3243 |
return 0; |
3244 | 3244 |
} |
... | ... | |
3249 | 3249 |
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
3250 | 3250 |
#endif |
3251 | 3251 |
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
3252 |
do_unassigned_access(addr, 0, 0, 0, 2);
|
|
3252 |
cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 2);
|
|
3253 | 3253 |
#endif |
3254 | 3254 |
return 0; |
3255 | 3255 |
} |
... | ... | |
3260 | 3260 |
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
3261 | 3261 |
#endif |
3262 | 3262 |
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
3263 |
do_unassigned_access(addr, 0, 0, 0, 4);
|
|
3263 |
cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 4);
|
|
3264 | 3264 |
#endif |
3265 | 3265 |
return 0; |
3266 | 3266 |
} |
... | ... | |
3271 | 3271 |
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
3272 | 3272 |
#endif |
3273 | 3273 |
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
3274 |
do_unassigned_access(addr, 1, 0, 0, 1);
|
|
3274 |
cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 1);
|
|
3275 | 3275 |
#endif |
3276 | 3276 |
} |
3277 | 3277 |
|
... | ... | |
3281 | 3281 |
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
3282 | 3282 |
#endif |
3283 | 3283 |
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
3284 |
do_unassigned_access(addr, 1, 0, 0, 2);
|
|
3284 |
cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 2);
|
|
3285 | 3285 |
#endif |
3286 | 3286 |
} |
3287 | 3287 |
|
... | ... | |
3291 | 3291 |
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
3292 | 3292 |
#endif |
3293 | 3293 |
#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
3294 |
do_unassigned_access(addr, 1, 0, 0, 4);
|
|
3294 |
cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 4);
|
|
3295 | 3295 |
#endif |
3296 | 3296 |
} |
3297 | 3297 |
|
b/target-alpha/cpu.h | ||
---|---|---|
434 | 434 |
void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); |
435 | 435 |
#ifndef CONFIG_USER_ONLY |
436 | 436 |
void swap_shadow_regs(CPUState *env); |
437 |
extern QEMU_NORETURN void do_unassigned_access(target_phys_addr_t addr, |
|
438 |
int, int, int, int); |
|
437 |
QEMU_NORETURN void cpu_unassigned_access(CPUState *env1, |
|
438 |
target_phys_addr_t addr, int is_write, |
|
439 |
int is_exec, int unused, int size); |
|
439 | 440 |
#endif |
440 | 441 |
|
441 | 442 |
/* Bits in TB->FLAGS that control how translation is processed. */ |
b/target-alpha/op_helper.c | ||
---|---|---|
1301 | 1301 |
helper_excp(EXCP_UNALIGN, 0); |
1302 | 1302 |
} |
1303 | 1303 |
|
1304 |
void QEMU_NORETURN do_unassigned_access(target_phys_addr_t addr, int is_write, |
|
1305 |
int is_exec, int unused, int size) |
|
1304 |
void QEMU_NORETURN cpu_unassigned_access(CPUState *env1, |
|
1305 |
target_phys_addr_t addr, int is_write, |
|
1306 |
int is_exec, int unused, int size) |
|
1306 | 1307 |
{ |
1308 |
env = env1; |
|
1307 | 1309 |
env->trap_arg0 = addr; |
1308 | 1310 |
env->trap_arg1 = is_write; |
1309 | 1311 |
dynamic_excp(EXCP_MCHK, 0); |
b/target-microblaze/cpu.h | ||
---|---|---|
347 | 347 |
} |
348 | 348 |
|
349 | 349 |
#if !defined(CONFIG_USER_ONLY) |
350 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
351 |
int is_asi, int size); |
|
350 |
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
|
|
351 |
int is_write, int is_exec, int is_asi, int size);
|
|
352 | 352 |
#endif |
353 | 353 |
|
354 | 354 |
static inline bool cpu_has_work(CPUState *env) |
b/target-microblaze/op_helper.c | ||
---|---|---|
488 | 488 |
mmu_write(env, rn, v); |
489 | 489 |
} |
490 | 490 |
|
491 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
492 |
int is_asi, int size) |
|
491 |
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
|
|
492 |
int is_write, int is_exec, int is_asi, int size)
|
|
493 | 493 |
{ |
494 | 494 |
CPUState *saved_env; |
495 | 495 |
|
496 |
if (!cpu_single_env) { |
|
497 |
/* XXX: ??? */ |
|
498 |
return; |
|
499 |
} |
|
500 |
|
|
501 |
/* XXX: hack to restore env in all cases, even if not called from |
|
502 |
generated code */ |
|
503 | 496 |
saved_env = env; |
504 |
env = cpu_single_env; |
|
497 |
env = env1; |
|
498 |
|
|
505 | 499 |
qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n", |
506 | 500 |
addr, is_write, is_exec); |
507 | 501 |
if (!(env->sregs[SR_MSR] & MSR_EE)) { |
b/target-mips/cpu.h | ||
---|---|---|
493 | 493 |
void r4k_helper_tlbp (void); |
494 | 494 |
void r4k_helper_tlbr (void); |
495 | 495 |
|
496 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
497 |
int unused, int size); |
|
496 |
void cpu_unassigned_access(CPUState *env, target_phys_addr_t addr,
|
|
497 |
int is_write, int is_exec, int unused, int size);
|
|
498 | 498 |
#endif |
499 | 499 |
|
500 | 500 |
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
b/target-mips/op_helper.c | ||
---|---|---|
1980 | 1980 |
env = saved_env; |
1981 | 1981 |
} |
1982 | 1982 |
|
1983 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
1984 |
int unused, int size) |
|
1983 |
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
|
|
1984 |
int is_write, int is_exec, int unused, int size)
|
|
1985 | 1985 |
{ |
1986 |
env = env1; |
|
1987 |
|
|
1986 | 1988 |
if (is_exec) |
1987 | 1989 |
helper_raise_exception(EXCP_IBE); |
1988 | 1990 |
else |
b/target-sparc/cpu.h | ||
---|---|---|
510 | 510 |
|
511 | 511 |
/* cpu-exec.c */ |
512 | 512 |
#if !defined(CONFIG_USER_ONLY) |
513 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
514 |
int is_asi, int size); |
|
513 |
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
|
|
514 |
int is_write, int is_exec, int is_asi, int size);
|
|
515 | 515 |
target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr, |
516 | 516 |
int mmu_idx); |
517 | 517 |
|
b/target-sparc/op_helper.c | ||
---|---|---|
79 | 79 |
#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ |
80 | 80 |
#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ |
81 | 81 |
|
82 |
#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) |
|
82 |
#if !defined(CONFIG_USER_ONLY) |
|
83 |
static void do_unassigned_access(target_phys_addr_t addr, int is_write, |
|
84 |
int is_exec, int is_asi, int size); |
|
85 |
#else |
|
86 |
#ifdef TARGET_SPARC64 |
|
83 | 87 |
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
84 |
int is_asi, int size); |
|
88 |
int is_asi, int size); |
|
89 |
#endif |
|
85 | 90 |
#endif |
86 | 91 |
|
87 | 92 |
#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) |
... | ... | |
4235 | 4240 |
|
4236 | 4241 |
#ifndef TARGET_SPARC64 |
4237 | 4242 |
#if !defined(CONFIG_USER_ONLY) |
4238 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
4239 |
int is_asi, int size) |
|
4243 |
static void do_unassigned_access(target_phys_addr_t addr, int is_write,
|
|
4244 |
int is_exec, int is_asi, int size)
|
|
4240 | 4245 |
{ |
4241 | 4246 |
CPUState *saved_env; |
4242 | 4247 |
int fault_type; |
... | ... | |
4301 | 4306 |
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
4302 | 4307 |
int is_asi, int size) |
4303 | 4308 |
#else |
4304 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
4305 |
int is_asi, int size) |
|
4309 |
static void do_unassigned_access(target_phys_addr_t addr, int is_write,
|
|
4310 |
int is_exec, int is_asi, int size)
|
|
4306 | 4311 |
#endif |
4307 | 4312 |
{ |
4308 | 4313 |
CPUState *saved_env; |
... | ... | |
4351 | 4356 |
#endif |
4352 | 4357 |
} |
4353 | 4358 |
#endif |
4359 |
|
|
4360 |
#if !defined(CONFIG_USER_ONLY) |
|
4361 |
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr, |
|
4362 |
int is_write, int is_exec, int is_asi, int size) |
|
4363 |
{ |
|
4364 |
env = env1; |
|
4365 |
do_unassigned_access(addr, is_write, is_exec, is_asi, size); |
|
4366 |
} |
|
4367 |
#endif |
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