root / target-ppc / helper.c @ b227a8e9
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | fdabc366 | bellard | #include <stdarg.h> |
21 | fdabc366 | bellard | #include <stdlib.h> |
22 | fdabc366 | bellard | #include <stdio.h> |
23 | fdabc366 | bellard | #include <string.h> |
24 | fdabc366 | bellard | #include <inttypes.h> |
25 | fdabc366 | bellard | #include <signal.h> |
26 | fdabc366 | bellard | #include <assert.h> |
27 | fdabc366 | bellard | |
28 | fdabc366 | bellard | #include "cpu.h" |
29 | fdabc366 | bellard | #include "exec-all.h" |
30 | 9a64fbe4 | bellard | |
31 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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32 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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33 | 76a66253 | j_mayer | //#define DEBUG_SOFTWARE_TLB
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34 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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35 | fdabc366 | bellard | //#define FLUSH_ALL_TLBS
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36 | 9a64fbe4 | bellard | |
37 | 9a64fbe4 | bellard | /*****************************************************************************/
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38 | 3fc6c082 | bellard | /* PowerPC MMU emulation */
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39 | a541f297 | bellard | |
40 | d9bce9d9 | j_mayer | #if defined(CONFIG_USER_ONLY)
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41 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
42 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
43 | 24741ef3 | bellard | { |
44 | 24741ef3 | bellard | int exception, error_code;
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45 | d9bce9d9 | j_mayer | |
46 | 24741ef3 | bellard | if (rw == 2) { |
47 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
48 | 8f793433 | j_mayer | error_code = 0x40000000;
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49 | 24741ef3 | bellard | } else {
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50 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
51 | 8f793433 | j_mayer | error_code = 0x40000000;
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52 | 24741ef3 | bellard | if (rw)
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53 | 24741ef3 | bellard | error_code |= 0x02000000;
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54 | 24741ef3 | bellard | env->spr[SPR_DAR] = address; |
55 | 24741ef3 | bellard | env->spr[SPR_DSISR] = error_code; |
56 | 24741ef3 | bellard | } |
57 | 24741ef3 | bellard | env->exception_index = exception; |
58 | 24741ef3 | bellard | env->error_code = error_code; |
59 | 76a66253 | j_mayer | |
60 | 24741ef3 | bellard | return 1; |
61 | 24741ef3 | bellard | } |
62 | 76a66253 | j_mayer | |
63 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
64 | 24741ef3 | bellard | { |
65 | 24741ef3 | bellard | return addr;
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66 | 24741ef3 | bellard | } |
67 | 36081602 | j_mayer | |
68 | 24741ef3 | bellard | #else
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69 | 76a66253 | j_mayer | /* Common routines used by software and hardware TLBs emulation */
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70 | b068d6a7 | j_mayer | static always_inline int pte_is_valid (target_ulong pte0) |
71 | 76a66253 | j_mayer | { |
72 | 76a66253 | j_mayer | return pte0 & 0x80000000 ? 1 : 0; |
73 | 76a66253 | j_mayer | } |
74 | 76a66253 | j_mayer | |
75 | b068d6a7 | j_mayer | static always_inline void pte_invalidate (target_ulong *pte0) |
76 | 76a66253 | j_mayer | { |
77 | 76a66253 | j_mayer | *pte0 &= ~0x80000000;
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78 | 76a66253 | j_mayer | } |
79 | 76a66253 | j_mayer | |
80 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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81 | b068d6a7 | j_mayer | static always_inline int pte64_is_valid (target_ulong pte0) |
82 | caa4039c | j_mayer | { |
83 | caa4039c | j_mayer | return pte0 & 0x0000000000000001ULL ? 1 : 0; |
84 | caa4039c | j_mayer | } |
85 | caa4039c | j_mayer | |
86 | b068d6a7 | j_mayer | static always_inline void pte64_invalidate (target_ulong *pte0) |
87 | caa4039c | j_mayer | { |
88 | caa4039c | j_mayer | *pte0 &= ~0x0000000000000001ULL;
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89 | caa4039c | j_mayer | } |
90 | caa4039c | j_mayer | #endif
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91 | caa4039c | j_mayer | |
92 | 76a66253 | j_mayer | #define PTE_PTEM_MASK 0x7FFFFFBF |
93 | 76a66253 | j_mayer | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
94 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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95 | caa4039c | j_mayer | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
96 | caa4039c | j_mayer | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
97 | caa4039c | j_mayer | #endif
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98 | 76a66253 | j_mayer | |
99 | b227a8e9 | j_mayer | static always_inline int pp_check (int key, int pp, int nx) |
100 | b227a8e9 | j_mayer | { |
101 | b227a8e9 | j_mayer | int access;
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102 | b227a8e9 | j_mayer | |
103 | b227a8e9 | j_mayer | /* Compute access rights */
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104 | b227a8e9 | j_mayer | /* When pp is 3/7, the result is undefined. Set it to noaccess */
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105 | b227a8e9 | j_mayer | access = 0;
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106 | b227a8e9 | j_mayer | if (key == 0) { |
107 | b227a8e9 | j_mayer | switch (pp) {
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108 | b227a8e9 | j_mayer | case 0x0: |
109 | b227a8e9 | j_mayer | case 0x1: |
110 | b227a8e9 | j_mayer | case 0x2: |
111 | b227a8e9 | j_mayer | access |= PAGE_WRITE; |
112 | b227a8e9 | j_mayer | /* No break here */
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113 | b227a8e9 | j_mayer | case 0x3: |
114 | b227a8e9 | j_mayer | case 0x6: |
115 | b227a8e9 | j_mayer | access |= PAGE_READ; |
116 | b227a8e9 | j_mayer | break;
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117 | b227a8e9 | j_mayer | } |
118 | b227a8e9 | j_mayer | } else {
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119 | b227a8e9 | j_mayer | switch (pp) {
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120 | b227a8e9 | j_mayer | case 0x0: |
121 | b227a8e9 | j_mayer | case 0x6: |
122 | b227a8e9 | j_mayer | access = 0;
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123 | b227a8e9 | j_mayer | break;
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124 | b227a8e9 | j_mayer | case 0x1: |
125 | b227a8e9 | j_mayer | case 0x3: |
126 | b227a8e9 | j_mayer | access = PAGE_READ; |
127 | b227a8e9 | j_mayer | break;
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128 | b227a8e9 | j_mayer | case 0x2: |
129 | b227a8e9 | j_mayer | access = PAGE_READ | PAGE_WRITE; |
130 | b227a8e9 | j_mayer | break;
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131 | b227a8e9 | j_mayer | } |
132 | b227a8e9 | j_mayer | } |
133 | b227a8e9 | j_mayer | if (nx == 0) |
134 | b227a8e9 | j_mayer | access |= PAGE_EXEC; |
135 | b227a8e9 | j_mayer | |
136 | b227a8e9 | j_mayer | return access;
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137 | b227a8e9 | j_mayer | } |
138 | b227a8e9 | j_mayer | |
139 | b227a8e9 | j_mayer | static always_inline int check_prot (int prot, int rw, int access_type) |
140 | b227a8e9 | j_mayer | { |
141 | b227a8e9 | j_mayer | int ret;
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142 | b227a8e9 | j_mayer | |
143 | b227a8e9 | j_mayer | if (access_type == ACCESS_CODE) {
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144 | b227a8e9 | j_mayer | if (prot & PAGE_EXEC)
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145 | b227a8e9 | j_mayer | ret = 0;
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146 | b227a8e9 | j_mayer | else
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147 | b227a8e9 | j_mayer | ret = -2;
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148 | b227a8e9 | j_mayer | } else if (rw) { |
149 | b227a8e9 | j_mayer | if (prot & PAGE_WRITE)
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150 | b227a8e9 | j_mayer | ret = 0;
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151 | b227a8e9 | j_mayer | else
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152 | b227a8e9 | j_mayer | ret = -2;
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153 | b227a8e9 | j_mayer | } else {
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154 | b227a8e9 | j_mayer | if (prot & PAGE_READ)
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155 | b227a8e9 | j_mayer | ret = 0;
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156 | b227a8e9 | j_mayer | else
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157 | b227a8e9 | j_mayer | ret = -2;
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158 | b227a8e9 | j_mayer | } |
159 | b227a8e9 | j_mayer | |
160 | b227a8e9 | j_mayer | return ret;
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161 | b227a8e9 | j_mayer | } |
162 | b227a8e9 | j_mayer | |
163 | b068d6a7 | j_mayer | static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
164 | b068d6a7 | j_mayer | target_ulong pte0, target_ulong pte1, |
165 | b227a8e9 | j_mayer | int h, int rw, int type) |
166 | 76a66253 | j_mayer | { |
167 | caa4039c | j_mayer | target_ulong ptem, mmask; |
168 | b227a8e9 | j_mayer | int access, ret, pteh, ptev, pp;
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169 | 76a66253 | j_mayer | |
170 | 76a66253 | j_mayer | access = 0;
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171 | 76a66253 | j_mayer | ret = -1;
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172 | 76a66253 | j_mayer | /* Check validity and table match */
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173 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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174 | caa4039c | j_mayer | if (is_64b) {
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175 | caa4039c | j_mayer | ptev = pte64_is_valid(pte0); |
176 | caa4039c | j_mayer | pteh = (pte0 >> 1) & 1; |
177 | caa4039c | j_mayer | } else
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178 | caa4039c | j_mayer | #endif
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179 | caa4039c | j_mayer | { |
180 | caa4039c | j_mayer | ptev = pte_is_valid(pte0); |
181 | caa4039c | j_mayer | pteh = (pte0 >> 6) & 1; |
182 | caa4039c | j_mayer | } |
183 | caa4039c | j_mayer | if (ptev && h == pteh) {
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184 | 76a66253 | j_mayer | /* Check vsid & api */
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185 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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186 | caa4039c | j_mayer | if (is_64b) {
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187 | caa4039c | j_mayer | ptem = pte0 & PTE64_PTEM_MASK; |
188 | caa4039c | j_mayer | mmask = PTE64_CHECK_MASK; |
189 | b227a8e9 | j_mayer | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
190 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */ |
191 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
192 | caa4039c | j_mayer | } else
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193 | caa4039c | j_mayer | #endif
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194 | caa4039c | j_mayer | { |
195 | caa4039c | j_mayer | ptem = pte0 & PTE_PTEM_MASK; |
196 | caa4039c | j_mayer | mmask = PTE_CHECK_MASK; |
197 | b227a8e9 | j_mayer | pp = pte1 & 0x00000003;
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198 | caa4039c | j_mayer | } |
199 | caa4039c | j_mayer | if (ptem == ctx->ptem) {
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200 | 76a66253 | j_mayer | if (ctx->raddr != (target_ulong)-1) { |
201 | 76a66253 | j_mayer | /* all matches should have equal RPN, WIMG & PP */
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202 | caa4039c | j_mayer | if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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203 | caa4039c | j_mayer | if (loglevel != 0) |
204 | 76a66253 | j_mayer | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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205 | 76a66253 | j_mayer | return -3; |
206 | 76a66253 | j_mayer | } |
207 | 76a66253 | j_mayer | } |
208 | 76a66253 | j_mayer | /* Compute access rights */
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209 | b227a8e9 | j_mayer | access = pp_check(ctx->key, pp, ctx->nx); |
210 | 76a66253 | j_mayer | /* Keep the matching PTE informations */
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211 | 76a66253 | j_mayer | ctx->raddr = pte1; |
212 | 76a66253 | j_mayer | ctx->prot = access; |
213 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
214 | b227a8e9 | j_mayer | if (ret == 0) { |
215 | 76a66253 | j_mayer | /* Access granted */
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216 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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217 | 4a057712 | j_mayer | if (loglevel != 0) |
218 | 76a66253 | j_mayer | fprintf(logfile, "PTE access granted !\n");
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219 | 76a66253 | j_mayer | #endif
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220 | 76a66253 | j_mayer | } else {
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221 | 76a66253 | j_mayer | /* Access right violation */
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222 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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223 | 4a057712 | j_mayer | if (loglevel != 0) |
224 | 76a66253 | j_mayer | fprintf(logfile, "PTE access rejected\n");
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225 | 76a66253 | j_mayer | #endif
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226 | 76a66253 | j_mayer | } |
227 | 76a66253 | j_mayer | } |
228 | 76a66253 | j_mayer | } |
229 | 76a66253 | j_mayer | |
230 | 76a66253 | j_mayer | return ret;
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231 | 76a66253 | j_mayer | } |
232 | 76a66253 | j_mayer | |
233 | b227a8e9 | j_mayer | static int pte32_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1, |
234 | b227a8e9 | j_mayer | int h, int rw, int type) |
235 | caa4039c | j_mayer | { |
236 | b227a8e9 | j_mayer | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
237 | caa4039c | j_mayer | } |
238 | caa4039c | j_mayer | |
239 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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240 | b227a8e9 | j_mayer | static int pte64_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1, |
241 | b227a8e9 | j_mayer | int h, int rw, int type) |
242 | caa4039c | j_mayer | { |
243 | b227a8e9 | j_mayer | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
244 | caa4039c | j_mayer | } |
245 | caa4039c | j_mayer | #endif
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246 | caa4039c | j_mayer | |
247 | 76a66253 | j_mayer | static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
248 | 76a66253 | j_mayer | int ret, int rw) |
249 | 76a66253 | j_mayer | { |
250 | 76a66253 | j_mayer | int store = 0; |
251 | 76a66253 | j_mayer | |
252 | 76a66253 | j_mayer | /* Update page flags */
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253 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000100)) { |
254 | 76a66253 | j_mayer | /* Update accessed flag */
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255 | 76a66253 | j_mayer | *pte1p |= 0x00000100;
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256 | 76a66253 | j_mayer | store = 1;
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257 | 76a66253 | j_mayer | } |
258 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000080)) { |
259 | 76a66253 | j_mayer | if (rw == 1 && ret == 0) { |
260 | 76a66253 | j_mayer | /* Update changed flag */
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261 | 76a66253 | j_mayer | *pte1p |= 0x00000080;
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262 | 76a66253 | j_mayer | store = 1;
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263 | 76a66253 | j_mayer | } else {
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264 | 76a66253 | j_mayer | /* Force page fault for first write access */
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265 | 76a66253 | j_mayer | ctx->prot &= ~PAGE_WRITE; |
266 | 76a66253 | j_mayer | } |
267 | 76a66253 | j_mayer | } |
268 | 76a66253 | j_mayer | |
269 | 76a66253 | j_mayer | return store;
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270 | 76a66253 | j_mayer | } |
271 | 76a66253 | j_mayer | |
272 | 76a66253 | j_mayer | /* Software driven TLB helpers */
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273 | 76a66253 | j_mayer | static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
274 | 76a66253 | j_mayer | int way, int is_code) |
275 | 76a66253 | j_mayer | { |
276 | 76a66253 | j_mayer | int nr;
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277 | 76a66253 | j_mayer | |
278 | 76a66253 | j_mayer | /* Select TLB num in a way from address */
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279 | 76a66253 | j_mayer | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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280 | 76a66253 | j_mayer | /* Select TLB way */
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281 | 76a66253 | j_mayer | nr += env->tlb_per_way * way; |
282 | 76a66253 | j_mayer | /* 6xx have separate TLBs for instructions and data */
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283 | 76a66253 | j_mayer | if (is_code && env->id_tlbs == 1) |
284 | 76a66253 | j_mayer | nr += env->nb_tlb; |
285 | 76a66253 | j_mayer | |
286 | 76a66253 | j_mayer | return nr;
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287 | 76a66253 | j_mayer | } |
288 | 76a66253 | j_mayer | |
289 | daf4f96e | j_mayer | static void ppc6xx_tlb_invalidate_all (CPUState *env) |
290 | 76a66253 | j_mayer | { |
291 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
292 | 76a66253 | j_mayer | int nr, max;
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293 | 76a66253 | j_mayer | |
294 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB) && 0 |
295 | 76a66253 | j_mayer | if (loglevel != 0) { |
296 | 76a66253 | j_mayer | fprintf(logfile, "Invalidate all TLBs\n");
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297 | 76a66253 | j_mayer | } |
298 | 76a66253 | j_mayer | #endif
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299 | 76a66253 | j_mayer | /* Invalidate all defined software TLB */
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300 | 76a66253 | j_mayer | max = env->nb_tlb; |
301 | 76a66253 | j_mayer | if (env->id_tlbs == 1) |
302 | 76a66253 | j_mayer | max *= 2;
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303 | 76a66253 | j_mayer | for (nr = 0; nr < max; nr++) { |
304 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
305 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
306 | 76a66253 | j_mayer | } |
307 | 76a66253 | j_mayer | tlb_flush(env, 1);
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308 | 76a66253 | j_mayer | } |
309 | 76a66253 | j_mayer | |
310 | b068d6a7 | j_mayer | static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
311 | b068d6a7 | j_mayer | target_ulong eaddr, |
312 | b068d6a7 | j_mayer | int is_code,
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313 | b068d6a7 | j_mayer | int match_epn)
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314 | 76a66253 | j_mayer | { |
315 | 4a057712 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
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316 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
317 | 76a66253 | j_mayer | int way, nr;
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318 | 76a66253 | j_mayer | |
319 | 76a66253 | j_mayer | /* Invalidate ITLB + DTLB, all ways */
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320 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
321 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
322 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
323 | 76a66253 | j_mayer | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
324 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
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325 | 76a66253 | j_mayer | if (loglevel != 0) { |
326 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
327 | 76a66253 | j_mayer | nr, env->nb_tlb, eaddr); |
328 | 76a66253 | j_mayer | } |
329 | 76a66253 | j_mayer | #endif
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330 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
331 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
332 | 76a66253 | j_mayer | } |
333 | 76a66253 | j_mayer | } |
334 | 76a66253 | j_mayer | #else
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335 | 76a66253 | j_mayer | /* XXX: PowerPC specification say this is valid as well */
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336 | 76a66253 | j_mayer | ppc6xx_tlb_invalidate_all(env); |
337 | 76a66253 | j_mayer | #endif
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338 | 76a66253 | j_mayer | } |
339 | 76a66253 | j_mayer | |
340 | daf4f96e | j_mayer | static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr, |
341 | daf4f96e | j_mayer | int is_code)
|
342 | 76a66253 | j_mayer | { |
343 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
344 | 76a66253 | j_mayer | } |
345 | 76a66253 | j_mayer | |
346 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
347 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1) |
348 | 76a66253 | j_mayer | { |
349 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
350 | 76a66253 | j_mayer | int nr;
|
351 | 76a66253 | j_mayer | |
352 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
353 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
354 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
355 | 76a66253 | j_mayer | if (loglevel != 0) { |
356 | 5fafdf24 | ths | fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
357 | 1b9eb036 | j_mayer | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
358 | 76a66253 | j_mayer | } |
359 | 76a66253 | j_mayer | #endif
|
360 | 76a66253 | j_mayer | /* Invalidate any pending reference in Qemu for this virtual address */
|
361 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
362 | 76a66253 | j_mayer | tlb->pte0 = pte0; |
363 | 76a66253 | j_mayer | tlb->pte1 = pte1; |
364 | 76a66253 | j_mayer | tlb->EPN = EPN; |
365 | 76a66253 | j_mayer | /* Store last way for LRU mechanism */
|
366 | 76a66253 | j_mayer | env->last_way = way; |
367 | 76a66253 | j_mayer | } |
368 | 76a66253 | j_mayer | |
369 | 76a66253 | j_mayer | static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
370 | 76a66253 | j_mayer | target_ulong eaddr, int rw, int access_type) |
371 | 76a66253 | j_mayer | { |
372 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
373 | 76a66253 | j_mayer | int nr, best, way;
|
374 | 76a66253 | j_mayer | int ret;
|
375 | d9bce9d9 | j_mayer | |
376 | 76a66253 | j_mayer | best = -1;
|
377 | 76a66253 | j_mayer | ret = -1; /* No TLB found */ |
378 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
379 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, |
380 | 76a66253 | j_mayer | access_type == ACCESS_CODE ? 1 : 0); |
381 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
382 | 76a66253 | j_mayer | /* This test "emulates" the PTE index match for hardware TLBs */
|
383 | 76a66253 | j_mayer | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
384 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
385 | 76a66253 | j_mayer | if (loglevel != 0) { |
386 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
387 | 1b9eb036 | j_mayer | "] <> " ADDRX "\n", |
388 | 76a66253 | j_mayer | nr, env->nb_tlb, |
389 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
390 | 76a66253 | j_mayer | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
391 | 76a66253 | j_mayer | } |
392 | 76a66253 | j_mayer | #endif
|
393 | 76a66253 | j_mayer | continue;
|
394 | 76a66253 | j_mayer | } |
395 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
396 | 76a66253 | j_mayer | if (loglevel != 0) { |
397 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
398 | 1b9eb036 | j_mayer | " %c %c\n",
|
399 | 76a66253 | j_mayer | nr, env->nb_tlb, |
400 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
401 | 76a66253 | j_mayer | tlb->EPN, eaddr, tlb->pte1, |
402 | 76a66253 | j_mayer | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
403 | 76a66253 | j_mayer | } |
404 | 76a66253 | j_mayer | #endif
|
405 | b227a8e9 | j_mayer | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
406 | 76a66253 | j_mayer | case -3: |
407 | 76a66253 | j_mayer | /* TLB inconsistency */
|
408 | 76a66253 | j_mayer | return -1; |
409 | 76a66253 | j_mayer | case -2: |
410 | 76a66253 | j_mayer | /* Access violation */
|
411 | 76a66253 | j_mayer | ret = -2;
|
412 | 76a66253 | j_mayer | best = nr; |
413 | 76a66253 | j_mayer | break;
|
414 | 76a66253 | j_mayer | case -1: |
415 | 76a66253 | j_mayer | default:
|
416 | 76a66253 | j_mayer | /* No match */
|
417 | 76a66253 | j_mayer | break;
|
418 | 76a66253 | j_mayer | case 0: |
419 | 76a66253 | j_mayer | /* access granted */
|
420 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all TLBs consistency
|
421 | 76a66253 | j_mayer | * but we can speed-up the whole thing as the
|
422 | 76a66253 | j_mayer | * result would be undefined if TLBs are not consistent.
|
423 | 76a66253 | j_mayer | */
|
424 | 76a66253 | j_mayer | ret = 0;
|
425 | 76a66253 | j_mayer | best = nr; |
426 | 76a66253 | j_mayer | goto done;
|
427 | 76a66253 | j_mayer | } |
428 | 76a66253 | j_mayer | } |
429 | 76a66253 | j_mayer | if (best != -1) { |
430 | 76a66253 | j_mayer | done:
|
431 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
432 | 4a057712 | j_mayer | if (loglevel != 0) { |
433 | 76a66253 | j_mayer | fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
|
434 | 76a66253 | j_mayer | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
435 | 76a66253 | j_mayer | } |
436 | 76a66253 | j_mayer | #endif
|
437 | 76a66253 | j_mayer | /* Update page flags */
|
438 | 1d0a48fb | j_mayer | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
439 | 76a66253 | j_mayer | } |
440 | 76a66253 | j_mayer | |
441 | 76a66253 | j_mayer | return ret;
|
442 | 76a66253 | j_mayer | } |
443 | 76a66253 | j_mayer | |
444 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
|
445 | 76a66253 | j_mayer | static int get_bat (CPUState *env, mmu_ctx_t *ctx, |
446 | 76a66253 | j_mayer | target_ulong virtual, int rw, int type) |
447 | 9a64fbe4 | bellard | { |
448 | 76a66253 | j_mayer | target_ulong *BATlt, *BATut, *BATu, *BATl; |
449 | 76a66253 | j_mayer | target_ulong base, BEPIl, BEPIu, bl; |
450 | b227a8e9 | j_mayer | int i, pp;
|
451 | 9a64fbe4 | bellard | int ret = -1; |
452 | 9a64fbe4 | bellard | |
453 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
454 | 4a057712 | j_mayer | if (loglevel != 0) { |
455 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
456 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
457 | 9a64fbe4 | bellard | } |
458 | 9a64fbe4 | bellard | #endif
|
459 | 9a64fbe4 | bellard | switch (type) {
|
460 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
461 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
|
462 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
|
463 | 9a64fbe4 | bellard | break;
|
464 | 9a64fbe4 | bellard | default:
|
465 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
|
466 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
|
467 | 9a64fbe4 | bellard | break;
|
468 | 9a64fbe4 | bellard | } |
469 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
470 | 4a057712 | j_mayer | if (loglevel != 0) { |
471 | 1b9eb036 | j_mayer | fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
472 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
473 | 9a64fbe4 | bellard | } |
474 | 9a64fbe4 | bellard | #endif
|
475 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
|
476 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
477 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
478 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
479 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
|
480 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
|
481 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
482 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
483 | 4a057712 | j_mayer | if (loglevel != 0) { |
484 | 5fafdf24 | ths | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
485 | 1b9eb036 | j_mayer | " BATl 0x" ADDRX "\n", |
486 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
487 | 9a64fbe4 | bellard | *BATu, *BATl); |
488 | 9a64fbe4 | bellard | } |
489 | 9a64fbe4 | bellard | #endif
|
490 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
491 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
492 | 9a64fbe4 | bellard | /* BAT matches */
|
493 | 9a64fbe4 | bellard | if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
494 | 9a64fbe4 | bellard | (msr_pr == 1 && (*BATu & 0x00000001))) { |
495 | 9a64fbe4 | bellard | /* Get physical address */
|
496 | 76a66253 | j_mayer | ctx->raddr = (*BATl & 0xF0000000) |
|
497 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
498 | a541f297 | bellard | (virtual & 0x0001F000);
|
499 | b227a8e9 | j_mayer | /* Compute access rights */
|
500 | b227a8e9 | j_mayer | pp = *BATl & 0x00000003;
|
501 | b227a8e9 | j_mayer | ctx->prot = 0;
|
502 | b227a8e9 | j_mayer | if (pp != 0) { |
503 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
504 | b227a8e9 | j_mayer | if (pp == 0x2) |
505 | b227a8e9 | j_mayer | ctx->prot |= PAGE_WRITE; |
506 | b227a8e9 | j_mayer | } |
507 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
508 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
509 | b227a8e9 | j_mayer | if (ret == 0 && loglevel != 0) { |
510 | 4a057712 | j_mayer | fprintf(logfile, "BAT %d match: r 0x" PADDRX
|
511 | 1b9eb036 | j_mayer | " prot=%c%c\n",
|
512 | 76a66253 | j_mayer | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
513 | 76a66253 | j_mayer | ctx->prot & PAGE_WRITE ? 'W' : '-'); |
514 | 9a64fbe4 | bellard | } |
515 | 9a64fbe4 | bellard | #endif
|
516 | 9a64fbe4 | bellard | break;
|
517 | 9a64fbe4 | bellard | } |
518 | 9a64fbe4 | bellard | } |
519 | 9a64fbe4 | bellard | } |
520 | 9a64fbe4 | bellard | if (ret < 0) { |
521 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
522 | 4a057712 | j_mayer | if (loglevel != 0) { |
523 | 4a057712 | j_mayer | fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual); |
524 | 4a057712 | j_mayer | for (i = 0; i < 4; i++) { |
525 | 4a057712 | j_mayer | BATu = &BATut[i]; |
526 | 4a057712 | j_mayer | BATl = &BATlt[i]; |
527 | 4a057712 | j_mayer | BEPIu = *BATu & 0xF0000000;
|
528 | 4a057712 | j_mayer | BEPIl = *BATu & 0x0FFE0000;
|
529 | 4a057712 | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
530 | 4a057712 | j_mayer | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
531 | 4a057712 | j_mayer | " BATl 0x" ADDRX " \n\t" |
532 | 4a057712 | j_mayer | "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", |
533 | 4a057712 | j_mayer | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
534 | 4a057712 | j_mayer | *BATu, *BATl, BEPIu, BEPIl, bl); |
535 | 4a057712 | j_mayer | } |
536 | 9a64fbe4 | bellard | } |
537 | 9a64fbe4 | bellard | #endif
|
538 | 9a64fbe4 | bellard | } |
539 | b227a8e9 | j_mayer | |
540 | 9a64fbe4 | bellard | /* No hit */
|
541 | 9a64fbe4 | bellard | return ret;
|
542 | 9a64fbe4 | bellard | } |
543 | 9a64fbe4 | bellard | |
544 | 9a64fbe4 | bellard | /* PTE table lookup */
|
545 | b227a8e9 | j_mayer | static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
546 | b227a8e9 | j_mayer | int rw, int type) |
547 | 9a64fbe4 | bellard | { |
548 | 76a66253 | j_mayer | target_ulong base, pte0, pte1; |
549 | 76a66253 | j_mayer | int i, good = -1; |
550 | caa4039c | j_mayer | int ret, r;
|
551 | 9a64fbe4 | bellard | |
552 | 76a66253 | j_mayer | ret = -1; /* No entry found */ |
553 | 76a66253 | j_mayer | base = ctx->pg_addr[h]; |
554 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
555 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
556 | caa4039c | j_mayer | if (is_64b) {
|
557 | caa4039c | j_mayer | pte0 = ldq_phys(base + (i * 16));
|
558 | caa4039c | j_mayer | pte1 = ldq_phys(base + (i * 16) + 8); |
559 | b227a8e9 | j_mayer | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
560 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
561 | 12de9a39 | j_mayer | if (loglevel != 0) { |
562 | 12de9a39 | j_mayer | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
563 | 12de9a39 | j_mayer | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", |
564 | 12de9a39 | j_mayer | base + (i * 16), pte0, pte1,
|
565 | 12de9a39 | j_mayer | (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), |
566 | 12de9a39 | j_mayer | ctx->ptem); |
567 | 12de9a39 | j_mayer | } |
568 | 12de9a39 | j_mayer | #endif
|
569 | caa4039c | j_mayer | } else
|
570 | caa4039c | j_mayer | #endif
|
571 | caa4039c | j_mayer | { |
572 | caa4039c | j_mayer | pte0 = ldl_phys(base + (i * 8));
|
573 | caa4039c | j_mayer | pte1 = ldl_phys(base + (i * 8) + 4); |
574 | b227a8e9 | j_mayer | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
575 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
576 | 12de9a39 | j_mayer | if (loglevel != 0) { |
577 | 12de9a39 | j_mayer | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
578 | 12de9a39 | j_mayer | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", |
579 | 12de9a39 | j_mayer | base + (i * 8), pte0, pte1,
|
580 | 12de9a39 | j_mayer | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), |
581 | 12de9a39 | j_mayer | ctx->ptem); |
582 | 12de9a39 | j_mayer | } |
583 | 9a64fbe4 | bellard | #endif
|
584 | 12de9a39 | j_mayer | } |
585 | caa4039c | j_mayer | switch (r) {
|
586 | 76a66253 | j_mayer | case -3: |
587 | 76a66253 | j_mayer | /* PTE inconsistency */
|
588 | 76a66253 | j_mayer | return -1; |
589 | 76a66253 | j_mayer | case -2: |
590 | 76a66253 | j_mayer | /* Access violation */
|
591 | 76a66253 | j_mayer | ret = -2;
|
592 | 76a66253 | j_mayer | good = i; |
593 | 76a66253 | j_mayer | break;
|
594 | 76a66253 | j_mayer | case -1: |
595 | 76a66253 | j_mayer | default:
|
596 | 76a66253 | j_mayer | /* No PTE match */
|
597 | 76a66253 | j_mayer | break;
|
598 | 76a66253 | j_mayer | case 0: |
599 | 76a66253 | j_mayer | /* access granted */
|
600 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all PTEs consistency
|
601 | 76a66253 | j_mayer | * but if we can speed-up the whole thing as the
|
602 | 76a66253 | j_mayer | * result would be undefined if PTEs are not consistent.
|
603 | 76a66253 | j_mayer | */
|
604 | 76a66253 | j_mayer | ret = 0;
|
605 | 76a66253 | j_mayer | good = i; |
606 | 76a66253 | j_mayer | goto done;
|
607 | 9a64fbe4 | bellard | } |
608 | 9a64fbe4 | bellard | } |
609 | 9a64fbe4 | bellard | if (good != -1) { |
610 | 76a66253 | j_mayer | done:
|
611 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
612 | 4a057712 | j_mayer | if (loglevel != 0) { |
613 | 4a057712 | j_mayer | fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x " |
614 | 1b9eb036 | j_mayer | "ret=%d\n",
|
615 | 76a66253 | j_mayer | ctx->raddr, ctx->prot, ret); |
616 | 76a66253 | j_mayer | } |
617 | 9a64fbe4 | bellard | #endif
|
618 | 9a64fbe4 | bellard | /* Update page flags */
|
619 | 76a66253 | j_mayer | pte1 = ctx->raddr; |
620 | caa4039c | j_mayer | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
621 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
622 | caa4039c | j_mayer | if (is_64b) {
|
623 | caa4039c | j_mayer | stq_phys_notdirty(base + (good * 16) + 8, pte1); |
624 | caa4039c | j_mayer | } else
|
625 | caa4039c | j_mayer | #endif
|
626 | caa4039c | j_mayer | { |
627 | caa4039c | j_mayer | stl_phys_notdirty(base + (good * 8) + 4, pte1); |
628 | caa4039c | j_mayer | } |
629 | caa4039c | j_mayer | } |
630 | 9a64fbe4 | bellard | } |
631 | 9a64fbe4 | bellard | |
632 | 9a64fbe4 | bellard | return ret;
|
633 | 79aceca5 | bellard | } |
634 | 79aceca5 | bellard | |
635 | b227a8e9 | j_mayer | static int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type) |
636 | caa4039c | j_mayer | { |
637 | b227a8e9 | j_mayer | return _find_pte(ctx, 0, h, rw, type); |
638 | caa4039c | j_mayer | } |
639 | caa4039c | j_mayer | |
640 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
641 | b227a8e9 | j_mayer | static int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type) |
642 | caa4039c | j_mayer | { |
643 | b227a8e9 | j_mayer | return _find_pte(ctx, 1, h, rw, type); |
644 | caa4039c | j_mayer | } |
645 | caa4039c | j_mayer | #endif
|
646 | caa4039c | j_mayer | |
647 | b068d6a7 | j_mayer | static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
648 | b227a8e9 | j_mayer | int h, int rw, int type) |
649 | caa4039c | j_mayer | { |
650 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
651 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B)
|
652 | b227a8e9 | j_mayer | return find_pte64(ctx, h, rw, type);
|
653 | caa4039c | j_mayer | #endif
|
654 | caa4039c | j_mayer | |
655 | b227a8e9 | j_mayer | return find_pte32(ctx, h, rw, type);
|
656 | caa4039c | j_mayer | } |
657 | caa4039c | j_mayer | |
658 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
659 | eacc3249 | j_mayer | static inline int slb_is_valid (uint64_t slb64) |
660 | eacc3249 | j_mayer | { |
661 | eacc3249 | j_mayer | return slb64 & 0x0000000008000000ULL ? 1 : 0; |
662 | eacc3249 | j_mayer | } |
663 | eacc3249 | j_mayer | |
664 | eacc3249 | j_mayer | static inline void slb_invalidate (uint64_t *slb64) |
665 | eacc3249 | j_mayer | { |
666 | eacc3249 | j_mayer | *slb64 &= ~0x0000000008000000ULL;
|
667 | eacc3249 | j_mayer | } |
668 | eacc3249 | j_mayer | |
669 | 12de9a39 | j_mayer | static int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
670 | caa4039c | j_mayer | target_ulong *vsid, target_ulong *page_mask, int *attr)
|
671 | caa4039c | j_mayer | { |
672 | caa4039c | j_mayer | target_phys_addr_t sr_base; |
673 | caa4039c | j_mayer | target_ulong mask; |
674 | caa4039c | j_mayer | uint64_t tmp64; |
675 | caa4039c | j_mayer | uint32_t tmp; |
676 | caa4039c | j_mayer | int n, ret;
|
677 | caa4039c | j_mayer | |
678 | caa4039c | j_mayer | ret = -5;
|
679 | caa4039c | j_mayer | sr_base = env->spr[SPR_ASR]; |
680 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
681 | 12de9a39 | j_mayer | if (loglevel != 0) { |
682 | 12de9a39 | j_mayer | fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n", |
683 | 12de9a39 | j_mayer | __func__, eaddr, sr_base); |
684 | 12de9a39 | j_mayer | } |
685 | 12de9a39 | j_mayer | #endif
|
686 | caa4039c | j_mayer | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
687 | eacc3249 | j_mayer | for (n = 0; n < env->slb_nr; n++) { |
688 | caa4039c | j_mayer | tmp64 = ldq_phys(sr_base); |
689 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
690 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
691 | 12de9a39 | j_mayer | if (loglevel != 0) { |
692 | b33c17e1 | j_mayer | fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08" |
693 | b33c17e1 | j_mayer | PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
|
694 | 12de9a39 | j_mayer | } |
695 | 12de9a39 | j_mayer | #endif
|
696 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
697 | caa4039c | j_mayer | /* SLB entry is valid */
|
698 | caa4039c | j_mayer | switch (tmp64 & 0x0000000006000000ULL) { |
699 | caa4039c | j_mayer | case 0x0000000000000000ULL: |
700 | caa4039c | j_mayer | /* 256 MB segment */
|
701 | caa4039c | j_mayer | mask = 0xFFFFFFFFF0000000ULL;
|
702 | caa4039c | j_mayer | break;
|
703 | caa4039c | j_mayer | case 0x0000000002000000ULL: |
704 | caa4039c | j_mayer | /* 1 TB segment */
|
705 | caa4039c | j_mayer | mask = 0xFFFF000000000000ULL;
|
706 | caa4039c | j_mayer | break;
|
707 | caa4039c | j_mayer | case 0x0000000004000000ULL: |
708 | caa4039c | j_mayer | case 0x0000000006000000ULL: |
709 | caa4039c | j_mayer | /* Reserved => segment is invalid */
|
710 | caa4039c | j_mayer | continue;
|
711 | caa4039c | j_mayer | } |
712 | caa4039c | j_mayer | if ((eaddr & mask) == (tmp64 & mask)) {
|
713 | caa4039c | j_mayer | /* SLB match */
|
714 | caa4039c | j_mayer | *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
715 | caa4039c | j_mayer | *page_mask = ~mask; |
716 | caa4039c | j_mayer | *attr = tmp & 0xFF;
|
717 | eacc3249 | j_mayer | ret = n; |
718 | caa4039c | j_mayer | break;
|
719 | caa4039c | j_mayer | } |
720 | caa4039c | j_mayer | } |
721 | caa4039c | j_mayer | sr_base += 12;
|
722 | caa4039c | j_mayer | } |
723 | caa4039c | j_mayer | |
724 | caa4039c | j_mayer | return ret;
|
725 | 79aceca5 | bellard | } |
726 | 12de9a39 | j_mayer | |
727 | eacc3249 | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env)
|
728 | eacc3249 | j_mayer | { |
729 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
730 | eacc3249 | j_mayer | uint64_t tmp64; |
731 | eacc3249 | j_mayer | int n, do_invalidate;
|
732 | eacc3249 | j_mayer | |
733 | eacc3249 | j_mayer | do_invalidate = 0;
|
734 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
735 | eacc3249 | j_mayer | for (n = 0; n < env->slb_nr; n++) { |
736 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
737 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
738 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
739 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
740 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
741 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
742 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
743 | eacc3249 | j_mayer | */
|
744 | eacc3249 | j_mayer | do_invalidate = 1;
|
745 | eacc3249 | j_mayer | } |
746 | eacc3249 | j_mayer | sr_base += 12;
|
747 | eacc3249 | j_mayer | } |
748 | eacc3249 | j_mayer | if (do_invalidate)
|
749 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
750 | eacc3249 | j_mayer | } |
751 | eacc3249 | j_mayer | |
752 | eacc3249 | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
|
753 | eacc3249 | j_mayer | { |
754 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
755 | eacc3249 | j_mayer | target_ulong vsid, page_mask; |
756 | eacc3249 | j_mayer | uint64_t tmp64; |
757 | eacc3249 | j_mayer | int attr;
|
758 | eacc3249 | j_mayer | int n;
|
759 | eacc3249 | j_mayer | |
760 | eacc3249 | j_mayer | n = slb_lookup(env, T0, &vsid, &page_mask, &attr); |
761 | eacc3249 | j_mayer | if (n >= 0) { |
762 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
763 | eacc3249 | j_mayer | sr_base += 12 * n;
|
764 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
765 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
766 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
767 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
768 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
769 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
770 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
771 | eacc3249 | j_mayer | */
|
772 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
773 | eacc3249 | j_mayer | } |
774 | eacc3249 | j_mayer | } |
775 | eacc3249 | j_mayer | } |
776 | eacc3249 | j_mayer | |
777 | 12de9a39 | j_mayer | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
|
778 | 12de9a39 | j_mayer | { |
779 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
780 | 12de9a39 | j_mayer | target_ulong rt; |
781 | 12de9a39 | j_mayer | uint64_t tmp64; |
782 | 12de9a39 | j_mayer | uint32_t tmp; |
783 | 12de9a39 | j_mayer | |
784 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
785 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
786 | 12de9a39 | j_mayer | tmp64 = ldq_phys(sr_base); |
787 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
788 | 12de9a39 | j_mayer | if (tmp64 & 0x0000000008000000ULL) { |
789 | 12de9a39 | j_mayer | /* SLB entry is valid */
|
790 | 12de9a39 | j_mayer | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
|
791 | 12de9a39 | j_mayer | rt = tmp >> 8; /* 65:88 => 40:63 */ |
792 | 12de9a39 | j_mayer | rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ |
793 | 12de9a39 | j_mayer | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
|
794 | 12de9a39 | j_mayer | rt |= ((tmp >> 4) & 0xF) << 27; |
795 | 12de9a39 | j_mayer | } else {
|
796 | 12de9a39 | j_mayer | rt = 0;
|
797 | 12de9a39 | j_mayer | } |
798 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
799 | 12de9a39 | j_mayer | if (loglevel != 0) { |
800 | 12de9a39 | j_mayer | fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d " |
801 | 12de9a39 | j_mayer | ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
|
802 | 12de9a39 | j_mayer | } |
803 | 12de9a39 | j_mayer | #endif
|
804 | 12de9a39 | j_mayer | |
805 | 12de9a39 | j_mayer | return rt;
|
806 | 12de9a39 | j_mayer | } |
807 | 12de9a39 | j_mayer | |
808 | 12de9a39 | j_mayer | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs) |
809 | 12de9a39 | j_mayer | { |
810 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
811 | 12de9a39 | j_mayer | uint64_t tmp64; |
812 | 12de9a39 | j_mayer | uint32_t tmp; |
813 | 12de9a39 | j_mayer | |
814 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
815 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
816 | 12de9a39 | j_mayer | /* Copy Rs bits 37:63 to SLB 62:88 */
|
817 | 12de9a39 | j_mayer | tmp = rs << 8;
|
818 | 12de9a39 | j_mayer | tmp64 = (rs >> 24) & 0x7; |
819 | 12de9a39 | j_mayer | /* Copy Rs bits 33:36 to SLB 89:92 */
|
820 | 12de9a39 | j_mayer | tmp |= ((rs >> 27) & 0xF) << 4; |
821 | 12de9a39 | j_mayer | /* Set the valid bit */
|
822 | 12de9a39 | j_mayer | tmp64 |= 1 << 27; |
823 | 12de9a39 | j_mayer | /* Set ESID */
|
824 | 12de9a39 | j_mayer | tmp64 |= (uint32_t)slb_nr << 28;
|
825 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
826 | 12de9a39 | j_mayer | if (loglevel != 0) { |
827 | 12de9a39 | j_mayer | fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08" |
828 | 12de9a39 | j_mayer | PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);
|
829 | 12de9a39 | j_mayer | } |
830 | 12de9a39 | j_mayer | #endif
|
831 | 12de9a39 | j_mayer | /* Write SLB entry to memory */
|
832 | 12de9a39 | j_mayer | stq_phys(sr_base, tmp64); |
833 | 12de9a39 | j_mayer | stl_phys(sr_base + 8, tmp);
|
834 | 12de9a39 | j_mayer | } |
835 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
836 | 79aceca5 | bellard | |
837 | 9a64fbe4 | bellard | /* Perform segment based translation */
|
838 | b068d6a7 | j_mayer | static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
|
839 | b068d6a7 | j_mayer | int sdr_sh,
|
840 | b068d6a7 | j_mayer | target_phys_addr_t hash, |
841 | b068d6a7 | j_mayer | target_phys_addr_t mask) |
842 | 12de9a39 | j_mayer | { |
843 | 12de9a39 | j_mayer | return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask); |
844 | 12de9a39 | j_mayer | } |
845 | 12de9a39 | j_mayer | |
846 | 76a66253 | j_mayer | static int get_segment (CPUState *env, mmu_ctx_t *ctx, |
847 | 76a66253 | j_mayer | target_ulong eaddr, int rw, int type) |
848 | 79aceca5 | bellard | { |
849 | 12de9a39 | j_mayer | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
850 | caa4039c | j_mayer | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
851 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
852 | caa4039c | j_mayer | int attr;
|
853 | 9a64fbe4 | bellard | #endif
|
854 | b227a8e9 | j_mayer | int ds, vsid_sh, sdr_sh;
|
855 | caa4039c | j_mayer | int ret, ret2;
|
856 | caa4039c | j_mayer | |
857 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
858 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B) {
|
859 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
860 | 12de9a39 | j_mayer | if (loglevel != 0) { |
861 | 12de9a39 | j_mayer | fprintf(logfile, "Check SLBs\n");
|
862 | 12de9a39 | j_mayer | } |
863 | 12de9a39 | j_mayer | #endif
|
864 | caa4039c | j_mayer | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); |
865 | caa4039c | j_mayer | if (ret < 0) |
866 | caa4039c | j_mayer | return ret;
|
867 | caa4039c | j_mayer | ctx->key = ((attr & 0x40) && msr_pr == 1) || |
868 | caa4039c | j_mayer | ((attr & 0x80) && msr_pr == 0) ? 1 : 0; |
869 | caa4039c | j_mayer | ds = 0;
|
870 | b227a8e9 | j_mayer | ctx->nx = attr & 0x20 ? 1 : 0; |
871 | caa4039c | j_mayer | vsid_mask = 0x00003FFFFFFFFF80ULL;
|
872 | caa4039c | j_mayer | vsid_sh = 7;
|
873 | caa4039c | j_mayer | sdr_sh = 18;
|
874 | caa4039c | j_mayer | sdr_mask = 0x3FF80;
|
875 | caa4039c | j_mayer | } else
|
876 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
877 | caa4039c | j_mayer | { |
878 | caa4039c | j_mayer | sr = env->sr[eaddr >> 28];
|
879 | caa4039c | j_mayer | page_mask = 0x0FFFFFFF;
|
880 | caa4039c | j_mayer | ctx->key = (((sr & 0x20000000) && msr_pr == 1) || |
881 | caa4039c | j_mayer | ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
882 | caa4039c | j_mayer | ds = sr & 0x80000000 ? 1 : 0; |
883 | b227a8e9 | j_mayer | ctx->nx = sr & 0x10000000 ? 1 : 0; |
884 | caa4039c | j_mayer | vsid = sr & 0x00FFFFFF;
|
885 | caa4039c | j_mayer | vsid_mask = 0x01FFFFC0;
|
886 | caa4039c | j_mayer | vsid_sh = 6;
|
887 | caa4039c | j_mayer | sdr_sh = 16;
|
888 | caa4039c | j_mayer | sdr_mask = 0xFFC0;
|
889 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
890 | caa4039c | j_mayer | if (loglevel != 0) { |
891 | caa4039c | j_mayer | fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX |
892 | caa4039c | j_mayer | " nip=0x" ADDRX " lr=0x" ADDRX |
893 | caa4039c | j_mayer | " ir=%d dr=%d pr=%d %d t=%d\n",
|
894 | caa4039c | j_mayer | eaddr, (int)(eaddr >> 28), sr, env->nip, |
895 | caa4039c | j_mayer | env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
896 | caa4039c | j_mayer | } |
897 | 9a64fbe4 | bellard | #endif
|
898 | caa4039c | j_mayer | } |
899 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
900 | 12de9a39 | j_mayer | if (loglevel != 0) { |
901 | 12de9a39 | j_mayer | fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", |
902 | b227a8e9 | j_mayer | ctx->key, ds, ctx->nx, vsid); |
903 | 12de9a39 | j_mayer | } |
904 | 12de9a39 | j_mayer | #endif
|
905 | caa4039c | j_mayer | ret = -1;
|
906 | caa4039c | j_mayer | if (!ds) {
|
907 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
|
908 | b227a8e9 | j_mayer | if (type != ACCESS_CODE || ctx->nx == 0) { |
909 | 9a64fbe4 | bellard | /* Page address translation */
|
910 | 76a66253 | j_mayer | /* Primary table address */
|
911 | 76a66253 | j_mayer | sdr = env->sdr1; |
912 | 12de9a39 | j_mayer | pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
913 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
914 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B) {
|
915 | 12de9a39 | j_mayer | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
916 | 12de9a39 | j_mayer | /* XXX: this is false for 1 TB segments */
|
917 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
918 | 12de9a39 | j_mayer | } else
|
919 | 12de9a39 | j_mayer | #endif
|
920 | 12de9a39 | j_mayer | { |
921 | 12de9a39 | j_mayer | htab_mask = sdr & 0x000001FF;
|
922 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
923 | 12de9a39 | j_mayer | } |
924 | 12de9a39 | j_mayer | mask = (htab_mask << sdr_sh) | sdr_mask; |
925 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
926 | 12de9a39 | j_mayer | if (loglevel != 0) { |
927 | 12de9a39 | j_mayer | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask " |
928 | 12de9a39 | j_mayer | PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask, |
929 | 12de9a39 | j_mayer | page_mask); |
930 | 12de9a39 | j_mayer | } |
931 | 12de9a39 | j_mayer | #endif
|
932 | caa4039c | j_mayer | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
933 | 76a66253 | j_mayer | /* Secondary table address */
|
934 | caa4039c | j_mayer | hash = (~hash) & vsid_mask; |
935 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
936 | 12de9a39 | j_mayer | if (loglevel != 0) { |
937 | 12de9a39 | j_mayer | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask " |
938 | 12de9a39 | j_mayer | PADDRX "\n", sdr, sdr_sh, hash, mask);
|
939 | 12de9a39 | j_mayer | } |
940 | 12de9a39 | j_mayer | #endif
|
941 | caa4039c | j_mayer | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
942 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
943 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B) {
|
944 | caa4039c | j_mayer | /* Only 5 bits of the page index are used in the AVPN */
|
945 | caa4039c | j_mayer | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
946 | caa4039c | j_mayer | } else
|
947 | caa4039c | j_mayer | #endif
|
948 | caa4039c | j_mayer | { |
949 | caa4039c | j_mayer | ctx->ptem = (vsid << 7) | (pgidx >> 10); |
950 | caa4039c | j_mayer | } |
951 | 76a66253 | j_mayer | /* Initialize real address with an invalid value */
|
952 | 76a66253 | j_mayer | ctx->raddr = (target_ulong)-1;
|
953 | 7dbe11ac | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
954 | 7dbe11ac | j_mayer | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { |
955 | 76a66253 | j_mayer | /* Software TLB search */
|
956 | 76a66253 | j_mayer | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
957 | 76a66253 | j_mayer | } else {
|
958 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
959 | 4a057712 | j_mayer | if (loglevel != 0) { |
960 | 4a057712 | j_mayer | fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x " |
961 | 4a057712 | j_mayer | "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n", |
962 | 4a057712 | j_mayer | sdr, (uint32_t)vsid, (uint32_t)pgidx, |
963 | 4a057712 | j_mayer | (uint32_t)hash, ctx->pg_addr[0]);
|
964 | 76a66253 | j_mayer | } |
965 | 9a64fbe4 | bellard | #endif
|
966 | 76a66253 | j_mayer | /* Primary table lookup */
|
967 | b227a8e9 | j_mayer | ret = find_pte(env, ctx, 0, rw, type);
|
968 | 76a66253 | j_mayer | if (ret < 0) { |
969 | 76a66253 | j_mayer | /* Secondary table lookup */
|
970 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
971 | 4a057712 | j_mayer | if (eaddr != 0xEFFFFFFF && loglevel != 0) { |
972 | 76a66253 | j_mayer | fprintf(logfile, |
973 | 4a057712 | j_mayer | "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x " |
974 | 4a057712 | j_mayer | "hash=0x%05x pg_addr=0x" PADDRX "\n", |
975 | 4a057712 | j_mayer | sdr, (uint32_t)vsid, (uint32_t)pgidx, |
976 | 4a057712 | j_mayer | (uint32_t)hash, ctx->pg_addr[1]);
|
977 | 76a66253 | j_mayer | } |
978 | 9a64fbe4 | bellard | #endif
|
979 | b227a8e9 | j_mayer | ret2 = find_pte(env, ctx, 1, rw, type);
|
980 | 76a66253 | j_mayer | if (ret2 != -1) |
981 | 76a66253 | j_mayer | ret = ret2; |
982 | 76a66253 | j_mayer | } |
983 | 9a64fbe4 | bellard | } |
984 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
985 | b33c17e1 | j_mayer | if (loglevel != 0) { |
986 | b33c17e1 | j_mayer | target_phys_addr_t curaddr; |
987 | b33c17e1 | j_mayer | uint32_t a0, a1, a2, a3; |
988 | b33c17e1 | j_mayer | fprintf(logfile, |
989 | b33c17e1 | j_mayer | "Page table: " PADDRX " len " PADDRX "\n", |
990 | b33c17e1 | j_mayer | sdr, mask + 0x80);
|
991 | b33c17e1 | j_mayer | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
992 | b33c17e1 | j_mayer | curaddr += 16) {
|
993 | b33c17e1 | j_mayer | a0 = ldl_phys(curaddr); |
994 | b33c17e1 | j_mayer | a1 = ldl_phys(curaddr + 4);
|
995 | b33c17e1 | j_mayer | a2 = ldl_phys(curaddr + 8);
|
996 | b33c17e1 | j_mayer | a3 = ldl_phys(curaddr + 12);
|
997 | b33c17e1 | j_mayer | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
998 | 12de9a39 | j_mayer | fprintf(logfile, |
999 | b33c17e1 | j_mayer | PADDRX ": %08x %08x %08x %08x\n",
|
1000 | b33c17e1 | j_mayer | curaddr, a0, a1, a2, a3); |
1001 | 12de9a39 | j_mayer | } |
1002 | b33c17e1 | j_mayer | } |
1003 | b33c17e1 | j_mayer | } |
1004 | 12de9a39 | j_mayer | #endif
|
1005 | 9a64fbe4 | bellard | } else {
|
1006 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1007 | 4a057712 | j_mayer | if (loglevel != 0) |
1008 | 76a66253 | j_mayer | fprintf(logfile, "No access allowed\n");
|
1009 | 9a64fbe4 | bellard | #endif
|
1010 | 76a66253 | j_mayer | ret = -3;
|
1011 | 9a64fbe4 | bellard | } |
1012 | 9a64fbe4 | bellard | } else {
|
1013 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1014 | 4a057712 | j_mayer | if (loglevel != 0) |
1015 | 76a66253 | j_mayer | fprintf(logfile, "direct store...\n");
|
1016 | 9a64fbe4 | bellard | #endif
|
1017 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
1018 | 9a64fbe4 | bellard | switch (type) {
|
1019 | 9a64fbe4 | bellard | case ACCESS_INT:
|
1020 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
1021 | 9a64fbe4 | bellard | break;
|
1022 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
1023 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1024 | 9a64fbe4 | bellard | return -4; |
1025 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1026 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1027 | 9a64fbe4 | bellard | return -4; |
1028 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1029 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
1030 | 9a64fbe4 | bellard | return -4; |
1031 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
1032 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
1033 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
1034 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
1035 | 9a64fbe4 | bellard | */
|
1036 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1037 | 9a64fbe4 | bellard | return 0; |
1038 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1039 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1040 | 9a64fbe4 | bellard | return -4; |
1041 | 9a64fbe4 | bellard | default:
|
1042 | 9a64fbe4 | bellard | if (logfile) {
|
1043 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
1044 | 9a64fbe4 | bellard | "address translation\n");
|
1045 | 9a64fbe4 | bellard | } |
1046 | 9a64fbe4 | bellard | return -4; |
1047 | 9a64fbe4 | bellard | } |
1048 | 76a66253 | j_mayer | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1049 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1050 | 9a64fbe4 | bellard | ret = 2;
|
1051 | 9a64fbe4 | bellard | } else {
|
1052 | 9a64fbe4 | bellard | ret = -2;
|
1053 | 9a64fbe4 | bellard | } |
1054 | 79aceca5 | bellard | } |
1055 | 9a64fbe4 | bellard | |
1056 | 9a64fbe4 | bellard | return ret;
|
1057 | 79aceca5 | bellard | } |
1058 | 79aceca5 | bellard | |
1059 | c294fc58 | j_mayer | /* Generic TLB check function for embedded PowerPC implementations */
|
1060 | c294fc58 | j_mayer | static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
1061 | c294fc58 | j_mayer | target_phys_addr_t *raddrp, |
1062 | 36081602 | j_mayer | target_ulong address, |
1063 | 36081602 | j_mayer | uint32_t pid, int ext, int i) |
1064 | c294fc58 | j_mayer | { |
1065 | c294fc58 | j_mayer | target_ulong mask; |
1066 | c294fc58 | j_mayer | |
1067 | c294fc58 | j_mayer | /* Check valid flag */
|
1068 | c294fc58 | j_mayer | if (!(tlb->prot & PAGE_VALID)) {
|
1069 | c294fc58 | j_mayer | if (loglevel != 0) |
1070 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
1071 | c294fc58 | j_mayer | return -1; |
1072 | c294fc58 | j_mayer | } |
1073 | c294fc58 | j_mayer | mask = ~(tlb->size - 1);
|
1074 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1075 | c294fc58 | j_mayer | if (loglevel != 0) { |
1076 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> " |
1077 | c294fc58 | j_mayer | ADDRX " " ADDRX " %d\n", |
1078 | 36081602 | j_mayer | __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
|
1079 | c294fc58 | j_mayer | } |
1080 | daf4f96e | j_mayer | #endif
|
1081 | c294fc58 | j_mayer | /* Check PID */
|
1082 | 36081602 | j_mayer | if (tlb->PID != 0 && tlb->PID != pid) |
1083 | c294fc58 | j_mayer | return -1; |
1084 | c294fc58 | j_mayer | /* Check effective address */
|
1085 | c294fc58 | j_mayer | if ((address & mask) != tlb->EPN)
|
1086 | c294fc58 | j_mayer | return -1; |
1087 | c294fc58 | j_mayer | *raddrp = (tlb->RPN & mask) | (address & ~mask); |
1088 | 9706285b | j_mayer | #if (TARGET_PHYS_ADDR_BITS >= 36) |
1089 | 36081602 | j_mayer | if (ext) {
|
1090 | 36081602 | j_mayer | /* Extend the physical address to 36 bits */
|
1091 | 36081602 | j_mayer | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
1092 | 36081602 | j_mayer | } |
1093 | 9706285b | j_mayer | #endif
|
1094 | c294fc58 | j_mayer | |
1095 | c294fc58 | j_mayer | return 0; |
1096 | c294fc58 | j_mayer | } |
1097 | c294fc58 | j_mayer | |
1098 | c294fc58 | j_mayer | /* Generic TLB search function for PowerPC embedded implementations */
|
1099 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
1100 | c294fc58 | j_mayer | { |
1101 | c294fc58 | j_mayer | ppcemb_tlb_t *tlb; |
1102 | c294fc58 | j_mayer | target_phys_addr_t raddr; |
1103 | c294fc58 | j_mayer | int i, ret;
|
1104 | c294fc58 | j_mayer | |
1105 | c294fc58 | j_mayer | /* Default return value is no match */
|
1106 | c294fc58 | j_mayer | ret = -1;
|
1107 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1108 | c294fc58 | j_mayer | tlb = &env->tlb[i].tlbe; |
1109 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
1110 | c294fc58 | j_mayer | ret = i; |
1111 | c294fc58 | j_mayer | break;
|
1112 | c294fc58 | j_mayer | } |
1113 | c294fc58 | j_mayer | } |
1114 | c294fc58 | j_mayer | |
1115 | c294fc58 | j_mayer | return ret;
|
1116 | c294fc58 | j_mayer | } |
1117 | c294fc58 | j_mayer | |
1118 | daf4f96e | j_mayer | /* Helpers specific to PowerPC 40x implementations */
|
1119 | daf4f96e | j_mayer | static void ppc4xx_tlb_invalidate_all (CPUState *env) |
1120 | a750fc0b | j_mayer | { |
1121 | a750fc0b | j_mayer | ppcemb_tlb_t *tlb; |
1122 | a750fc0b | j_mayer | int i;
|
1123 | a750fc0b | j_mayer | |
1124 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1125 | a750fc0b | j_mayer | tlb = &env->tlb[i].tlbe; |
1126 | daf4f96e | j_mayer | tlb->prot &= ~PAGE_VALID; |
1127 | a750fc0b | j_mayer | } |
1128 | daf4f96e | j_mayer | tlb_flush(env, 1);
|
1129 | a750fc0b | j_mayer | } |
1130 | a750fc0b | j_mayer | |
1131 | daf4f96e | j_mayer | static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr, |
1132 | daf4f96e | j_mayer | uint32_t pid) |
1133 | 0a032cbe | j_mayer | { |
1134 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1135 | 0a032cbe | j_mayer | ppcemb_tlb_t *tlb; |
1136 | daf4f96e | j_mayer | target_phys_addr_t raddr; |
1137 | daf4f96e | j_mayer | target_ulong page, end; |
1138 | 0a032cbe | j_mayer | int i;
|
1139 | 0a032cbe | j_mayer | |
1140 | 0a032cbe | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1141 | 0a032cbe | j_mayer | tlb = &env->tlb[i].tlbe; |
1142 | daf4f96e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
1143 | 0a032cbe | j_mayer | end = tlb->EPN + tlb->size; |
1144 | 0a032cbe | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
1145 | 0a032cbe | j_mayer | tlb_flush_page(env, page); |
1146 | 0a032cbe | j_mayer | tlb->prot &= ~PAGE_VALID; |
1147 | daf4f96e | j_mayer | break;
|
1148 | 0a032cbe | j_mayer | } |
1149 | 0a032cbe | j_mayer | } |
1150 | daf4f96e | j_mayer | #else
|
1151 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1152 | daf4f96e | j_mayer | #endif
|
1153 | 0a032cbe | j_mayer | } |
1154 | 0a032cbe | j_mayer | |
1155 | 36081602 | j_mayer | int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1156 | e96efcfc | j_mayer | target_ulong address, int rw, int access_type) |
1157 | a8dea12f | j_mayer | { |
1158 | a8dea12f | j_mayer | ppcemb_tlb_t *tlb; |
1159 | a8dea12f | j_mayer | target_phys_addr_t raddr; |
1160 | a8dea12f | j_mayer | int i, ret, zsel, zpr;
|
1161 | 3b46e624 | ths | |
1162 | c55e9aef | j_mayer | ret = -1;
|
1163 | c55e9aef | j_mayer | raddr = -1;
|
1164 | a8dea12f | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1165 | a8dea12f | j_mayer | tlb = &env->tlb[i].tlbe; |
1166 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1167 | 36081602 | j_mayer | env->spr[SPR_40x_PID], 0, i) < 0) |
1168 | a8dea12f | j_mayer | continue;
|
1169 | a8dea12f | j_mayer | zsel = (tlb->attr >> 4) & 0xF; |
1170 | a8dea12f | j_mayer | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
1171 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1172 | 4a057712 | j_mayer | if (loglevel != 0) { |
1173 | a8dea12f | j_mayer | fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
1174 | a8dea12f | j_mayer | __func__, i, zsel, zpr, rw, tlb->attr); |
1175 | a8dea12f | j_mayer | } |
1176 | daf4f96e | j_mayer | #endif
|
1177 | b227a8e9 | j_mayer | /* Check execute enable bit */
|
1178 | b227a8e9 | j_mayer | switch (zpr) {
|
1179 | b227a8e9 | j_mayer | case 0x2: |
1180 | b227a8e9 | j_mayer | if (msr_pr)
|
1181 | b227a8e9 | j_mayer | goto check_perms;
|
1182 | b227a8e9 | j_mayer | /* No break here */
|
1183 | b227a8e9 | j_mayer | case 0x3: |
1184 | b227a8e9 | j_mayer | /* All accesses granted */
|
1185 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1186 | b227a8e9 | j_mayer | ret = 0;
|
1187 | b227a8e9 | j_mayer | break;
|
1188 | b227a8e9 | j_mayer | case 0x0: |
1189 | b227a8e9 | j_mayer | if (msr_pr) {
|
1190 | b227a8e9 | j_mayer | ctx->prot = 0;
|
1191 | b227a8e9 | j_mayer | ret = -2;
|
1192 | a8dea12f | j_mayer | break;
|
1193 | a8dea12f | j_mayer | } |
1194 | b227a8e9 | j_mayer | /* No break here */
|
1195 | b227a8e9 | j_mayer | case 0x1: |
1196 | b227a8e9 | j_mayer | check_perms:
|
1197 | b227a8e9 | j_mayer | /* Check from TLB entry */
|
1198 | b227a8e9 | j_mayer | /* XXX: there is a problem here or in the TLB fill code... */
|
1199 | b227a8e9 | j_mayer | ctx->prot = tlb->prot; |
1200 | b227a8e9 | j_mayer | ctx->prot |= PAGE_EXEC; |
1201 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, access_type); |
1202 | b227a8e9 | j_mayer | break;
|
1203 | a8dea12f | j_mayer | } |
1204 | a8dea12f | j_mayer | if (ret >= 0) { |
1205 | a8dea12f | j_mayer | ctx->raddr = raddr; |
1206 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1207 | 4a057712 | j_mayer | if (loglevel != 0) { |
1208 | a8dea12f | j_mayer | fprintf(logfile, "%s: access granted " ADDRX " => " REGX |
1209 | c55e9aef | j_mayer | " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1210 | c55e9aef | j_mayer | ret); |
1211 | a8dea12f | j_mayer | } |
1212 | daf4f96e | j_mayer | #endif
|
1213 | c55e9aef | j_mayer | return 0; |
1214 | a8dea12f | j_mayer | } |
1215 | a8dea12f | j_mayer | } |
1216 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1217 | 4a057712 | j_mayer | if (loglevel != 0) { |
1218 | c55e9aef | j_mayer | fprintf(logfile, "%s: access refused " ADDRX " => " REGX |
1219 | c55e9aef | j_mayer | " %d %d\n", __func__, address, raddr, ctx->prot,
|
1220 | c55e9aef | j_mayer | ret); |
1221 | c55e9aef | j_mayer | } |
1222 | daf4f96e | j_mayer | #endif
|
1223 | 3b46e624 | ths | |
1224 | a8dea12f | j_mayer | return ret;
|
1225 | a8dea12f | j_mayer | } |
1226 | a8dea12f | j_mayer | |
1227 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1228 | c294fc58 | j_mayer | { |
1229 | c294fc58 | j_mayer | /* XXX: TO BE FIXED */
|
1230 | c294fc58 | j_mayer | if (val != 0x00000000) { |
1231 | c294fc58 | j_mayer | cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1232 | c294fc58 | j_mayer | } |
1233 | c294fc58 | j_mayer | env->spr[SPR_405_SLER] = val; |
1234 | c294fc58 | j_mayer | } |
1235 | c294fc58 | j_mayer | |
1236 | 5eb7995e | j_mayer | int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1237 | 5eb7995e | j_mayer | target_ulong address, int rw,
|
1238 | 5eb7995e | j_mayer | int access_type)
|
1239 | 5eb7995e | j_mayer | { |
1240 | 5eb7995e | j_mayer | ppcemb_tlb_t *tlb; |
1241 | 5eb7995e | j_mayer | target_phys_addr_t raddr; |
1242 | 5eb7995e | j_mayer | int i, prot, ret;
|
1243 | 5eb7995e | j_mayer | |
1244 | 5eb7995e | j_mayer | ret = -1;
|
1245 | 5eb7995e | j_mayer | raddr = -1;
|
1246 | 5eb7995e | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1247 | 5eb7995e | j_mayer | tlb = &env->tlb[i].tlbe; |
1248 | 5eb7995e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1249 | 5eb7995e | j_mayer | env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1250 | 5eb7995e | j_mayer | continue;
|
1251 | 5eb7995e | j_mayer | if (msr_pr)
|
1252 | 5eb7995e | j_mayer | prot = tlb->prot & 0xF;
|
1253 | 5eb7995e | j_mayer | else
|
1254 | 5eb7995e | j_mayer | prot = (tlb->prot >> 4) & 0xF; |
1255 | 5eb7995e | j_mayer | /* Check the address space */
|
1256 | 5eb7995e | j_mayer | if (access_type == ACCESS_CODE) {
|
1257 | d26bfc9a | j_mayer | if (msr_ir != (tlb->attr & 1)) |
1258 | 5eb7995e | j_mayer | continue;
|
1259 | 5eb7995e | j_mayer | ctx->prot = prot; |
1260 | 5eb7995e | j_mayer | if (prot & PAGE_EXEC) {
|
1261 | 5eb7995e | j_mayer | ret = 0;
|
1262 | 5eb7995e | j_mayer | break;
|
1263 | 5eb7995e | j_mayer | } |
1264 | 5eb7995e | j_mayer | ret = -3;
|
1265 | 5eb7995e | j_mayer | } else {
|
1266 | d26bfc9a | j_mayer | if (msr_dr != (tlb->attr & 1)) |
1267 | 5eb7995e | j_mayer | continue;
|
1268 | 5eb7995e | j_mayer | ctx->prot = prot; |
1269 | 5eb7995e | j_mayer | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1270 | 5eb7995e | j_mayer | ret = 0;
|
1271 | 5eb7995e | j_mayer | break;
|
1272 | 5eb7995e | j_mayer | } |
1273 | 5eb7995e | j_mayer | ret = -2;
|
1274 | 5eb7995e | j_mayer | } |
1275 | 5eb7995e | j_mayer | } |
1276 | 5eb7995e | j_mayer | if (ret >= 0) |
1277 | 5eb7995e | j_mayer | ctx->raddr = raddr; |
1278 | 5eb7995e | j_mayer | |
1279 | 5eb7995e | j_mayer | return ret;
|
1280 | 5eb7995e | j_mayer | } |
1281 | 5eb7995e | j_mayer | |
1282 | 76a66253 | j_mayer | static int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1283 | 76a66253 | j_mayer | target_ulong eaddr, int rw)
|
1284 | 76a66253 | j_mayer | { |
1285 | 76a66253 | j_mayer | int in_plb, ret;
|
1286 | 3b46e624 | ths | |
1287 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1288 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
1289 | 76a66253 | j_mayer | ret = 0;
|
1290 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1291 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1292 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1293 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1294 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1295 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1296 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1297 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1298 | caa4039c | j_mayer | break;
|
1299 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
1300 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1301 | caa4039c | j_mayer | /* Real address are 60 bits long */
|
1302 | a750fc0b | j_mayer | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1303 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1304 | caa4039c | j_mayer | break;
|
1305 | 9706285b | j_mayer | #endif
|
1306 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1307 | caa4039c | j_mayer | if (unlikely(msr_pe != 0)) { |
1308 | caa4039c | j_mayer | /* 403 family add some particular protections,
|
1309 | caa4039c | j_mayer | * using PBL/PBU registers for accesses with no translation.
|
1310 | caa4039c | j_mayer | */
|
1311 | caa4039c | j_mayer | in_plb = |
1312 | caa4039c | j_mayer | /* Check PLB validity */
|
1313 | caa4039c | j_mayer | (env->pb[0] < env->pb[1] && |
1314 | caa4039c | j_mayer | /* and address in plb area */
|
1315 | caa4039c | j_mayer | eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1316 | caa4039c | j_mayer | (env->pb[2] < env->pb[3] && |
1317 | caa4039c | j_mayer | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1318 | caa4039c | j_mayer | if (in_plb ^ msr_px) {
|
1319 | caa4039c | j_mayer | /* Access in protected area */
|
1320 | caa4039c | j_mayer | if (rw == 1) { |
1321 | caa4039c | j_mayer | /* Access is not allowed */
|
1322 | caa4039c | j_mayer | ret = -2;
|
1323 | caa4039c | j_mayer | } |
1324 | caa4039c | j_mayer | } else {
|
1325 | caa4039c | j_mayer | /* Read-write access is allowed */
|
1326 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1327 | 76a66253 | j_mayer | } |
1328 | 76a66253 | j_mayer | } |
1329 | e1833e1f | j_mayer | break;
|
1330 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1331 | caa4039c | j_mayer | /* XXX: TODO */
|
1332 | caa4039c | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1333 | caa4039c | j_mayer | break;
|
1334 | caa4039c | j_mayer | default:
|
1335 | caa4039c | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1336 | caa4039c | j_mayer | return -1; |
1337 | 76a66253 | j_mayer | } |
1338 | 76a66253 | j_mayer | |
1339 | 76a66253 | j_mayer | return ret;
|
1340 | 76a66253 | j_mayer | } |
1341 | 76a66253 | j_mayer | |
1342 | 76a66253 | j_mayer | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1343 | 76a66253 | j_mayer | int rw, int access_type, int check_BATs) |
1344 | 9a64fbe4 | bellard | { |
1345 | 9a64fbe4 | bellard | int ret;
|
1346 | 514fb8c1 | bellard | #if 0
|
1347 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1348 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
1349 | 9a64fbe4 | bellard | }
|
1350 | d9bce9d9 | j_mayer | #endif
|
1351 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1352 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
1353 | 9a64fbe4 | bellard | /* No address translation */
|
1354 | 76a66253 | j_mayer | ret = check_physical(env, ctx, eaddr, rw); |
1355 | 9a64fbe4 | bellard | } else {
|
1356 | c55e9aef | j_mayer | ret = -1;
|
1357 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1358 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1359 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1360 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1361 | a8dea12f | j_mayer | /* Try to find a BAT */
|
1362 | a8dea12f | j_mayer | if (check_BATs)
|
1363 | a8dea12f | j_mayer | ret = get_bat(env, ctx, eaddr, rw, access_type); |
1364 | c55e9aef | j_mayer | /* No break here */
|
1365 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1366 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1367 | c55e9aef | j_mayer | #endif
|
1368 | a8dea12f | j_mayer | if (ret < 0) { |
1369 | c55e9aef | j_mayer | /* We didn't match any BAT entry or don't have BATs */
|
1370 | a8dea12f | j_mayer | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1371 | a8dea12f | j_mayer | } |
1372 | a8dea12f | j_mayer | break;
|
1373 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1374 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1375 | 36081602 | j_mayer | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1376 | a8dea12f | j_mayer | rw, access_type); |
1377 | a8dea12f | j_mayer | break;
|
1378 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1379 | 5eb7995e | j_mayer | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1380 | 5eb7995e | j_mayer | rw, access_type); |
1381 | 5eb7995e | j_mayer | break;
|
1382 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1383 | c55e9aef | j_mayer | /* XXX: TODO */
|
1384 | c55e9aef | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1385 | c55e9aef | j_mayer | return -1; |
1386 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1387 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 does not do any translation\n");
|
1388 | 2662a059 | j_mayer | return -1; |
1389 | c55e9aef | j_mayer | default:
|
1390 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1391 | a8dea12f | j_mayer | return -1; |
1392 | 9a64fbe4 | bellard | } |
1393 | 9a64fbe4 | bellard | } |
1394 | 514fb8c1 | bellard | #if 0
|
1395 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1396 | 4a057712 | j_mayer | fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
1397 | c55e9aef | j_mayer | __func__, eaddr, ret, ctx->raddr);
|
1398 | a541f297 | bellard | }
|
1399 | 76a66253 | j_mayer | #endif
|
1400 | d9bce9d9 | j_mayer | |
1401 | 9a64fbe4 | bellard | return ret;
|
1402 | 9a64fbe4 | bellard | } |
1403 | 9a64fbe4 | bellard | |
1404 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1405 | a6b025d3 | bellard | { |
1406 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1407 | a6b025d3 | bellard | |
1408 | 76a66253 | j_mayer | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0)) |
1409 | a6b025d3 | bellard | return -1; |
1410 | 76a66253 | j_mayer | |
1411 | 76a66253 | j_mayer | return ctx.raddr & TARGET_PAGE_MASK;
|
1412 | a6b025d3 | bellard | } |
1413 | 9a64fbe4 | bellard | |
1414 | 9a64fbe4 | bellard | /* Perform address translation */
|
1415 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1416 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
1417 | 9a64fbe4 | bellard | { |
1418 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1419 | a541f297 | bellard | int access_type;
|
1420 | 9a64fbe4 | bellard | int ret = 0; |
1421 | d9bce9d9 | j_mayer | |
1422 | b769d8fe | bellard | if (rw == 2) { |
1423 | b769d8fe | bellard | /* code access */
|
1424 | b769d8fe | bellard | rw = 0;
|
1425 | b769d8fe | bellard | access_type = ACCESS_CODE; |
1426 | b769d8fe | bellard | } else {
|
1427 | b769d8fe | bellard | /* data access */
|
1428 | b769d8fe | bellard | /* XXX: put correct access by using cpu_restore_state()
|
1429 | b769d8fe | bellard | correctly */
|
1430 | b769d8fe | bellard | access_type = ACCESS_INT; |
1431 | b769d8fe | bellard | // access_type = env->access_type;
|
1432 | b769d8fe | bellard | } |
1433 | 76a66253 | j_mayer | ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
|
1434 | 9a64fbe4 | bellard | if (ret == 0) { |
1435 | b227a8e9 | j_mayer | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1436 | b227a8e9 | j_mayer | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1437 | b227a8e9 | j_mayer | mmu_idx, is_softmmu); |
1438 | 9a64fbe4 | bellard | } else if (ret < 0) { |
1439 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1440 | 4a057712 | j_mayer | if (loglevel != 0) |
1441 | 76a66253 | j_mayer | cpu_dump_state(env, logfile, fprintf, 0);
|
1442 | 9a64fbe4 | bellard | #endif
|
1443 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
1444 | 9a64fbe4 | bellard | switch (ret) {
|
1445 | 9a64fbe4 | bellard | case -1: |
1446 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1447 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1448 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1449 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1450 | 8f793433 | j_mayer | env->error_code = 1 << 18; |
1451 | 76a66253 | j_mayer | env->spr[SPR_IMISS] = address; |
1452 | 76a66253 | j_mayer | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1453 | 76a66253 | j_mayer | goto tlb_miss;
|
1454 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1455 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1456 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
1457 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1458 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1459 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ITLB; |
1460 | 8f793433 | j_mayer | env->error_code = 0;
|
1461 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1462 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1463 | c55e9aef | j_mayer | break;
|
1464 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1465 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1466 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1467 | c55e9aef | j_mayer | #endif
|
1468 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1469 | 8f793433 | j_mayer | env->error_code = 0x40000000;
|
1470 | 8f793433 | j_mayer | break;
|
1471 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1472 | c55e9aef | j_mayer | /* XXX: TODO */
|
1473 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1474 | c55e9aef | j_mayer | return -1; |
1475 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1476 | c55e9aef | j_mayer | /* XXX: TODO */
|
1477 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1478 | c55e9aef | j_mayer | return -1; |
1479 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1480 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1481 | 2662a059 | j_mayer | "exceptions\n");
|
1482 | 2662a059 | j_mayer | return -1; |
1483 | c55e9aef | j_mayer | default:
|
1484 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1485 | c55e9aef | j_mayer | return -1; |
1486 | 76a66253 | j_mayer | } |
1487 | 9a64fbe4 | bellard | break;
|
1488 | 9a64fbe4 | bellard | case -2: |
1489 | 9a64fbe4 | bellard | /* Access rights violation */
|
1490 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1491 | 8f793433 | j_mayer | env->error_code = 0x08000000;
|
1492 | 9a64fbe4 | bellard | break;
|
1493 | 9a64fbe4 | bellard | case -3: |
1494 | 76a66253 | j_mayer | /* No execute protection violation */
|
1495 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1496 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1497 | 9a64fbe4 | bellard | break;
|
1498 | 9a64fbe4 | bellard | case -4: |
1499 | 9a64fbe4 | bellard | /* Direct store exception */
|
1500 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1501 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1502 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1503 | 2be0071f | bellard | break;
|
1504 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1505 | 2be0071f | bellard | case -5: |
1506 | 2be0071f | bellard | /* No match in segment table */
|
1507 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISEG; |
1508 | 8f793433 | j_mayer | env->error_code = 0;
|
1509 | 9a64fbe4 | bellard | break;
|
1510 | e1833e1f | j_mayer | #endif
|
1511 | 9a64fbe4 | bellard | } |
1512 | 9a64fbe4 | bellard | } else {
|
1513 | 9a64fbe4 | bellard | switch (ret) {
|
1514 | 9a64fbe4 | bellard | case -1: |
1515 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1516 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1517 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1518 | 76a66253 | j_mayer | if (rw == 1) { |
1519 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1520 | 8f793433 | j_mayer | env->error_code = 1 << 16; |
1521 | 76a66253 | j_mayer | } else {
|
1522 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1523 | 8f793433 | j_mayer | env->error_code = 0;
|
1524 | 76a66253 | j_mayer | } |
1525 | 76a66253 | j_mayer | env->spr[SPR_DMISS] = address; |
1526 | 76a66253 | j_mayer | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1527 | 76a66253 | j_mayer | tlb_miss:
|
1528 | 8f793433 | j_mayer | env->error_code |= ctx.key << 19;
|
1529 | 76a66253 | j_mayer | env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1530 | 76a66253 | j_mayer | env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1531 | 8f793433 | j_mayer | break;
|
1532 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1533 | 7dbe11ac | j_mayer | if (rw == 1) { |
1534 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1535 | 7dbe11ac | j_mayer | } else {
|
1536 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1537 | 7dbe11ac | j_mayer | } |
1538 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
1539 | 7dbe11ac | j_mayer | /* Implement LRU algorithm */
|
1540 | 8f793433 | j_mayer | env->error_code = ctx.key << 19;
|
1541 | 7dbe11ac | j_mayer | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
|
1542 | 7dbe11ac | j_mayer | ((env->last_way + 1) & (env->nb_ways - 1)); |
1543 | 7dbe11ac | j_mayer | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
|
1544 | 7dbe11ac | j_mayer | break;
|
1545 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1546 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1547 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DTLB; |
1548 | 8f793433 | j_mayer | env->error_code = 0;
|
1549 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1550 | a8dea12f | j_mayer | if (rw)
|
1551 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00800000;
|
1552 | a8dea12f | j_mayer | else
|
1553 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1554 | c55e9aef | j_mayer | break;
|
1555 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1556 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1557 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1558 | c55e9aef | j_mayer | #endif
|
1559 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1560 | 8f793433 | j_mayer | env->error_code = 0;
|
1561 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1562 | 8f793433 | j_mayer | if (rw == 1) |
1563 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1564 | 8f793433 | j_mayer | else
|
1565 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1566 | 8f793433 | j_mayer | break;
|
1567 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1568 | c55e9aef | j_mayer | /* XXX: TODO */
|
1569 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1570 | c55e9aef | j_mayer | return -1; |
1571 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1572 | c55e9aef | j_mayer | /* XXX: TODO */
|
1573 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1574 | c55e9aef | j_mayer | return -1; |
1575 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1576 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1577 | 2662a059 | j_mayer | "exceptions\n");
|
1578 | 2662a059 | j_mayer | return -1; |
1579 | c55e9aef | j_mayer | default:
|
1580 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1581 | c55e9aef | j_mayer | return -1; |
1582 | 76a66253 | j_mayer | } |
1583 | 9a64fbe4 | bellard | break;
|
1584 | 9a64fbe4 | bellard | case -2: |
1585 | 9a64fbe4 | bellard | /* Access rights violation */
|
1586 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1587 | 8f793433 | j_mayer | env->error_code = 0;
|
1588 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1589 | 8f793433 | j_mayer | if (rw == 1) |
1590 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x0A000000;
|
1591 | 8f793433 | j_mayer | else
|
1592 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x08000000;
|
1593 | 9a64fbe4 | bellard | break;
|
1594 | 9a64fbe4 | bellard | case -4: |
1595 | 9a64fbe4 | bellard | /* Direct store exception */
|
1596 | 9a64fbe4 | bellard | switch (access_type) {
|
1597 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1598 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1599 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ALIGN; |
1600 | 8f793433 | j_mayer | env->error_code = POWERPC_EXCP_ALIGN_FP; |
1601 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1602 | 9a64fbe4 | bellard | break;
|
1603 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1604 | 8f793433 | j_mayer | /* lwarx, ldarx or stwcx. */
|
1605 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1606 | 8f793433 | j_mayer | env->error_code = 0;
|
1607 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1608 | 8f793433 | j_mayer | if (rw == 1) |
1609 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06000000;
|
1610 | 8f793433 | j_mayer | else
|
1611 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04000000;
|
1612 | 9a64fbe4 | bellard | break;
|
1613 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1614 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1615 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1616 | 8f793433 | j_mayer | env->error_code = 0;
|
1617 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1618 | 8f793433 | j_mayer | if (rw == 1) |
1619 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06100000;
|
1620 | 8f793433 | j_mayer | else
|
1621 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04100000;
|
1622 | 9a64fbe4 | bellard | break;
|
1623 | 9a64fbe4 | bellard | default:
|
1624 | 76a66253 | j_mayer | printf("DSI: invalid exception (%d)\n", ret);
|
1625 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_PROGRAM; |
1626 | 8f793433 | j_mayer | env->error_code = |
1627 | 8f793433 | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
1628 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1629 | 9a64fbe4 | bellard | break;
|
1630 | 9a64fbe4 | bellard | } |
1631 | fdabc366 | bellard | break;
|
1632 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1633 | 2be0071f | bellard | case -5: |
1634 | 2be0071f | bellard | /* No match in segment table */
|
1635 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSEG; |
1636 | 8f793433 | j_mayer | env->error_code = 0;
|
1637 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1638 | 2be0071f | bellard | break;
|
1639 | e1833e1f | j_mayer | #endif
|
1640 | 9a64fbe4 | bellard | } |
1641 | 9a64fbe4 | bellard | } |
1642 | 9a64fbe4 | bellard | #if 0
|
1643 | 8f793433 | j_mayer | printf("%s: set exception to %d %02x\n", __func__,
|
1644 | 8f793433 | j_mayer | env->exception, env->error_code);
|
1645 | 9a64fbe4 | bellard | #endif
|
1646 | 9a64fbe4 | bellard | ret = 1;
|
1647 | 9a64fbe4 | bellard | } |
1648 | 76a66253 | j_mayer | |
1649 | 9a64fbe4 | bellard | return ret;
|
1650 | 9a64fbe4 | bellard | } |
1651 | 9a64fbe4 | bellard | |
1652 | 3fc6c082 | bellard | /*****************************************************************************/
|
1653 | 3fc6c082 | bellard | /* BATs management */
|
1654 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1655 | b068d6a7 | j_mayer | static always_inline void do_invalidate_BAT (CPUPPCState *env, |
1656 | b068d6a7 | j_mayer | target_ulong BATu, |
1657 | b068d6a7 | j_mayer | target_ulong mask) |
1658 | 3fc6c082 | bellard | { |
1659 | 3fc6c082 | bellard | target_ulong base, end, page; |
1660 | 76a66253 | j_mayer | |
1661 | 3fc6c082 | bellard | base = BATu & ~0x0001FFFF;
|
1662 | 3fc6c082 | bellard | end = base + mask + 0x00020000;
|
1663 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1664 | 76a66253 | j_mayer | if (loglevel != 0) { |
1665 | 1b9eb036 | j_mayer | fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
1666 | 76a66253 | j_mayer | base, end, mask); |
1667 | 76a66253 | j_mayer | } |
1668 | 3fc6c082 | bellard | #endif
|
1669 | 3fc6c082 | bellard | for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1670 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1671 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1672 | 3fc6c082 | bellard | if (loglevel != 0) |
1673 | 3fc6c082 | bellard | fprintf(logfile, "Flush done\n");
|
1674 | 3fc6c082 | bellard | #endif
|
1675 | 3fc6c082 | bellard | } |
1676 | 3fc6c082 | bellard | #endif
|
1677 | 3fc6c082 | bellard | |
1678 | b068d6a7 | j_mayer | static always_inline void dump_store_bat (CPUPPCState *env, char ID, |
1679 | b068d6a7 | j_mayer | int ul, int nr, target_ulong value) |
1680 | 3fc6c082 | bellard | { |
1681 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1682 | 3fc6c082 | bellard | if (loglevel != 0) { |
1683 | 1b9eb036 | j_mayer | fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n", |
1684 | 1b9eb036 | j_mayer | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1685 | 3fc6c082 | bellard | } |
1686 | 3fc6c082 | bellard | #endif
|
1687 | 3fc6c082 | bellard | } |
1688 | 3fc6c082 | bellard | |
1689 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr)
|
1690 | 3fc6c082 | bellard | { |
1691 | 3fc6c082 | bellard | return env->IBAT[0][nr]; |
1692 | 3fc6c082 | bellard | } |
1693 | 3fc6c082 | bellard | |
1694 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr)
|
1695 | 3fc6c082 | bellard | { |
1696 | 3fc6c082 | bellard | return env->IBAT[1][nr]; |
1697 | 3fc6c082 | bellard | } |
1698 | 3fc6c082 | bellard | |
1699 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1700 | 3fc6c082 | bellard | { |
1701 | 3fc6c082 | bellard | target_ulong mask; |
1702 | 3fc6c082 | bellard | |
1703 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 0, nr, value); |
1704 | 3fc6c082 | bellard | if (env->IBAT[0][nr] != value) { |
1705 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1706 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1707 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1708 | 3fc6c082 | bellard | #endif
|
1709 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1710 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1711 | 3fc6c082 | bellard | */
|
1712 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1713 | 3fc6c082 | bellard | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1714 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1715 | 3fc6c082 | bellard | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1716 | 3fc6c082 | bellard | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1717 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1718 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1719 | 76a66253 | j_mayer | #else
|
1720 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1721 | 3fc6c082 | bellard | #endif
|
1722 | 3fc6c082 | bellard | } |
1723 | 3fc6c082 | bellard | } |
1724 | 3fc6c082 | bellard | |
1725 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1726 | 3fc6c082 | bellard | { |
1727 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 1, nr, value); |
1728 | 3fc6c082 | bellard | env->IBAT[1][nr] = value;
|
1729 | 3fc6c082 | bellard | } |
1730 | 3fc6c082 | bellard | |
1731 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr)
|
1732 | 3fc6c082 | bellard | { |
1733 | 3fc6c082 | bellard | return env->DBAT[0][nr]; |
1734 | 3fc6c082 | bellard | } |
1735 | 3fc6c082 | bellard | |
1736 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr)
|
1737 | 3fc6c082 | bellard | { |
1738 | 3fc6c082 | bellard | return env->DBAT[1][nr]; |
1739 | 3fc6c082 | bellard | } |
1740 | 3fc6c082 | bellard | |
1741 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1742 | 3fc6c082 | bellard | { |
1743 | 3fc6c082 | bellard | target_ulong mask; |
1744 | 3fc6c082 | bellard | |
1745 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 0, nr, value); |
1746 | 3fc6c082 | bellard | if (env->DBAT[0][nr] != value) { |
1747 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1748 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1749 | 3fc6c082 | bellard | */
|
1750 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1751 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1752 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1753 | 3fc6c082 | bellard | #endif
|
1754 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1755 | 3fc6c082 | bellard | env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1756 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1757 | 3fc6c082 | bellard | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1758 | 3fc6c082 | bellard | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1759 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1760 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1761 | 3fc6c082 | bellard | #else
|
1762 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1763 | 3fc6c082 | bellard | #endif
|
1764 | 3fc6c082 | bellard | } |
1765 | 3fc6c082 | bellard | } |
1766 | 3fc6c082 | bellard | |
1767 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1768 | 3fc6c082 | bellard | { |
1769 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 1, nr, value); |
1770 | 3fc6c082 | bellard | env->DBAT[1][nr] = value;
|
1771 | 3fc6c082 | bellard | } |
1772 | 3fc6c082 | bellard | |
1773 | 0a032cbe | j_mayer | /*****************************************************************************/
|
1774 | 0a032cbe | j_mayer | /* TLB management */
|
1775 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1776 | 0a032cbe | j_mayer | { |
1777 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1778 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1779 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1780 | 0a032cbe | j_mayer | ppc6xx_tlb_invalidate_all(env); |
1781 | daf4f96e | j_mayer | break;
|
1782 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1783 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1784 | 0a032cbe | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1785 | daf4f96e | j_mayer | break;
|
1786 | 7dbe11ac | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1787 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1788 | 7dbe11ac | j_mayer | break;
|
1789 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1790 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1791 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1792 | 7dbe11ac | j_mayer | break;
|
1793 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1794 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1795 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1796 | 7dbe11ac | j_mayer | break;
|
1797 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1798 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1799 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1800 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1801 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
1802 | daf4f96e | j_mayer | break;
|
1803 | 00af685f | j_mayer | default:
|
1804 | 00af685f | j_mayer | /* XXX: TODO */
|
1805 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1806 | 00af685f | j_mayer | break;
|
1807 | 0a032cbe | j_mayer | } |
1808 | 0a032cbe | j_mayer | } |
1809 | 0a032cbe | j_mayer | |
1810 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
1811 | daf4f96e | j_mayer | { |
1812 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1813 | daf4f96e | j_mayer | addr &= TARGET_PAGE_MASK; |
1814 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1815 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1816 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1817 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
1818 | daf4f96e | j_mayer | if (env->id_tlbs == 1) |
1819 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
1820 | daf4f96e | j_mayer | break;
|
1821 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1822 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1823 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); |
1824 | daf4f96e | j_mayer | break;
|
1825 | 7dbe11ac | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1826 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1827 | 7dbe11ac | j_mayer | break;
|
1828 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1829 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1830 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1831 | 7dbe11ac | j_mayer | break;
|
1832 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1833 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1834 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1835 | 7dbe11ac | j_mayer | break;
|
1836 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1837 | daf4f96e | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1838 | daf4f96e | j_mayer | addr &= ~((target_ulong)-1 << 28); |
1839 | daf4f96e | j_mayer | /* XXX: this case should be optimized,
|
1840 | daf4f96e | j_mayer | * giving a mask to tlb_flush_page
|
1841 | daf4f96e | j_mayer | */
|
1842 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x0 << 28)); |
1843 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x1 << 28)); |
1844 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x2 << 28)); |
1845 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x3 << 28)); |
1846 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x4 << 28)); |
1847 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x5 << 28)); |
1848 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x6 << 28)); |
1849 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x7 << 28)); |
1850 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x8 << 28)); |
1851 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x9 << 28)); |
1852 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xA << 28)); |
1853 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xB << 28)); |
1854 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xC << 28)); |
1855 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xD << 28)); |
1856 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xE << 28)); |
1857 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xF << 28)); |
1858 | 7dbe11ac | j_mayer | break;
|
1859 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1860 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1861 | 7dbe11ac | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1862 | 7dbe11ac | j_mayer | /* XXX: given the fact that there are too many segments to invalidate,
|
1863 | 00af685f | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
|
1864 | 7dbe11ac | j_mayer | * we just invalidate all TLBs
|
1865 | 7dbe11ac | j_mayer | */
|
1866 | 7dbe11ac | j_mayer | tlb_flush(env, 1);
|
1867 | 7dbe11ac | j_mayer | break;
|
1868 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1869 | 00af685f | j_mayer | default:
|
1870 | 00af685f | j_mayer | /* XXX: TODO */
|
1871 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1872 | 00af685f | j_mayer | break;
|
1873 | daf4f96e | j_mayer | } |
1874 | daf4f96e | j_mayer | #else
|
1875 | daf4f96e | j_mayer | ppc_tlb_invalidate_all(env); |
1876 | daf4f96e | j_mayer | #endif
|
1877 | daf4f96e | j_mayer | } |
1878 | daf4f96e | j_mayer | |
1879 | 3fc6c082 | bellard | /*****************************************************************************/
|
1880 | 3fc6c082 | bellard | /* Special registers manipulation */
|
1881 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1882 | d9bce9d9 | j_mayer | target_ulong ppc_load_asr (CPUPPCState *env) |
1883 | d9bce9d9 | j_mayer | { |
1884 | d9bce9d9 | j_mayer | return env->asr;
|
1885 | d9bce9d9 | j_mayer | } |
1886 | d9bce9d9 | j_mayer | |
1887 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
1888 | d9bce9d9 | j_mayer | { |
1889 | d9bce9d9 | j_mayer | if (env->asr != value) {
|
1890 | d9bce9d9 | j_mayer | env->asr = value; |
1891 | d9bce9d9 | j_mayer | tlb_flush(env, 1);
|
1892 | d9bce9d9 | j_mayer | } |
1893 | d9bce9d9 | j_mayer | } |
1894 | d9bce9d9 | j_mayer | #endif
|
1895 | d9bce9d9 | j_mayer | |
1896 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env) |
1897 | 3fc6c082 | bellard | { |
1898 | 3fc6c082 | bellard | return env->sdr1;
|
1899 | 3fc6c082 | bellard | } |
1900 | 3fc6c082 | bellard | |
1901 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1902 | 3fc6c082 | bellard | { |
1903 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
1904 | 3fc6c082 | bellard | if (loglevel != 0) { |
1905 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value); |
1906 | 3fc6c082 | bellard | } |
1907 | 3fc6c082 | bellard | #endif
|
1908 | 3fc6c082 | bellard | if (env->sdr1 != value) {
|
1909 | 12de9a39 | j_mayer | /* XXX: for PowerPC 64, should check that the HTABSIZE value
|
1910 | 12de9a39 | j_mayer | * is <= 28
|
1911 | 12de9a39 | j_mayer | */
|
1912 | 3fc6c082 | bellard | env->sdr1 = value; |
1913 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1914 | 3fc6c082 | bellard | } |
1915 | 3fc6c082 | bellard | } |
1916 | 3fc6c082 | bellard | |
1917 | 12de9a39 | j_mayer | #if 0 // Unused
|
1918 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum)
|
1919 | 3fc6c082 | bellard | {
|
1920 | 3fc6c082 | bellard | return env->sr[srnum];
|
1921 | 3fc6c082 | bellard | }
|
1922 | 12de9a39 | j_mayer | #endif
|
1923 | 3fc6c082 | bellard | |
1924 | 3fc6c082 | bellard | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1925 | 3fc6c082 | bellard | { |
1926 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
1927 | 3fc6c082 | bellard | if (loglevel != 0) { |
1928 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n", |
1929 | 1b9eb036 | j_mayer | __func__, srnum, value, env->sr[srnum]); |
1930 | 3fc6c082 | bellard | } |
1931 | 3fc6c082 | bellard | #endif
|
1932 | 3fc6c082 | bellard | if (env->sr[srnum] != value) {
|
1933 | 3fc6c082 | bellard | env->sr[srnum] = value; |
1934 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS) && 0 |
1935 | 3fc6c082 | bellard | { |
1936 | 3fc6c082 | bellard | target_ulong page, end; |
1937 | 3fc6c082 | bellard | /* Invalidate 256 MB of virtual memory */
|
1938 | 3fc6c082 | bellard | page = (16 << 20) * srnum; |
1939 | 3fc6c082 | bellard | end = page + (16 << 20); |
1940 | 3fc6c082 | bellard | for (; page != end; page += TARGET_PAGE_SIZE)
|
1941 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1942 | 3fc6c082 | bellard | } |
1943 | 3fc6c082 | bellard | #else
|
1944 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1945 | 3fc6c082 | bellard | #endif
|
1946 | 3fc6c082 | bellard | } |
1947 | 3fc6c082 | bellard | } |
1948 | 76a66253 | j_mayer | #endif /* !defined (CONFIG_USER_ONLY) */ |
1949 | 3fc6c082 | bellard | |
1950 | bfa1e5cf | j_mayer | target_ulong ppc_load_xer (CPUPPCState *env) |
1951 | 79aceca5 | bellard | { |
1952 | 79aceca5 | bellard | return (xer_so << XER_SO) |
|
1953 | 79aceca5 | bellard | (xer_ov << XER_OV) | |
1954 | 79aceca5 | bellard | (xer_ca << XER_CA) | |
1955 | 3fc6c082 | bellard | (xer_bc << XER_BC) | |
1956 | 3fc6c082 | bellard | (xer_cmp << XER_CMP); |
1957 | 79aceca5 | bellard | } |
1958 | 79aceca5 | bellard | |
1959 | bfa1e5cf | j_mayer | void ppc_store_xer (CPUPPCState *env, target_ulong value)
|
1960 | 79aceca5 | bellard | { |
1961 | 79aceca5 | bellard | xer_so = (value >> XER_SO) & 0x01;
|
1962 | 79aceca5 | bellard | xer_ov = (value >> XER_OV) & 0x01;
|
1963 | 79aceca5 | bellard | xer_ca = (value >> XER_CA) & 0x01;
|
1964 | 3fc6c082 | bellard | xer_cmp = (value >> XER_CMP) & 0xFF;
|
1965 | d9bce9d9 | j_mayer | xer_bc = (value >> XER_BC) & 0x7F;
|
1966 | 79aceca5 | bellard | } |
1967 | 79aceca5 | bellard | |
1968 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
1969 | b068d6a7 | j_mayer | static always_inline void swap_gpr_tgpr (CPUPPCState *env) |
1970 | 79aceca5 | bellard | { |
1971 | 76a66253 | j_mayer | ppc_gpr_t tmp; |
1972 | 76a66253 | j_mayer | |
1973 | 76a66253 | j_mayer | tmp = env->gpr[0];
|
1974 | 76a66253 | j_mayer | env->gpr[0] = env->tgpr[0]; |
1975 | 76a66253 | j_mayer | env->tgpr[0] = tmp;
|
1976 | 76a66253 | j_mayer | tmp = env->gpr[1];
|
1977 | 76a66253 | j_mayer | env->gpr[1] = env->tgpr[1]; |
1978 | 76a66253 | j_mayer | env->tgpr[1] = tmp;
|
1979 | 76a66253 | j_mayer | tmp = env->gpr[2];
|
1980 | 76a66253 | j_mayer | env->gpr[2] = env->tgpr[2]; |
1981 | 76a66253 | j_mayer | env->tgpr[2] = tmp;
|
1982 | 76a66253 | j_mayer | tmp = env->gpr[3];
|
1983 | 76a66253 | j_mayer | env->gpr[3] = env->tgpr[3]; |
1984 | 76a66253 | j_mayer | env->tgpr[3] = tmp;
|
1985 | 79aceca5 | bellard | } |
1986 | 79aceca5 | bellard | |
1987 | 76a66253 | j_mayer | /* GDBstub can read and write MSR... */
|
1988 | 76a66253 | j_mayer | target_ulong do_load_msr (CPUPPCState *env) |
1989 | 79aceca5 | bellard | { |
1990 | 76a66253 | j_mayer | return
|
1991 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
|
1992 | d9bce9d9 | j_mayer | ((target_ulong)msr_sf << MSR_SF) | |
1993 | d9bce9d9 | j_mayer | ((target_ulong)msr_isf << MSR_ISF) | |
1994 | d9bce9d9 | j_mayer | ((target_ulong)msr_hv << MSR_HV) | |
1995 | 76a66253 | j_mayer | #endif
|
1996 | d9bce9d9 | j_mayer | ((target_ulong)msr_ucle << MSR_UCLE) | |
1997 | d9bce9d9 | j_mayer | ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
|
1998 | d9bce9d9 | j_mayer | ((target_ulong)msr_ap << MSR_AP) | |
1999 | d9bce9d9 | j_mayer | ((target_ulong)msr_sa << MSR_SA) | |
2000 | d9bce9d9 | j_mayer | ((target_ulong)msr_key << MSR_KEY) | |
2001 | 25ba3a68 | j_mayer | ((target_ulong)msr_pow << MSR_POW) | |
2002 | d26bfc9a | j_mayer | ((target_ulong)msr_tgpr << MSR_TGPR) | /* TGPR / CE */
|
2003 | d9bce9d9 | j_mayer | ((target_ulong)msr_ile << MSR_ILE) | |
2004 | d9bce9d9 | j_mayer | ((target_ulong)msr_ee << MSR_EE) | |
2005 | d9bce9d9 | j_mayer | ((target_ulong)msr_pr << MSR_PR) | |
2006 | d9bce9d9 | j_mayer | ((target_ulong)msr_fp << MSR_FP) | |
2007 | d9bce9d9 | j_mayer | ((target_ulong)msr_me << MSR_ME) | |
2008 | d9bce9d9 | j_mayer | ((target_ulong)msr_fe0 << MSR_FE0) | |
2009 | d9bce9d9 | j_mayer | ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
|
2010 | d9bce9d9 | j_mayer | ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
|
2011 | d9bce9d9 | j_mayer | ((target_ulong)msr_fe1 << MSR_FE1) | |
2012 | d9bce9d9 | j_mayer | ((target_ulong)msr_al << MSR_AL) | |
2013 | 25ba3a68 | j_mayer | ((target_ulong)msr_ep << MSR_EP) | |
2014 | 25ba3a68 | j_mayer | ((target_ulong)msr_ir << MSR_IR) | |
2015 | 25ba3a68 | j_mayer | ((target_ulong)msr_dr << MSR_DR) | |
2016 | 25ba3a68 | j_mayer | ((target_ulong)msr_pe << MSR_PE) | |
2017 | d9bce9d9 | j_mayer | ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
|
2018 | d9bce9d9 | j_mayer | ((target_ulong)msr_ri << MSR_RI) | |
2019 | d9bce9d9 | j_mayer | ((target_ulong)msr_le << MSR_LE); |
2020 | 3fc6c082 | bellard | } |
2021 | 3fc6c082 | bellard | |
2022 | a97fed52 | j_mayer | int do_store_msr (CPUPPCState *env, target_ulong value)
|
2023 | 313adae9 | bellard | { |
2024 | 50443c98 | bellard | int enter_pm;
|
2025 | 50443c98 | bellard | |
2026 | 3fc6c082 | bellard | value &= env->msr_mask; |
2027 | 3fc6c082 | bellard | if (((value >> MSR_IR) & 1) != msr_ir || |
2028 | 3fc6c082 | bellard | ((value >> MSR_DR) & 1) != msr_dr) {
|
2029 | 76a66253 | j_mayer | /* Flush all tlb when changing translation mode */
|
2030 | d094807b | bellard | tlb_flush(env, 1);
|
2031 | 3fc6c082 | bellard | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
2032 | a541f297 | bellard | } |
2033 | 4e80effc | j_mayer | #if !defined (CONFIG_USER_ONLY)
|
2034 | d26bfc9a | j_mayer | if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
|
2035 | d26bfc9a | j_mayer | ((value >> MSR_TGPR) & 1) != msr_tgpr)) {
|
2036 | d26bfc9a | j_mayer | /* Swap temporary saved registers with GPRs */
|
2037 | d26bfc9a | j_mayer | swap_gpr_tgpr(env); |
2038 | 76a66253 | j_mayer | } |
2039 | 4e80effc | j_mayer | if (unlikely((value >> MSR_EP) & 1) != msr_ep) { |
2040 | 4e80effc | j_mayer | /* Change the exception prefix on PowerPC 601 */
|
2041 | 4e80effc | j_mayer | env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; |
2042 | 4e80effc | j_mayer | } |
2043 | 4e80effc | j_mayer | #endif
|
2044 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
|
2045 | 76a66253 | j_mayer | msr_sf = (value >> MSR_SF) & 1;
|
2046 | 76a66253 | j_mayer | msr_isf = (value >> MSR_ISF) & 1;
|
2047 | 76a66253 | j_mayer | msr_hv = (value >> MSR_HV) & 1;
|
2048 | 76a66253 | j_mayer | #endif
|
2049 | 76a66253 | j_mayer | msr_ucle = (value >> MSR_UCLE) & 1;
|
2050 | 76a66253 | j_mayer | msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */ |
2051 | 76a66253 | j_mayer | msr_ap = (value >> MSR_AP) & 1;
|
2052 | 76a66253 | j_mayer | msr_sa = (value >> MSR_SA) & 1;
|
2053 | 76a66253 | j_mayer | msr_key = (value >> MSR_KEY) & 1;
|
2054 | 25ba3a68 | j_mayer | msr_pow = (value >> MSR_POW) & 1;
|
2055 | d26bfc9a | j_mayer | msr_tgpr = (value >> MSR_TGPR) & 1; /* TGPR / CE */ |
2056 | 76a66253 | j_mayer | msr_ile = (value >> MSR_ILE) & 1;
|
2057 | 76a66253 | j_mayer | msr_ee = (value >> MSR_EE) & 1;
|
2058 | 76a66253 | j_mayer | msr_pr = (value >> MSR_PR) & 1;
|
2059 | 76a66253 | j_mayer | msr_fp = (value >> MSR_FP) & 1;
|
2060 | 76a66253 | j_mayer | msr_me = (value >> MSR_ME) & 1;
|
2061 | 76a66253 | j_mayer | msr_fe0 = (value >> MSR_FE0) & 1;
|
2062 | 76a66253 | j_mayer | msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */ |
2063 | 76a66253 | j_mayer | msr_be = (value >> MSR_BE) & 1; /* BE / DE */ |
2064 | 76a66253 | j_mayer | msr_fe1 = (value >> MSR_FE1) & 1;
|
2065 | 76a66253 | j_mayer | msr_al = (value >> MSR_AL) & 1;
|
2066 | 25ba3a68 | j_mayer | msr_ep = (value >> MSR_EP) & 1;
|
2067 | 25ba3a68 | j_mayer | msr_ir = (value >> MSR_IR) & 1;
|
2068 | 25ba3a68 | j_mayer | msr_dr = (value >> MSR_DR) & 1;
|
2069 | 25ba3a68 | j_mayer | msr_pe = (value >> MSR_PE) & 1;
|
2070 | 76a66253 | j_mayer | msr_px = (value >> MSR_PX) & 1; /* PX / PMM */ |
2071 | 76a66253 | j_mayer | msr_ri = (value >> MSR_RI) & 1;
|
2072 | 76a66253 | j_mayer | msr_le = (value >> MSR_LE) & 1;
|
2073 | 3fc6c082 | bellard | do_compute_hflags(env); |
2074 | 50443c98 | bellard | |
2075 | 50443c98 | bellard | enter_pm = 0;
|
2076 | a750fc0b | j_mayer | switch (env->excp_model) {
|
2077 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2078 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2079 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2080 | d9bce9d9 | j_mayer | /* Don't handle SLEEP mode: we should disable all clocks...
|
2081 | d9bce9d9 | j_mayer | * No dynamic power-management.
|
2082 | d9bce9d9 | j_mayer | */
|
2083 | d9bce9d9 | j_mayer | if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0) |
2084 | d9bce9d9 | j_mayer | enter_pm = 1;
|
2085 | d9bce9d9 | j_mayer | break;
|
2086 | a750fc0b | j_mayer | case POWERPC_EXCP_604:
|
2087 | d9bce9d9 | j_mayer | if (msr_pow == 1) |
2088 | d9bce9d9 | j_mayer | enter_pm = 1;
|
2089 | d9bce9d9 | j_mayer | break;
|
2090 | a750fc0b | j_mayer | case POWERPC_EXCP_7x0:
|
2091 | 76a66253 | j_mayer | if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0) |
2092 | 50443c98 | bellard | enter_pm = 1;
|
2093 | 50443c98 | bellard | break;
|
2094 | 50443c98 | bellard | default:
|
2095 | 50443c98 | bellard | break;
|
2096 | 50443c98 | bellard | } |
2097 | a97fed52 | j_mayer | |
2098 | a97fed52 | j_mayer | return enter_pm;
|
2099 | 3fc6c082 | bellard | } |
2100 | 3fc6c082 | bellard | |
2101 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2102 | a97fed52 | j_mayer | int ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
|
2103 | d9bce9d9 | j_mayer | { |
2104 | a97fed52 | j_mayer | return do_store_msr(env, (do_load_msr(env) & ~0xFFFFFFFFULL) | |
2105 | a97fed52 | j_mayer | (value & 0xFFFFFFFF));
|
2106 | d9bce9d9 | j_mayer | } |
2107 | d9bce9d9 | j_mayer | #endif
|
2108 | d9bce9d9 | j_mayer | |
2109 | 76a66253 | j_mayer | void do_compute_hflags (CPUPPCState *env)
|
2110 | 3fc6c082 | bellard | { |
2111 | 76a66253 | j_mayer | /* Compute current hflags */
|
2112 | 4296f459 | j_mayer | env->hflags = (msr_vr << MSR_VR) | |
2113 | c62db105 | j_mayer | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) | |
2114 | c62db105 | j_mayer | (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) | |
2115 | c62db105 | j_mayer | (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE); |
2116 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
|
2117 | 4296f459 | j_mayer | env->hflags |= msr_cm << MSR_CM; |
2118 | 4296f459 | j_mayer | env->hflags |= (uint64_t)msr_sf << MSR_SF; |
2119 | 4296f459 | j_mayer | env->hflags |= (uint64_t)msr_hv << MSR_HV; |
2120 | 6ebbf390 | j_mayer | /* Precompute MMU index */
|
2121 | 6ebbf390 | j_mayer | if (msr_pr == 0 && msr_hv == 1) |
2122 | 6ebbf390 | j_mayer | env->mmu_idx = 2;
|
2123 | 6ebbf390 | j_mayer | else
|
2124 | 4b3686fa | bellard | #endif
|
2125 | 6ebbf390 | j_mayer | env->mmu_idx = 1 - msr_pr;
|
2126 | 3fc6c082 | bellard | } |
2127 | 3fc6c082 | bellard | |
2128 | 3fc6c082 | bellard | /*****************************************************************************/
|
2129 | 3fc6c082 | bellard | /* Exception processing */
|
2130 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
2131 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
2132 | 79aceca5 | bellard | { |
2133 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2134 | e1833e1f | j_mayer | env->error_code = 0;
|
2135 | 18fba28c | bellard | } |
2136 | 47103572 | j_mayer | |
2137 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUState *env)
|
2138 | 47103572 | j_mayer | { |
2139 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2140 | e1833e1f | j_mayer | env->error_code = 0;
|
2141 | 47103572 | j_mayer | } |
2142 | 76a66253 | j_mayer | #else /* defined (CONFIG_USER_ONLY) */ |
2143 | 36081602 | j_mayer | static void dump_syscall (CPUState *env) |
2144 | d094807b | bellard | { |
2145 | d9bce9d9 | j_mayer | fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX |
2146 | 1b9eb036 | j_mayer | " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n", |
2147 | d094807b | bellard | env->gpr[0], env->gpr[3], env->gpr[4], |
2148 | d094807b | bellard | env->gpr[5], env->gpr[6], env->nip); |
2149 | d094807b | bellard | } |
2150 | d094807b | bellard | |
2151 | e1833e1f | j_mayer | /* Note that this function should be greatly optimized
|
2152 | e1833e1f | j_mayer | * when called with a constant excp, from ppc_hw_interrupt
|
2153 | e1833e1f | j_mayer | */
|
2154 | e1833e1f | j_mayer | static always_inline void powerpc_excp (CPUState *env, |
2155 | e1833e1f | j_mayer | int excp_model, int excp) |
2156 | 18fba28c | bellard | { |
2157 | e1833e1f | j_mayer | target_ulong msr, vector; |
2158 | e1833e1f | j_mayer | int srr0, srr1, asrr0, asrr1;
|
2159 | 79aceca5 | bellard | |
2160 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2161 | 1b9eb036 | j_mayer | fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
2162 | 1b9eb036 | j_mayer | env->nip, excp, env->error_code); |
2163 | b769d8fe | bellard | } |
2164 | e1833e1f | j_mayer | msr = do_load_msr(env); |
2165 | e1833e1f | j_mayer | srr0 = SPR_SRR0; |
2166 | e1833e1f | j_mayer | srr1 = SPR_SRR1; |
2167 | e1833e1f | j_mayer | asrr0 = -1;
|
2168 | e1833e1f | j_mayer | asrr1 = -1;
|
2169 | e1833e1f | j_mayer | msr &= ~((target_ulong)0x783F0000);
|
2170 | 9a64fbe4 | bellard | switch (excp) {
|
2171 | e1833e1f | j_mayer | case POWERPC_EXCP_NONE:
|
2172 | e1833e1f | j_mayer | /* Should never happen */
|
2173 | e1833e1f | j_mayer | return;
|
2174 | e1833e1f | j_mayer | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
2175 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2176 | e1833e1f | j_mayer | switch (excp_model) {
|
2177 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2178 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2179 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2180 | c62db105 | j_mayer | break;
|
2181 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2182 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2183 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2184 | c62db105 | j_mayer | break;
|
2185 | e1833e1f | j_mayer | case POWERPC_EXCP_G2:
|
2186 | c62db105 | j_mayer | break;
|
2187 | e1833e1f | j_mayer | default:
|
2188 | e1833e1f | j_mayer | goto excp_invalid;
|
2189 | 2be0071f | bellard | } |
2190 | 9a64fbe4 | bellard | goto store_next;
|
2191 | e1833e1f | j_mayer | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2192 | e1833e1f | j_mayer | if (msr_me == 0) { |
2193 | e63ecc6f | j_mayer | /* Machine check exception is not enabled.
|
2194 | e63ecc6f | j_mayer | * Enter checkstop state.
|
2195 | e63ecc6f | j_mayer | */
|
2196 | e63ecc6f | j_mayer | if (loglevel != 0) { |
2197 | e63ecc6f | j_mayer | fprintf(logfile, "Machine check while not allowed. "
|
2198 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2199 | e63ecc6f | j_mayer | } else {
|
2200 | e63ecc6f | j_mayer | fprintf(stderr, "Machine check while not allowed. "
|
2201 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2202 | e63ecc6f | j_mayer | } |
2203 | e63ecc6f | j_mayer | env->halted = 1;
|
2204 | e63ecc6f | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
2205 | e1833e1f | j_mayer | } |
2206 | e1833e1f | j_mayer | msr_ri = 0;
|
2207 | e1833e1f | j_mayer | msr_me = 0;
|
2208 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2209 | e1833e1f | j_mayer | msr_hv = 1;
|
2210 | e1833e1f | j_mayer | #endif
|
2211 | e1833e1f | j_mayer | /* XXX: should also have something loaded in DAR / DSISR */
|
2212 | e1833e1f | j_mayer | switch (excp_model) {
|
2213 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2214 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2215 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2216 | c62db105 | j_mayer | break;
|
2217 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2218 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_MCSRR0; |
2219 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_MCSRR1; |
2220 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2221 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2222 | c62db105 | j_mayer | break;
|
2223 | c62db105 | j_mayer | default:
|
2224 | c62db105 | j_mayer | break;
|
2225 | 2be0071f | bellard | } |
2226 | e1833e1f | j_mayer | goto store_next;
|
2227 | e1833e1f | j_mayer | case POWERPC_EXCP_DSI: /* Data storage exception */ |
2228 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2229 | 4a057712 | j_mayer | if (loglevel != 0) { |
2230 | 1b9eb036 | j_mayer | fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
2231 | 1b9eb036 | j_mayer | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
2232 | 76a66253 | j_mayer | } |
2233 | a541f297 | bellard | #endif
|
2234 | e1833e1f | j_mayer | msr_ri = 0;
|
2235 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2236 | e1833e1f | j_mayer | if (lpes1 == 0) |
2237 | e1833e1f | j_mayer | msr_hv = 1;
|
2238 | e1833e1f | j_mayer | #endif
|
2239 | a541f297 | bellard | goto store_next;
|
2240 | e1833e1f | j_mayer | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
2241 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2242 | 76a66253 | j_mayer | if (loglevel != 0) { |
2243 | 1b9eb036 | j_mayer | fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX |
2244 | 1b9eb036 | j_mayer | "\n", msr, env->nip);
|
2245 | 76a66253 | j_mayer | } |
2246 | a541f297 | bellard | #endif
|
2247 | e1833e1f | j_mayer | msr_ri = 0;
|
2248 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2249 | e1833e1f | j_mayer | if (lpes1 == 0) |
2250 | e1833e1f | j_mayer | msr_hv = 1;
|
2251 | e1833e1f | j_mayer | #endif
|
2252 | e1833e1f | j_mayer | msr |= env->error_code; |
2253 | 9a64fbe4 | bellard | goto store_next;
|
2254 | e1833e1f | j_mayer | case POWERPC_EXCP_EXTERNAL: /* External input */ |
2255 | e1833e1f | j_mayer | msr_ri = 0;
|
2256 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2257 | e1833e1f | j_mayer | if (lpes0 == 1) |
2258 | e1833e1f | j_mayer | msr_hv = 1;
|
2259 | e1833e1f | j_mayer | #endif
|
2260 | 9a64fbe4 | bellard | goto store_next;
|
2261 | e1833e1f | j_mayer | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
2262 | e1833e1f | j_mayer | msr_ri = 0;
|
2263 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2264 | e1833e1f | j_mayer | if (lpes1 == 0) |
2265 | e1833e1f | j_mayer | msr_hv = 1;
|
2266 | e1833e1f | j_mayer | #endif
|
2267 | e1833e1f | j_mayer | /* XXX: this is false */
|
2268 | e1833e1f | j_mayer | /* Get rS/rD and rA from faulting opcode */
|
2269 | e1833e1f | j_mayer | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
2270 | 9a64fbe4 | bellard | goto store_current;
|
2271 | e1833e1f | j_mayer | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
2272 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
2273 | e1833e1f | j_mayer | case POWERPC_EXCP_FP:
|
2274 | e1833e1f | j_mayer | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
2275 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2276 | 4a057712 | j_mayer | if (loglevel != 0) { |
2277 | a496775f | j_mayer | fprintf(logfile, "Ignore floating point exception\n");
|
2278 | a496775f | j_mayer | } |
2279 | 9a64fbe4 | bellard | #endif
|
2280 | 9a64fbe4 | bellard | return;
|
2281 | 76a66253 | j_mayer | } |
2282 | e1833e1f | j_mayer | msr_ri = 0;
|
2283 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2284 | e1833e1f | j_mayer | if (lpes1 == 0) |
2285 | e1833e1f | j_mayer | msr_hv = 1;
|
2286 | e1833e1f | j_mayer | #endif
|
2287 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
2288 | 9a64fbe4 | bellard | /* Set FX */
|
2289 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x8; |
2290 | 9a64fbe4 | bellard | /* Finally, update FEX */
|
2291 | 9a64fbe4 | bellard | if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
2292 | 9a64fbe4 | bellard | ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
2293 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x4; |
2294 | e1833e1f | j_mayer | if (msr_fe0 != msr_fe1) {
|
2295 | e1833e1f | j_mayer | msr |= 0x00010000;
|
2296 | e1833e1f | j_mayer | goto store_current;
|
2297 | e1833e1f | j_mayer | } |
2298 | 76a66253 | j_mayer | break;
|
2299 | e1833e1f | j_mayer | case POWERPC_EXCP_INVAL:
|
2300 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2301 | 4a057712 | j_mayer | if (loglevel != 0) { |
2302 | a496775f | j_mayer | fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n", |
2303 | a496775f | j_mayer | env->nip); |
2304 | a496775f | j_mayer | } |
2305 | a496775f | j_mayer | #endif
|
2306 | e1833e1f | j_mayer | msr_ri = 0;
|
2307 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2308 | e1833e1f | j_mayer | if (lpes1 == 0) |
2309 | e1833e1f | j_mayer | msr_hv = 1;
|
2310 | e1833e1f | j_mayer | #endif
|
2311 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
2312 | 76a66253 | j_mayer | break;
|
2313 | e1833e1f | j_mayer | case POWERPC_EXCP_PRIV:
|
2314 | e1833e1f | j_mayer | msr_ri = 0;
|
2315 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2316 | e1833e1f | j_mayer | if (lpes1 == 0) |
2317 | e1833e1f | j_mayer | msr_hv = 1;
|
2318 | e1833e1f | j_mayer | #endif
|
2319 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
2320 | 76a66253 | j_mayer | break;
|
2321 | e1833e1f | j_mayer | case POWERPC_EXCP_TRAP:
|
2322 | e1833e1f | j_mayer | msr_ri = 0;
|
2323 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2324 | e1833e1f | j_mayer | if (lpes1 == 0) |
2325 | e1833e1f | j_mayer | msr_hv = 1;
|
2326 | e1833e1f | j_mayer | #endif
|
2327 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
2328 | 9a64fbe4 | bellard | break;
|
2329 | 9a64fbe4 | bellard | default:
|
2330 | 9a64fbe4 | bellard | /* Should never occur */
|
2331 | e1833e1f | j_mayer | cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
2332 | e1833e1f | j_mayer | env->error_code); |
2333 | 76a66253 | j_mayer | break;
|
2334 | 76a66253 | j_mayer | } |
2335 | 9a64fbe4 | bellard | goto store_next;
|
2336 | e1833e1f | j_mayer | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
2337 | e1833e1f | j_mayer | msr_ri = 0;
|
2338 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2339 | e1833e1f | j_mayer | if (lpes1 == 0) |
2340 | e1833e1f | j_mayer | msr_hv = 1;
|
2341 | e1833e1f | j_mayer | #endif
|
2342 | e1833e1f | j_mayer | goto store_current;
|
2343 | e1833e1f | j_mayer | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
2344 | d094807b | bellard | /* NOTE: this is a temporary hack to support graphics OSI
|
2345 | d094807b | bellard | calls from the MOL driver */
|
2346 | e1833e1f | j_mayer | /* XXX: To be removed */
|
2347 | d094807b | bellard | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2348 | d094807b | bellard | env->osi_call) { |
2349 | d094807b | bellard | if (env->osi_call(env) != 0) |
2350 | d094807b | bellard | return;
|
2351 | d094807b | bellard | } |
2352 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2353 | d094807b | bellard | dump_syscall(env); |
2354 | b769d8fe | bellard | } |
2355 | e1833e1f | j_mayer | msr_ri = 0;
|
2356 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2357 | e1833e1f | j_mayer | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2358 | e1833e1f | j_mayer | msr_hv = 1;
|
2359 | e1833e1f | j_mayer | #endif
|
2360 | e1833e1f | j_mayer | goto store_next;
|
2361 | e1833e1f | j_mayer | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
2362 | e1833e1f | j_mayer | msr_ri = 0;
|
2363 | e1833e1f | j_mayer | goto store_current;
|
2364 | e1833e1f | j_mayer | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
2365 | e1833e1f | j_mayer | msr_ri = 0;
|
2366 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2367 | e1833e1f | j_mayer | if (lpes1 == 0) |
2368 | e1833e1f | j_mayer | msr_hv = 1;
|
2369 | e1833e1f | j_mayer | #endif
|
2370 | e1833e1f | j_mayer | goto store_next;
|
2371 | e1833e1f | j_mayer | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
2372 | e1833e1f | j_mayer | /* FIT on 4xx */
|
2373 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2374 | e1833e1f | j_mayer | if (loglevel != 0) |
2375 | e1833e1f | j_mayer | fprintf(logfile, "FIT exception\n");
|
2376 | e1833e1f | j_mayer | #endif
|
2377 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2378 | 9a64fbe4 | bellard | goto store_next;
|
2379 | e1833e1f | j_mayer | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2380 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2381 | e1833e1f | j_mayer | if (loglevel != 0) |
2382 | e1833e1f | j_mayer | fprintf(logfile, "WDT exception\n");
|
2383 | e1833e1f | j_mayer | #endif
|
2384 | e1833e1f | j_mayer | switch (excp_model) {
|
2385 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2386 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2387 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2388 | e1833e1f | j_mayer | break;
|
2389 | e1833e1f | j_mayer | default:
|
2390 | e1833e1f | j_mayer | break;
|
2391 | e1833e1f | j_mayer | } |
2392 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2393 | 2be0071f | bellard | goto store_next;
|
2394 | e1833e1f | j_mayer | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
2395 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2396 | e1833e1f | j_mayer | goto store_next;
|
2397 | e1833e1f | j_mayer | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
2398 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2399 | e1833e1f | j_mayer | goto store_next;
|
2400 | e1833e1f | j_mayer | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
2401 | e1833e1f | j_mayer | switch (excp_model) {
|
2402 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2403 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_DSRR0; |
2404 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_DSRR1; |
2405 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2406 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2407 | e1833e1f | j_mayer | break;
|
2408 | e1833e1f | j_mayer | default:
|
2409 | e1833e1f | j_mayer | break;
|
2410 | e1833e1f | j_mayer | } |
2411 | 2be0071f | bellard | /* XXX: TODO */
|
2412 | e1833e1f | j_mayer | cpu_abort(env, "Debug exception is not implemented yet !\n");
|
2413 | 2be0071f | bellard | goto store_next;
|
2414 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2415 | e1833e1f | j_mayer | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
2416 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2417 | e1833e1f | j_mayer | goto store_current;
|
2418 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
2419 | 2be0071f | bellard | /* XXX: TODO */
|
2420 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point data exception "
|
2421 | 2be0071f | bellard | "is not implemented yet !\n");
|
2422 | 2be0071f | bellard | goto store_next;
|
2423 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2424 | 2be0071f | bellard | /* XXX: TODO */
|
2425 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point round exception "
|
2426 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2427 | 9a64fbe4 | bellard | goto store_next;
|
2428 | e1833e1f | j_mayer | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
2429 | e1833e1f | j_mayer | msr_ri = 0;
|
2430 | 2be0071f | bellard | /* XXX: TODO */
|
2431 | 2be0071f | bellard | cpu_abort(env, |
2432 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2433 | 9a64fbe4 | bellard | goto store_next;
|
2434 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
2435 | 76a66253 | j_mayer | /* XXX: TODO */
|
2436 | e1833e1f | j_mayer | cpu_abort(env, |
2437 | e1833e1f | j_mayer | "Embedded doorbell interrupt is not implemented yet !\n");
|
2438 | 2be0071f | bellard | goto store_next;
|
2439 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2440 | e1833e1f | j_mayer | switch (excp_model) {
|
2441 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2442 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2443 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2444 | a750fc0b | j_mayer | break;
|
2445 | 2be0071f | bellard | default:
|
2446 | 2be0071f | bellard | break;
|
2447 | 2be0071f | bellard | } |
2448 | e1833e1f | j_mayer | /* XXX: TODO */
|
2449 | e1833e1f | j_mayer | cpu_abort(env, "Embedded doorbell critical interrupt "
|
2450 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2451 | e1833e1f | j_mayer | goto store_next;
|
2452 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPCEMB) */ |
2453 | e1833e1f | j_mayer | case POWERPC_EXCP_RESET: /* System reset exception */ |
2454 | e1833e1f | j_mayer | msr_ri = 0;
|
2455 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2456 | e1833e1f | j_mayer | msr_hv = 1;
|
2457 | e1833e1f | j_mayer | #endif
|
2458 | e1833e1f | j_mayer | goto store_next;
|
2459 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
2460 | e1833e1f | j_mayer | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
2461 | e1833e1f | j_mayer | msr_ri = 0;
|
2462 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2463 | e1833e1f | j_mayer | if (lpes1 == 0) |
2464 | e1833e1f | j_mayer | msr_hv = 1;
|
2465 | e1833e1f | j_mayer | #endif
|
2466 | e1833e1f | j_mayer | goto store_next;
|
2467 | e1833e1f | j_mayer | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
2468 | e1833e1f | j_mayer | msr_ri = 0;
|
2469 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2470 | e1833e1f | j_mayer | if (lpes1 == 0) |
2471 | e1833e1f | j_mayer | msr_hv = 1;
|
2472 | e1833e1f | j_mayer | #endif
|
2473 | e1833e1f | j_mayer | goto store_next;
|
2474 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
2475 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2476 | e1833e1f | j_mayer | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2477 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2478 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2479 | e1833e1f | j_mayer | msr_hv = 1;
|
2480 | e1833e1f | j_mayer | goto store_next;
|
2481 | e1833e1f | j_mayer | #endif
|
2482 | e1833e1f | j_mayer | case POWERPC_EXCP_TRACE: /* Trace exception */ |
2483 | e1833e1f | j_mayer | msr_ri = 0;
|
2484 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2485 | e1833e1f | j_mayer | if (lpes1 == 0) |
2486 | e1833e1f | j_mayer | msr_hv = 1;
|
2487 | e1833e1f | j_mayer | #endif
|
2488 | e1833e1f | j_mayer | goto store_next;
|
2489 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2490 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2491 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2492 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2493 | e1833e1f | j_mayer | msr_hv = 1;
|
2494 | e1833e1f | j_mayer | goto store_next;
|
2495 | e1833e1f | j_mayer | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2496 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2497 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2498 | e1833e1f | j_mayer | msr_hv = 1;
|
2499 | e1833e1f | j_mayer | /* XXX: TODO */
|
2500 | e1833e1f | j_mayer | cpu_abort(env, "Hypervisor instruction storage exception "
|
2501 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2502 | e1833e1f | j_mayer | goto store_next;
|
2503 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2504 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2505 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2506 | e1833e1f | j_mayer | msr_hv = 1;
|
2507 | e1833e1f | j_mayer | goto store_next;
|
2508 | e1833e1f | j_mayer | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2509 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2510 | e1833e1f | j_mayer | srr1 = SPR_HSSR1; |
2511 | e1833e1f | j_mayer | msr_hv = 1;
|
2512 | e1833e1f | j_mayer | goto store_next;
|
2513 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64H) */ |
2514 | e1833e1f | j_mayer | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
2515 | e1833e1f | j_mayer | msr_ri = 0;
|
2516 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2517 | e1833e1f | j_mayer | if (lpes1 == 0) |
2518 | e1833e1f | j_mayer | msr_hv = 1;
|
2519 | e1833e1f | j_mayer | #endif
|
2520 | e1833e1f | j_mayer | goto store_current;
|
2521 | e1833e1f | j_mayer | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
2522 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2523 | e1833e1f | j_mayer | if (loglevel != 0) |
2524 | e1833e1f | j_mayer | fprintf(logfile, "PIT exception\n");
|
2525 | e1833e1f | j_mayer | #endif
|
2526 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2527 | e1833e1f | j_mayer | goto store_next;
|
2528 | e1833e1f | j_mayer | case POWERPC_EXCP_IO: /* IO error exception */ |
2529 | e1833e1f | j_mayer | /* XXX: TODO */
|
2530 | e1833e1f | j_mayer | cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
2531 | e1833e1f | j_mayer | goto store_next;
|
2532 | e1833e1f | j_mayer | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
2533 | e1833e1f | j_mayer | /* XXX: TODO */
|
2534 | e1833e1f | j_mayer | cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
2535 | e1833e1f | j_mayer | goto store_next;
|
2536 | e1833e1f | j_mayer | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
2537 | e1833e1f | j_mayer | /* XXX: TODO */
|
2538 | e1833e1f | j_mayer | cpu_abort(env, "602 emulation trap exception "
|
2539 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2540 | e1833e1f | j_mayer | goto store_next;
|
2541 | e1833e1f | j_mayer | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
2542 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2543 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2544 | e1833e1f | j_mayer | if (lpes1 == 0) |
2545 | e1833e1f | j_mayer | msr_hv = 1;
|
2546 | a496775f | j_mayer | #endif
|
2547 | e1833e1f | j_mayer | switch (excp_model) {
|
2548 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2549 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2550 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2551 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2552 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2553 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2554 | 76a66253 | j_mayer | goto tlb_miss;
|
2555 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2556 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2557 | 2be0071f | bellard | default:
|
2558 | e1833e1f | j_mayer | cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
2559 | 2be0071f | bellard | break;
|
2560 | 2be0071f | bellard | } |
2561 | e1833e1f | j_mayer | break;
|
2562 | e1833e1f | j_mayer | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
2563 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2564 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2565 | e1833e1f | j_mayer | if (lpes1 == 0) |
2566 | e1833e1f | j_mayer | msr_hv = 1;
|
2567 | a496775f | j_mayer | #endif
|
2568 | e1833e1f | j_mayer | switch (excp_model) {
|
2569 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2570 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2571 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2572 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2573 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2574 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2575 | 76a66253 | j_mayer | goto tlb_miss;
|
2576 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2577 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2578 | 2be0071f | bellard | default:
|
2579 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data load TLB miss exception\n");
|
2580 | 2be0071f | bellard | break;
|
2581 | 2be0071f | bellard | } |
2582 | e1833e1f | j_mayer | break;
|
2583 | e1833e1f | j_mayer | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
2584 | e1833e1f | j_mayer | msr_ri = 0; /* XXX: check this */ |
2585 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2586 | e1833e1f | j_mayer | if (lpes1 == 0) |
2587 | e1833e1f | j_mayer | msr_hv = 1;
|
2588 | e1833e1f | j_mayer | #endif
|
2589 | e1833e1f | j_mayer | switch (excp_model) {
|
2590 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2591 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2592 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2593 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2594 | e1833e1f | j_mayer | tlb_miss_tgpr:
|
2595 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
2596 | 76a66253 | j_mayer | swap_gpr_tgpr(env); |
2597 | 76a66253 | j_mayer | msr_tgpr = 1;
|
2598 | e1833e1f | j_mayer | goto tlb_miss;
|
2599 | e1833e1f | j_mayer | case POWERPC_EXCP_7x5:
|
2600 | e1833e1f | j_mayer | tlb_miss:
|
2601 | 2be0071f | bellard | #if defined (DEBUG_SOFTWARE_TLB)
|
2602 | 2be0071f | bellard | if (loglevel != 0) { |
2603 | 76a66253 | j_mayer | const unsigned char *es; |
2604 | 76a66253 | j_mayer | target_ulong *miss, *cmp; |
2605 | 76a66253 | j_mayer | int en;
|
2606 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2607 | 76a66253 | j_mayer | es = "I";
|
2608 | 76a66253 | j_mayer | en = 'I';
|
2609 | 76a66253 | j_mayer | miss = &env->spr[SPR_IMISS]; |
2610 | 76a66253 | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2611 | 76a66253 | j_mayer | } else {
|
2612 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2613 | 76a66253 | j_mayer | es = "DL";
|
2614 | 76a66253 | j_mayer | else
|
2615 | 76a66253 | j_mayer | es = "DS";
|
2616 | 76a66253 | j_mayer | en = 'D';
|
2617 | 76a66253 | j_mayer | miss = &env->spr[SPR_DMISS]; |
2618 | 76a66253 | j_mayer | cmp = &env->spr[SPR_DCMP]; |
2619 | 76a66253 | j_mayer | } |
2620 | 1b9eb036 | j_mayer | fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2621 | 4a057712 | j_mayer | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
2622 | 1b9eb036 | j_mayer | es, en, *miss, en, *cmp, |
2623 | 76a66253 | j_mayer | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2624 | 2be0071f | bellard | env->error_code); |
2625 | 2be0071f | bellard | } |
2626 | 9a64fbe4 | bellard | #endif
|
2627 | 2be0071f | bellard | msr |= env->crf[0] << 28; |
2628 | 2be0071f | bellard | msr |= env->error_code; /* key, D/I, S/L bits */
|
2629 | 2be0071f | bellard | /* Set way using a LRU mechanism */
|
2630 | 76a66253 | j_mayer | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2631 | c62db105 | j_mayer | break;
|
2632 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2633 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
2634 | 7dbe11ac | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
2635 | 7dbe11ac | j_mayer | if (loglevel != 0) { |
2636 | 7dbe11ac | j_mayer | const unsigned char *es; |
2637 | 7dbe11ac | j_mayer | target_ulong *miss, *cmp; |
2638 | 7dbe11ac | j_mayer | int en;
|
2639 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2640 | 7dbe11ac | j_mayer | es = "I";
|
2641 | 7dbe11ac | j_mayer | en = 'I';
|
2642 | 7dbe11ac | j_mayer | miss = &env->spr[SPR_IMISS]; |
2643 | 7dbe11ac | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2644 | 7dbe11ac | j_mayer | } else {
|
2645 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2646 | 7dbe11ac | j_mayer | es = "DL";
|
2647 | 7dbe11ac | j_mayer | else
|
2648 | 7dbe11ac | j_mayer | es = "DS";
|
2649 | 7dbe11ac | j_mayer | en = 'D';
|
2650 | 7dbe11ac | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2651 | 7dbe11ac | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2652 | 7dbe11ac | j_mayer | } |
2653 | 7dbe11ac | j_mayer | fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2654 | 7dbe11ac | j_mayer | " %08x\n",
|
2655 | 7dbe11ac | j_mayer | es, en, *miss, en, *cmp, env->error_code); |
2656 | 7dbe11ac | j_mayer | } |
2657 | 7dbe11ac | j_mayer | #endif
|
2658 | 7dbe11ac | j_mayer | msr |= env->error_code; /* key bit */
|
2659 | 7dbe11ac | j_mayer | break;
|
2660 | 2be0071f | bellard | default:
|
2661 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data store TLB miss exception\n");
|
2662 | 2be0071f | bellard | break;
|
2663 | 2be0071f | bellard | } |
2664 | e1833e1f | j_mayer | goto store_next;
|
2665 | e1833e1f | j_mayer | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
2666 | e1833e1f | j_mayer | /* XXX: TODO */
|
2667 | e1833e1f | j_mayer | cpu_abort(env, "Floating point assist exception "
|
2668 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2669 | e1833e1f | j_mayer | goto store_next;
|
2670 | e1833e1f | j_mayer | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2671 | e1833e1f | j_mayer | /* XXX: TODO */
|
2672 | e1833e1f | j_mayer | cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2673 | e1833e1f | j_mayer | goto store_next;
|
2674 | e1833e1f | j_mayer | case POWERPC_EXCP_SMI: /* System management interrupt */ |
2675 | e1833e1f | j_mayer | /* XXX: TODO */
|
2676 | e1833e1f | j_mayer | cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2677 | e1833e1f | j_mayer | goto store_next;
|
2678 | e1833e1f | j_mayer | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
2679 | e1833e1f | j_mayer | /* XXX: TODO */
|
2680 | e1833e1f | j_mayer | cpu_abort(env, "Thermal management exception "
|
2681 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2682 | e1833e1f | j_mayer | goto store_next;
|
2683 | e1833e1f | j_mayer | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
2684 | e1833e1f | j_mayer | msr_ri = 0;
|
2685 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2686 | e1833e1f | j_mayer | if (lpes1 == 0) |
2687 | e1833e1f | j_mayer | msr_hv = 1;
|
2688 | e1833e1f | j_mayer | #endif
|
2689 | e1833e1f | j_mayer | /* XXX: TODO */
|
2690 | e1833e1f | j_mayer | cpu_abort(env, |
2691 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2692 | e1833e1f | j_mayer | goto store_next;
|
2693 | e1833e1f | j_mayer | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
2694 | e1833e1f | j_mayer | /* XXX: TODO */
|
2695 | e1833e1f | j_mayer | cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2696 | e1833e1f | j_mayer | goto store_next;
|
2697 | e1833e1f | j_mayer | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
2698 | e1833e1f | j_mayer | /* XXX: TODO */
|
2699 | e1833e1f | j_mayer | cpu_abort(env, |
2700 | e1833e1f | j_mayer | "970 soft-patch exception is not implemented yet !\n");
|
2701 | e1833e1f | j_mayer | goto store_next;
|
2702 | e1833e1f | j_mayer | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
2703 | e1833e1f | j_mayer | /* XXX: TODO */
|
2704 | e1833e1f | j_mayer | cpu_abort(env, |
2705 | e1833e1f | j_mayer | "970 maintenance exception is not implemented yet !\n");
|
2706 | e1833e1f | j_mayer | goto store_next;
|
2707 | 2be0071f | bellard | default:
|
2708 | e1833e1f | j_mayer | excp_invalid:
|
2709 | e1833e1f | j_mayer | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
2710 | e1833e1f | j_mayer | break;
|
2711 | 9a64fbe4 | bellard | store_current:
|
2712 | 2be0071f | bellard | /* save current instruction location */
|
2713 | e1833e1f | j_mayer | env->spr[srr0] = env->nip - 4;
|
2714 | 9a64fbe4 | bellard | break;
|
2715 | 9a64fbe4 | bellard | store_next:
|
2716 | 2be0071f | bellard | /* save next instruction location */
|
2717 | e1833e1f | j_mayer | env->spr[srr0] = env->nip; |
2718 | 9a64fbe4 | bellard | break;
|
2719 | 9a64fbe4 | bellard | } |
2720 | e1833e1f | j_mayer | /* Save MSR */
|
2721 | e1833e1f | j_mayer | env->spr[srr1] = msr; |
2722 | e1833e1f | j_mayer | /* If any alternate SRR register are defined, duplicate saved values */
|
2723 | e1833e1f | j_mayer | if (asrr0 != -1) |
2724 | e1833e1f | j_mayer | env->spr[asrr0] = env->spr[srr0]; |
2725 | e1833e1f | j_mayer | if (asrr1 != -1) |
2726 | e1833e1f | j_mayer | env->spr[asrr1] = env->spr[srr1]; |
2727 | 2be0071f | bellard | /* If we disactivated any translation, flush TLBs */
|
2728 | e1833e1f | j_mayer | if (msr_ir || msr_dr)
|
2729 | 2be0071f | bellard | tlb_flush(env, 1);
|
2730 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
2731 | 9a64fbe4 | bellard | msr_ee = 0;
|
2732 | 9a64fbe4 | bellard | msr_pr = 0;
|
2733 | 9a64fbe4 | bellard | msr_fp = 0;
|
2734 | 9a64fbe4 | bellard | msr_fe0 = 0;
|
2735 | 9a64fbe4 | bellard | msr_se = 0;
|
2736 | 9a64fbe4 | bellard | msr_be = 0;
|
2737 | 9a64fbe4 | bellard | msr_fe1 = 0;
|
2738 | 9a64fbe4 | bellard | msr_ir = 0;
|
2739 | 9a64fbe4 | bellard | msr_dr = 0;
|
2740 | e1833e1f | j_mayer | #if 0 /* Fix this: not on all targets */
|
2741 | e1833e1f | j_mayer | msr_pmm = 0;
|
2742 | e1833e1f | j_mayer | #endif
|
2743 | 9a64fbe4 | bellard | msr_le = msr_ile; |
2744 | e1833e1f | j_mayer | do_compute_hflags(env); |
2745 | e1833e1f | j_mayer | /* Jump to handler */
|
2746 | e1833e1f | j_mayer | vector = env->excp_vectors[excp]; |
2747 | e1833e1f | j_mayer | if (vector == (target_ulong)-1) { |
2748 | e1833e1f | j_mayer | cpu_abort(env, "Raised an exception without defined vector %d\n",
|
2749 | e1833e1f | j_mayer | excp); |
2750 | e1833e1f | j_mayer | } |
2751 | e1833e1f | j_mayer | vector |= env->excp_prefix; |
2752 | c62db105 | j_mayer | #if defined(TARGET_PPC64)
|
2753 | e1833e1f | j_mayer | if (excp_model == POWERPC_EXCP_BOOKE) {
|
2754 | e1833e1f | j_mayer | msr_cm = msr_icm; |
2755 | e1833e1f | j_mayer | if (!msr_cm)
|
2756 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2757 | c62db105 | j_mayer | } else {
|
2758 | c62db105 | j_mayer | msr_sf = msr_isf; |
2759 | e1833e1f | j_mayer | if (!msr_sf)
|
2760 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2761 | c62db105 | j_mayer | } |
2762 | e1833e1f | j_mayer | #endif
|
2763 | e1833e1f | j_mayer | env->nip = vector; |
2764 | e1833e1f | j_mayer | /* Reset exception state */
|
2765 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2766 | e1833e1f | j_mayer | env->error_code = 0;
|
2767 | fb0eaffc | bellard | } |
2768 | 47103572 | j_mayer | |
2769 | e1833e1f | j_mayer | void do_interrupt (CPUState *env)
|
2770 | 47103572 | j_mayer | { |
2771 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, env->exception_index); |
2772 | e1833e1f | j_mayer | } |
2773 | 47103572 | j_mayer | |
2774 | e1833e1f | j_mayer | void ppc_hw_interrupt (CPUPPCState *env)
|
2775 | e1833e1f | j_mayer | { |
2776 | a496775f | j_mayer | #if 1 |
2777 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
2778 | a496775f | j_mayer | fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2779 | a496775f | j_mayer | __func__, env, env->pending_interrupts, |
2780 | a496775f | j_mayer | env->interrupt_request, msr_me, msr_ee); |
2781 | a496775f | j_mayer | } |
2782 | 47103572 | j_mayer | #endif
|
2783 | e1833e1f | j_mayer | /* External reset */
|
2784 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2785 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2786 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2787 | e1833e1f | j_mayer | return;
|
2788 | e1833e1f | j_mayer | } |
2789 | e1833e1f | j_mayer | /* Machine check exception */
|
2790 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2791 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2792 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
2793 | e1833e1f | j_mayer | return;
|
2794 | 47103572 | j_mayer | } |
2795 | e1833e1f | j_mayer | #if 0 /* TODO */
|
2796 | e1833e1f | j_mayer | /* External debug exception */
|
2797 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2798 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2799 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
2800 | e1833e1f | j_mayer | return;
|
2801 | e1833e1f | j_mayer | }
|
2802 | e1833e1f | j_mayer | #endif
|
2803 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2804 | e1833e1f | j_mayer | if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) { |
2805 | 47103572 | j_mayer | /* Hypervisor decrementer exception */
|
2806 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2807 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2808 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2809 | e1833e1f | j_mayer | return;
|
2810 | e1833e1f | j_mayer | } |
2811 | e1833e1f | j_mayer | } |
2812 | e1833e1f | j_mayer | #endif
|
2813 | e1833e1f | j_mayer | if (msr_ce != 0) { |
2814 | e1833e1f | j_mayer | /* External critical interrupt */
|
2815 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
2816 | e1833e1f | j_mayer | /* Taking a critical external interrupt does not clear the external
|
2817 | e1833e1f | j_mayer | * critical interrupt status
|
2818 | e1833e1f | j_mayer | */
|
2819 | e1833e1f | j_mayer | #if 0
|
2820 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
2821 | 47103572 | j_mayer | #endif
|
2822 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2823 | e1833e1f | j_mayer | return;
|
2824 | e1833e1f | j_mayer | } |
2825 | e1833e1f | j_mayer | } |
2826 | e1833e1f | j_mayer | if (msr_ee != 0) { |
2827 | e1833e1f | j_mayer | /* Watchdog timer on embedded PowerPC */
|
2828 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2829 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2830 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
2831 | e1833e1f | j_mayer | return;
|
2832 | e1833e1f | j_mayer | } |
2833 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2834 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2835 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
2836 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
2837 | e1833e1f | j_mayer | return;
|
2838 | e1833e1f | j_mayer | } |
2839 | e1833e1f | j_mayer | #endif
|
2840 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2841 | e1833e1f | j_mayer | /* External interrupt */
|
2842 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2843 | e1833e1f | j_mayer | /* Taking an external interrupt does not clear the external
|
2844 | e1833e1f | j_mayer | * interrupt status
|
2845 | e1833e1f | j_mayer | */
|
2846 | e1833e1f | j_mayer | #if 0
|
2847 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2848 | e1833e1f | j_mayer | #endif
|
2849 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2850 | e1833e1f | j_mayer | return;
|
2851 | e1833e1f | j_mayer | } |
2852 | e1833e1f | j_mayer | #endif
|
2853 | e1833e1f | j_mayer | /* Fixed interval timer on embedded PowerPC */
|
2854 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2855 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2856 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
2857 | e1833e1f | j_mayer | return;
|
2858 | e1833e1f | j_mayer | } |
2859 | e1833e1f | j_mayer | /* Programmable interval timer on embedded PowerPC */
|
2860 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2861 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2862 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
2863 | e1833e1f | j_mayer | return;
|
2864 | e1833e1f | j_mayer | } |
2865 | 47103572 | j_mayer | /* Decrementer exception */
|
2866 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2867 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2868 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2869 | e1833e1f | j_mayer | return;
|
2870 | e1833e1f | j_mayer | } |
2871 | e1833e1f | j_mayer | #if !defined(TARGET_PPCEMB)
|
2872 | 47103572 | j_mayer | /* External interrupt */
|
2873 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2874 | e9df014c | j_mayer | /* Taking an external interrupt does not clear the external
|
2875 | e9df014c | j_mayer | * interrupt status
|
2876 | e9df014c | j_mayer | */
|
2877 | e9df014c | j_mayer | #if 0
|
2878 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2879 | e9df014c | j_mayer | #endif
|
2880 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2881 | e1833e1f | j_mayer | return;
|
2882 | e1833e1f | j_mayer | } |
2883 | d0dfae6e | j_mayer | #endif
|
2884 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2885 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2886 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
2887 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
2888 | e1833e1f | j_mayer | return;
|
2889 | 47103572 | j_mayer | } |
2890 | 47103572 | j_mayer | #endif
|
2891 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2892 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
2893 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
2894 | e1833e1f | j_mayer | return;
|
2895 | e1833e1f | j_mayer | } |
2896 | e1833e1f | j_mayer | /* Thermal interrupt */
|
2897 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
2898 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2899 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
2900 | e1833e1f | j_mayer | return;
|
2901 | e1833e1f | j_mayer | } |
2902 | 47103572 | j_mayer | } |
2903 | 47103572 | j_mayer | } |
2904 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |
2905 | a496775f | j_mayer | |
2906 | a496775f | j_mayer | void cpu_dump_EA (target_ulong EA)
|
2907 | a496775f | j_mayer | { |
2908 | a496775f | j_mayer | FILE *f; |
2909 | a496775f | j_mayer | |
2910 | a496775f | j_mayer | if (logfile) {
|
2911 | a496775f | j_mayer | f = logfile; |
2912 | a496775f | j_mayer | } else {
|
2913 | a496775f | j_mayer | f = stdout; |
2914 | a496775f | j_mayer | return;
|
2915 | a496775f | j_mayer | } |
2916 | 4a057712 | j_mayer | fprintf(f, "Memory access at address " ADDRX "\n", EA); |
2917 | 4a057712 | j_mayer | } |
2918 | 4a057712 | j_mayer | |
2919 | 4a057712 | j_mayer | void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2920 | 4a057712 | j_mayer | { |
2921 | 4a057712 | j_mayer | FILE *f; |
2922 | 4a057712 | j_mayer | |
2923 | 4a057712 | j_mayer | if (logfile) {
|
2924 | 4a057712 | j_mayer | f = logfile; |
2925 | 4a057712 | j_mayer | } else {
|
2926 | 4a057712 | j_mayer | f = stdout; |
2927 | 4a057712 | j_mayer | return;
|
2928 | 4a057712 | j_mayer | } |
2929 | 4a057712 | j_mayer | fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", |
2930 | 4a057712 | j_mayer | RA, msr); |
2931 | a496775f | j_mayer | } |
2932 | a496775f | j_mayer | |
2933 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque) |
2934 | 0a032cbe | j_mayer | { |
2935 | 0a032cbe | j_mayer | CPUPPCState *env; |
2936 | 5eb7995e | j_mayer | int i;
|
2937 | 0a032cbe | j_mayer | |
2938 | 0a032cbe | j_mayer | env = opaque; |
2939 | 5eb7995e | j_mayer | /* XXX: some of those flags initialisation values could depend
|
2940 | 5eb7995e | j_mayer | * on the actual PowerPC implementation
|
2941 | 5eb7995e | j_mayer | */
|
2942 | 5eb7995e | j_mayer | for (i = 0; i < 63; i++) |
2943 | 5eb7995e | j_mayer | env->msr[i] = 0;
|
2944 | 5eb7995e | j_mayer | #if defined(TARGET_PPC64)
|
2945 | 5eb7995e | j_mayer | msr_hv = 0; /* Should be 1... */ |
2946 | 5eb7995e | j_mayer | #endif
|
2947 | 5eb7995e | j_mayer | msr_ap = 0; /* TO BE CHECKED */ |
2948 | 5eb7995e | j_mayer | msr_sa = 0; /* TO BE CHECKED */ |
2949 | 4e80effc | j_mayer | msr_ep = 1;
|
2950 | 0a032cbe | j_mayer | #if defined (DO_SINGLE_STEP) && 0 |
2951 | 0a032cbe | j_mayer | /* Single step trace mode */
|
2952 | 0a032cbe | j_mayer | msr_se = 1;
|
2953 | 0a032cbe | j_mayer | msr_be = 1;
|
2954 | 0a032cbe | j_mayer | #endif
|
2955 | 0a032cbe | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2956 | 5eb7995e | j_mayer | msr_fp = 1; /* Allow floating point exceptions */ |
2957 | 0a032cbe | j_mayer | msr_pr = 1;
|
2958 | 0a032cbe | j_mayer | #else
|
2959 | 1c27f8fb | j_mayer | env->nip = env->hreset_vector | env->excp_prefix; |
2960 | 141c8ae2 | j_mayer | if (env->mmu_model != POWERPC_MMU_REAL_4xx)
|
2961 | 141c8ae2 | j_mayer | ppc_tlb_invalidate_all(env); |
2962 | 0a032cbe | j_mayer | #endif
|
2963 | 0a032cbe | j_mayer | do_compute_hflags(env); |
2964 | 0a032cbe | j_mayer | env->reserve = -1;
|
2965 | 5eb7995e | j_mayer | /* Be sure no exception or interrupt is pending */
|
2966 | 5eb7995e | j_mayer | env->pending_interrupts = 0;
|
2967 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2968 | e1833e1f | j_mayer | env->error_code = 0;
|
2969 | 5eb7995e | j_mayer | /* Flush all TLBs */
|
2970 | 5eb7995e | j_mayer | tlb_flush(env, 1);
|
2971 | 0a032cbe | j_mayer | } |
2972 | 0a032cbe | j_mayer | |
2973 | 0a032cbe | j_mayer | CPUPPCState *cpu_ppc_init (void)
|
2974 | 0a032cbe | j_mayer | { |
2975 | 0a032cbe | j_mayer | CPUPPCState *env; |
2976 | 0a032cbe | j_mayer | |
2977 | 0a032cbe | j_mayer | env = qemu_mallocz(sizeof(CPUPPCState));
|
2978 | 0a032cbe | j_mayer | if (!env)
|
2979 | 0a032cbe | j_mayer | return NULL; |
2980 | 0a032cbe | j_mayer | cpu_exec_init(env); |
2981 | 0a032cbe | j_mayer | |
2982 | 0a032cbe | j_mayer | return env;
|
2983 | 0a032cbe | j_mayer | } |
2984 | 0a032cbe | j_mayer | |
2985 | 0a032cbe | j_mayer | void cpu_ppc_close (CPUPPCState *env)
|
2986 | 0a032cbe | j_mayer | { |
2987 | 0a032cbe | j_mayer | /* Should also remove all opcode tables... */
|
2988 | 0a032cbe | j_mayer | free(env); |
2989 | 0a032cbe | j_mayer | } |