Revision b26eefb6 target-arm/cpu.h
| b/target-arm/cpu.h | ||
|---|---|---|
| 89 | 89 |
uint32_t NZF; /* N is bit 31. Z is computed from NZF */ |
| 90 | 90 |
uint32_t QF; /* 0 or 1 */ |
| 91 | 91 |
uint32_t GE; /* cpsr[19:16] */ |
| 92 |
int thumb; /* cprs[5]. 0 = arm mode, 1 = thumb mode. */
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| 92 |
uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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| 93 | 93 |
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
| 94 | 94 |
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| 95 | 95 |
/* System control coprocessor (cp15) */ |
| ... | ... | |
| 207 | 207 |
} CPUARMState; |
| 208 | 208 |
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| 209 | 209 |
CPUARMState *cpu_arm_init(const char *cpu_model); |
| 210 |
void arm_translate_init(void); |
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| 210 | 211 |
int cpu_arm_exec(CPUARMState *s); |
| 211 | 212 |
void cpu_arm_close(CPUARMState *s); |
| 212 | 213 |
void do_interrupt(CPUARMState *); |
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