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/*
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* OMAP on-chip MMC/SD host emulation.
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*
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "vl.h"
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#include "sd.h"
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struct omap_mmc_s {
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target_phys_addr_t base;
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qemu_irq irq;
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qemu_irq *dma;
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omap_clk clk;
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SDState *card;
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uint16_t last_cmd;
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uint16_t sdio;
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uint16_t rsp[8];
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uint32_t arg;
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int dw;
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int mode;
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int enable;
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uint16_t status;
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uint16_t mask;
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uint8_t cto;
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uint16_t dto;
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uint16_t fifo[32];
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int fifo_start;
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int fifo_len;
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uint16_t blen;
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uint16_t blen_counter;
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uint16_t nblk;
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uint16_t nblk_counter;
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int tx_dma;
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int rx_dma;
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int af_level;
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int ae_level;
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int ddir;
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int transfer;
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};
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static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
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{
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qemu_set_irq(s->irq, !!(s->status & s->mask));
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}
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static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
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{
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if (!host->transfer && !host->fifo_len) {
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host->status &= 0xf3ff;
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return;
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}
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if (host->fifo_len > host->af_level && host->ddir) {
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if (host->rx_dma) {
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host->status &= 0xfbff;
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qemu_irq_raise(host->dma[1]);
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} else
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host->status |= 0x0400;
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} else {
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host->status &= 0xfbff;
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qemu_irq_lower(host->dma[1]);
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}
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if (host->fifo_len < host->ae_level && !host->ddir) {
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if (host->tx_dma) {
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host->status &= 0xf7ff;
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qemu_irq_raise(host->dma[0]);
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} else
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host->status |= 0x0800;
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} else {
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qemu_irq_lower(host->dma[0]);
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host->status &= 0xf7ff;
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}
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}
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typedef enum {
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sd_nore = 0, /* no response */
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sd_r1, /* normal response command */
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sd_r2, /* CID, CSD registers */
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sd_r3, /* OCR register */
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sd_r6 = 6, /* Published RCA response */
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sd_r1b = -1,
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} sd_rsp_type_t;
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static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
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sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
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{
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uint32_t rspstatus, mask;
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int rsplen, timeout;
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struct sd_request_s request;
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uint8_t response[16];
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if (resptype == sd_r1 && busy)
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resptype = sd_r1b;
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if (type == sd_adtc) {
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host->fifo_start = 0;
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host->fifo_len = 0;
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host->transfer = 1;
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host->ddir = dir;
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} else
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host->transfer = 0;
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timeout = 0;
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mask = 0;
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rspstatus = 0;
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request.cmd = cmd;
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request.arg = host->arg;
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request.crc = 0; /* FIXME */
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rsplen = sd_do_command(host->card, &request, response);
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/* TODO: validate CRCs */
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switch (resptype) {
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case sd_nore:
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rsplen = 0;
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break;
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case sd_r1:
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case sd_r1b:
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if (rsplen < 4) {
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timeout = 1;
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break;
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}
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rsplen = 4;
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mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
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ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
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LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
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CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
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CID_CSD_OVERWRITE;
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if (host->sdio & (1 << 13))
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mask |= AKE_SEQ_ERROR;
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rspstatus = (response[0] << 24) | (response[1] << 16) |
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(response[2] << 8) | (response[3] << 0);
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break;
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case sd_r2:
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if (rsplen < 16) {
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timeout = 1;
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break;
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}
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rsplen = 16;
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break;
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case sd_r3:
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if (rsplen < 4) {
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timeout = 1;
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break;
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}
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rsplen = 4;
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rspstatus = (response[0] << 24) | (response[1] << 16) |
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(response[2] << 8) | (response[3] << 0);
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if (rspstatus & 0x80000000)
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host->status &= 0xe000;
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else
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host->status |= 0x1000;
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break;
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case sd_r6:
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if (rsplen < 4) {
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timeout = 1;
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break;
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}
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rsplen = 4;
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mask = 0xe000 | AKE_SEQ_ERROR;
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rspstatus = (response[2] << 8) | (response[3] << 0);
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}
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if (rspstatus & mask)
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host->status |= 0x4000;
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else
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host->status &= 0xb000;
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if (rsplen)
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for (rsplen = 0; rsplen < 8; rsplen ++)
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host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
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(response[(rsplen << 1) | 0] << 8);
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if (timeout)
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host->status |= 0x0080;
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else if (cmd == 12)
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host->status |= 0x0005; /* Makes it more real */
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else
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host->status |= 0x0001;
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}
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static void omap_mmc_transfer(struct omap_mmc_s *host)
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{
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uint8_t value;
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if (!host->transfer)
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return;
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while (1) {
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if (host->ddir) {
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if (host->fifo_len > host->af_level)
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break;
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value = sd_read_data(host->card);
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host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
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if (-- host->blen_counter) {
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value = sd_read_data(host->card);
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host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
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value << 8;
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host->blen_counter --;
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}
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host->fifo_len ++;
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} else {
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if (!host->fifo_len)
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break;
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value = host->fifo[host->fifo_start] & 0xff;
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sd_write_data(host->card, value);
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if (-- host->blen_counter) {
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value = host->fifo[host->fifo_start] >> 8;
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sd_write_data(host->card, value);
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host->blen_counter --;
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}
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host->fifo_start ++;
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host->fifo_len --;
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host->fifo_start &= 31;
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}
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if (host->blen_counter == 0) {
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host->nblk_counter --;
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host->blen_counter = host->blen;
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if (host->nblk_counter == 0) {
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host->nblk_counter = host->nblk;
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host->transfer = 0;
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host->status |= 0x0008;
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break;
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}
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}
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}
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}
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static void omap_mmc_update(void *opaque)
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{
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struct omap_mmc_s *s = opaque;
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omap_mmc_transfer(s);
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omap_mmc_fifolevel_update(s);
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omap_mmc_interrupts_update(s);
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}
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static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
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{
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uint16_t i;
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struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
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offset -= s->base;
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switch (offset) {
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case 0x00: /* MMC_CMD */
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return s->last_cmd;
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case 0x04: /* MMC_ARGL */
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return s->arg & 0x0000ffff;
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case 0x08: /* MMC_ARGH */
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return s->arg >> 16;
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case 0x0c: /* MMC_CON */
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return (s->dw << 15) | (s->mode << 12) | (s->enable << 11);
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case 0x10: /* MMC_STAT */
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return s->status;
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case 0x14: /* MMC_IE */
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return s->mask;
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case 0x18: /* MMC_CTO */
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return s->cto;
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case 0x1c: /* MMC_DTO */
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return s->dto;
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case 0x20: /* MMC_DATA */
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/* TODO: support 8-bit access */
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i = s->fifo[s->fifo_start];
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if (s->fifo_len == 0) {
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printf("MMC: FIFO underrun\n");
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return i;
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}
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s->fifo_start ++;
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s->fifo_len --;
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s->fifo_start &= 31;
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omap_mmc_transfer(s);
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omap_mmc_fifolevel_update(s);
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omap_mmc_interrupts_update(s);
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return i;
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312 |
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case 0x24: /* MMC_BLEN */
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return s->blen_counter;
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case 0x28: /* MMC_NBLK */
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return s->nblk_counter;
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319 |
case 0x2c: /* MMC_BUF */
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320 |
return (s->rx_dma << 15) | (s->af_level << 8) |
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(s->tx_dma << 7) | s->ae_level;
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322 |
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323 |
case 0x30: /* MMC_SPI */
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return 0x0000;
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case 0x34: /* MMC_SDIO */
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return s->sdio;
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327 |
case 0x38: /* MMC_SYST */
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328 |
return 0x0000;
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329 |
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330 |
case 0x3c: /* MMC_REV */
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331 |
return 0x0001;
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332 |
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333 |
case 0x40: /* MMC_RSP0 */
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case 0x44: /* MMC_RSP1 */
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case 0x48: /* MMC_RSP2 */
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336 |
case 0x4c: /* MMC_RSP3 */
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337 |
case 0x50: /* MMC_RSP4 */
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338 |
case 0x54: /* MMC_RSP5 */
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339 |
case 0x58: /* MMC_RSP6 */
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340 |
case 0x5c: /* MMC_RSP7 */
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341 |
return s->rsp[(offset - 0x40) >> 2];
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342 |
}
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343 |
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344 |
OMAP_BAD_REG(offset);
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345 |
return 0;
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346 |
}
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347 |
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348 |
static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
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349 |
uint32_t value)
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350 |
{
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351 |
int i;
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352 |
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
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353 |
offset -= s->base;
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354 |
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355 |
switch (offset) {
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356 |
case 0x00: /* MMC_CMD */
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357 |
if (!s->enable)
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358 |
break;
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359 |
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360 |
s->last_cmd = value;
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361 |
for (i = 0; i < 8; i ++)
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362 |
s->rsp[i] = 0x0000;
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363 |
omap_mmc_command(s, value & 63, (value >> 15) & 1,
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364 |
(sd_cmd_type_t) ((value >> 12) & 3),
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365 |
(value >> 11) & 1,
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366 |
(sd_rsp_type_t) ((value >> 8) & 7),
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367 |
(value >> 7) & 1);
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368 |
omap_mmc_update(s);
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369 |
break;
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370 |
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371 |
case 0x04: /* MMC_ARGL */
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372 |
s->arg &= 0xffff0000;
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373 |
s->arg |= 0x0000ffff & value;
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374 |
break;
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375 |
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376 |
case 0x08: /* MMC_ARGH */
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377 |
s->arg &= 0x0000ffff;
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378 |
s->arg |= value << 16;
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379 |
break;
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380 |
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381 |
case 0x0c: /* MMC_CON */
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382 |
s->dw = (value >> 15) & 1;
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383 |
s->mode = (value >> 12) & 3;
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|
384 |
s->enable = (value >> 11) & 1;
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385 |
if (s->mode != 0)
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386 |
printf("SD mode %i unimplemented!\n", s->mode);
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387 |
if (s->dw != 0)
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388 |
printf("4-bit SD bus enabled\n");
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|
389 |
break;
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390 |
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391 |
case 0x10: /* MMC_STAT */
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392 |
s->status &= ~value;
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393 |
omap_mmc_interrupts_update(s);
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|
394 |
break;
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395 |
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396 |
case 0x14: /* MMC_IE */
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397 |
s->mask = value;
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398 |
omap_mmc_interrupts_update(s);
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399 |
break;
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|
400 |
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|
401 |
case 0x18: /* MMC_CTO */
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402 |
s->cto = value & 0xff;
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|
403 |
if (s->cto > 0xfd)
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|
404 |
printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
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|
405 |
break;
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406 |
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|
407 |
case 0x1c: /* MMC_DTO */
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408 |
s->dto = value & 0xffff;
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|
409 |
break;
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|
410 |
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|
411 |
case 0x20: /* MMC_DATA */
|
|
412 |
/* TODO: support 8-bit access */
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|
413 |
if (s->fifo_len == 32)
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|
414 |
break;
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|
415 |
s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
|
|
416 |
s->fifo_len ++;
|
|
417 |
omap_mmc_transfer(s);
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|
418 |
omap_mmc_fifolevel_update(s);
|
|
419 |
omap_mmc_interrupts_update(s);
|
|
420 |
break;
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|
421 |
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|
422 |
case 0x24: /* MMC_BLEN */
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423 |
s->blen = (value & 0x07ff) + 1;
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|
424 |
s->blen_counter = s->blen;
|
|
425 |
break;
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|
426 |
|
|
427 |
case 0x28: /* MMC_NBLK */
|
|
428 |
s->nblk = (value & 0x07ff) + 1;
|
|
429 |
s->nblk_counter = s->nblk;
|
|
430 |
s->blen_counter = s->blen;
|
|
431 |
break;
|
|
432 |
|
|
433 |
case 0x2c: /* MMC_BUF */
|
|
434 |
s->rx_dma = (value >> 15) & 1;
|
|
435 |
s->af_level = (value >> 8) & 0x1f;
|
|
436 |
s->tx_dma = (value >> 7) & 1;
|
|
437 |
s->ae_level = value & 0x1f;
|
|
438 |
|
|
439 |
if (s->rx_dma)
|
|
440 |
s->status &= 0xfbff;
|
|
441 |
if (s->tx_dma)
|
|
442 |
s->status &= 0xf7ff;
|
|
443 |
omap_mmc_fifolevel_update(s);
|
|
444 |
omap_mmc_interrupts_update(s);
|
|
445 |
break;
|
|
446 |
|
|
447 |
/* SPI, SDIO and TEST modes unimplemented */
|
|
448 |
case 0x30: /* MMC_SPI */
|
|
449 |
break;
|
|
450 |
case 0x34: /* MMC_SDIO */
|
|
451 |
s->sdio = value & 0x2020;
|
|
452 |
break;
|
|
453 |
case 0x38: /* MMC_SYST */
|
|
454 |
break;
|
|
455 |
|
|
456 |
case 0x3c: /* MMC_REV */
|
|
457 |
case 0x40: /* MMC_RSP0 */
|
|
458 |
case 0x44: /* MMC_RSP1 */
|
|
459 |
case 0x48: /* MMC_RSP2 */
|
|
460 |
case 0x4c: /* MMC_RSP3 */
|
|
461 |
case 0x50: /* MMC_RSP4 */
|
|
462 |
case 0x54: /* MMC_RSP5 */
|
|
463 |
case 0x58: /* MMC_RSP6 */
|
|
464 |
case 0x5c: /* MMC_RSP7 */
|
|
465 |
OMAP_RO_REG(offset);
|
|
466 |
break;
|
|
467 |
|
|
468 |
default:
|
|
469 |
OMAP_BAD_REG(offset);
|
|
470 |
}
|
|
471 |
}
|
|
472 |
|
|
473 |
static CPUReadMemoryFunc *omap_mmc_readfn[] = {
|
|
474 |
omap_badwidth_read16,
|
|
475 |
omap_mmc_read,
|
|
476 |
omap_badwidth_read16,
|
|
477 |
};
|
|
478 |
|
|
479 |
static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
|
|
480 |
omap_badwidth_write16,
|
|
481 |
omap_mmc_write,
|
|
482 |
omap_badwidth_write16,
|
|
483 |
};
|
|
484 |
|
|
485 |
void omap_mmc_reset(struct omap_mmc_s *host)
|
|
486 |
{
|
|
487 |
host->last_cmd = 0;
|
|
488 |
memset(host->rsp, 0, sizeof(host->rsp));
|
|
489 |
host->arg = 0;
|
|
490 |
host->dw = 0;
|
|
491 |
host->mode = 0;
|
|
492 |
host->enable = 0;
|
|
493 |
host->status = 0;
|
|
494 |
host->mask = 0;
|
|
495 |
host->cto = 0;
|
|
496 |
host->dto = 0;
|
|
497 |
host->fifo_len = 0;
|
|
498 |
host->blen = 0;
|
|
499 |
host->blen_counter = 0;
|
|
500 |
host->nblk = 0;
|
|
501 |
host->nblk_counter = 0;
|
|
502 |
host->tx_dma = 0;
|
|
503 |
host->rx_dma = 0;
|
|
504 |
host->ae_level = 0x00;
|
|
505 |
host->af_level = 0x1f;
|
|
506 |
host->transfer = 0;
|
|
507 |
}
|
|
508 |
|
|
509 |
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
|
510 |
qemu_irq irq, qemu_irq dma[], omap_clk clk)
|
|
511 |
{
|
|
512 |
int iomemtype;
|
|
513 |
struct omap_mmc_s *s = (struct omap_mmc_s *)
|
|
514 |
qemu_mallocz(sizeof(struct omap_mmc_s));
|
|
515 |
|
|
516 |
s->irq = irq;
|
|
517 |
s->base = base;
|
|
518 |
s->dma = dma;
|
|
519 |
s->clk = clk;
|
|
520 |
|
|
521 |
iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
|
|
522 |
omap_mmc_writefn, s);
|
|
523 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
|
524 |
|
|
525 |
/* Instantiate the storage */
|
|
526 |
s->card = sd_init(sd_bdrv);
|
|
527 |
|
|
528 |
return s;
|
|
529 |
}
|
|
530 |
|
|
531 |
/* TODO: insertion and read-only handlers */
|