Revision b30bb3a2 hw/omap.c
| b/hw/omap.c | ||
|---|---|---|
| 22 | 22 |
#include "arm_pic.h" |
| 23 | 23 |
|
| 24 | 24 |
/* Should signal the TCMI */ |
| 25 |
static uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
|
|
| 25 |
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) |
|
| 26 | 26 |
{
|
| 27 | 27 |
OMAP_16B_REG(addr); |
| 28 | 28 |
return 0; |
| 29 | 29 |
} |
| 30 | 30 |
|
| 31 |
static void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
|
|
| 31 |
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
|
| 32 | 32 |
uint32_t value) |
| 33 | 33 |
{
|
| 34 | 34 |
OMAP_16B_REG(addr); |
| 35 | 35 |
} |
| 36 | 36 |
|
| 37 |
static uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
|
|
| 37 |
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr) |
|
| 38 | 38 |
{
|
| 39 | 39 |
OMAP_32B_REG(addr); |
| 40 | 40 |
return 0; |
| 41 | 41 |
} |
| 42 | 42 |
|
| 43 |
static void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
|
|
| 43 |
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
|
| 44 | 44 |
uint32_t value) |
| 45 | 45 |
{
|
| 46 | 46 |
OMAP_32B_REG(addr); |
| ... | ... | |
| 2816 | 2816 |
omap_uart_reset(mpu->uart1); |
| 2817 | 2817 |
omap_uart_reset(mpu->uart2); |
| 2818 | 2818 |
omap_uart_reset(mpu->uart3); |
| 2819 |
omap_mmc_reset(mpu->mmc); |
|
| 2819 | 2820 |
cpu_reset(mpu->env); |
| 2820 | 2821 |
} |
| 2821 | 2822 |
|
| ... | ... | |
| 2921 | 2922 |
omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
| 2922 | 2923 |
omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
| 2923 | 2924 |
|
| 2925 |
s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN], |
|
| 2926 |
&s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck")); |
|
| 2927 |
|
|
| 2924 | 2928 |
qemu_register_reset(omap_mpu_reset, s); |
| 2925 | 2929 |
s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
| 2926 | 2930 |
|
Also available in: Unified diff