Revision b30bb3a2 hw/omap.h
| b/hw/omap.h | ||
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| 163 | 163 |
# define OMAP_INT_USB_W2FC 20 |
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# define OMAP_INT_1WIRE 21 |
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# define OMAP_INT_OS_TIMER 22 |
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# define OMAP_INT_MMC 23
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# define OMAP_INT_OQN 23
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# define OMAP_INT_GAUGE_32K 24 |
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# define OMAP_INT_RTC_TIMER 25 |
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# define OMAP_INT_RTC_ALARM 26 |
| ... | ... | |
| 457 | 457 |
struct omap_dma_lcd_channel_s *dma, DisplayState *ds, |
| 458 | 458 |
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
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/* omap_mmc.c */ |
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struct omap_mmc_s; |
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struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, |
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qemu_irq irq, qemu_irq dma[], omap_clk clk); |
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void omap_mmc_reset(struct omap_mmc_s *s); |
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# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) |
| 461 | 467 |
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) |
| 462 | 468 |
# define cpu_is_omap15xx(cpu) \ |
| ... | ... | |
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struct omap_uart_s *uart1; |
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struct omap_uart_s *uart2; |
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struct omap_mmc_s *mmc; |
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/* MPU private TIPB peripherals */ |
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struct omap_intr_handler_s *ih[2]; |
| 502 | 510 |
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| ... | ... | |
| 566 | 574 |
# error TARGET_PHYS_ADDR_BITS undefined |
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# endif |
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uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr); |
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void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
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uint32_t value); |
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uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr); |
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void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
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uint32_t value); |
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# define OMAP_BAD_REG(paddr) \ |
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printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)
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| 571 | 586 |
# define OMAP_RO_REG(paddr) \ |
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