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1
/*
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 * Texas Instruments OMAP processors.
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 *
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 * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 * MA 02111-1307 USA
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 */
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#ifndef hw_omap_h
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# define hw_omap_h                "omap.h"
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# define OMAP_EMIFS_BASE        0x00000000
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# define OMAP_CS0_BASE                0x00000000
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# define OMAP_CS1_BASE                0x04000000
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# define OMAP_CS2_BASE                0x08000000
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# define OMAP_CS3_BASE                0x0c000000
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# define OMAP_EMIFF_BASE        0x10000000
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# define OMAP_IMIF_BASE                0x20000000
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# define OMAP_LOCALBUS_BASE        0x30000000
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# define OMAP_MPUI_BASE                0xe1000000
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# define OMAP730_SRAM_SIZE        0x00032000
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# define OMAP15XX_SRAM_SIZE        0x00030000
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# define OMAP16XX_SRAM_SIZE        0x00004000
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# define OMAP1611_SRAM_SIZE        0x0003e800
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# define OMAP_CS0_SIZE                0x04000000
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# define OMAP_CS1_SIZE                0x04000000
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# define OMAP_CS2_SIZE                0x04000000
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# define OMAP_CS3_SIZE                0x04000000
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43
/* omap1_clk.c */
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struct omap_mpu_state_s;
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typedef struct clk *omap_clk;
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omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
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void omap_clk_init(struct omap_mpu_state_s *mpu);
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void omap_clk_adduser(struct clk *clk, qemu_irq user);
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void omap_clk_get(omap_clk clk);
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void omap_clk_put(omap_clk clk);
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void omap_clk_onoff(omap_clk clk, int on);
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void omap_clk_canidle(omap_clk clk, int can);
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void omap_clk_setrate(omap_clk clk, int divide, int multiply);
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int64_t omap_clk_getrate(omap_clk clk);
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void omap_clk_reparent(omap_clk clk, omap_clk parent);
56

    
57
/* omap.c */
58
struct omap_intr_handler_s;
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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                unsigned long size, qemu_irq parent[2], omap_clk clk);
61

    
62
/*
63
 * Common IRQ numbers for level 1 interrupt handler
64
 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
65
 */
66
# define OMAP_INT_CAMERA                1
67
# define OMAP_INT_FIQ                        3
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# define OMAP_INT_RTDX                        6
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# define OMAP_INT_DSP_MMU_ABORT                7
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# define OMAP_INT_HOST                        8
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# define OMAP_INT_ABORT                        9
72
# define OMAP_INT_BRIDGE_PRIV                13
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# define OMAP_INT_GPIO_BANK1                14
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# define OMAP_INT_UART3                        15
75
# define OMAP_INT_TIMER3                16
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# define OMAP_INT_DMA_CH0_6                19
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# define OMAP_INT_DMA_CH1_7                20
78
# define OMAP_INT_DMA_CH2_8                21
79
# define OMAP_INT_DMA_CH3                22
80
# define OMAP_INT_DMA_CH4                23
81
# define OMAP_INT_DMA_CH5                24
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# define OMAP_INT_DMA_LCD                25
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# define OMAP_INT_TIMER1                26
84
# define OMAP_INT_WD_TIMER                27
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# define OMAP_INT_BRIDGE_PUB                28
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# define OMAP_INT_TIMER2                30
87
# define OMAP_INT_LCD_CTRL                31
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89
/*
90
 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
91
 */
92
# define OMAP_INT_15XX_IH2_IRQ                0
93
# define OMAP_INT_15XX_LB_MMU                17
94
# define OMAP_INT_15XX_LOCAL_BUS        29
95

    
96
/*
97
 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
98
 */
99
# define OMAP_INT_1510_SPI_TX                4
100
# define OMAP_INT_1510_SPI_RX                5
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# define OMAP_INT_1510_DSP_MAILBOX1        10
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# define OMAP_INT_1510_DSP_MAILBOX2        11
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104
/*
105
 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
106
 */
107
# define OMAP_INT_310_McBSP2_TX                4
108
# define OMAP_INT_310_McBSP2_RX                5
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# define OMAP_INT_310_HSB_MAILBOX1        12
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# define OMAP_INT_310_HSAB_MMU                18
111

    
112
/*
113
 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
114
 */
115
# define OMAP_INT_1610_IH2_IRQ                0
116
# define OMAP_INT_1610_IH2_FIQ                2
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# define OMAP_INT_1610_McBSP2_TX        4
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# define OMAP_INT_1610_McBSP2_RX        5
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# define OMAP_INT_1610_DSP_MAILBOX1        10
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# define OMAP_INT_1610_DSP_MAILBOX2        11
121
# define OMAP_INT_1610_LCD_LINE                12
122
# define OMAP_INT_1610_GPTIMER1                17
123
# define OMAP_INT_1610_GPTIMER2                18
124
# define OMAP_INT_1610_SSR_FIFO_0        29
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126
/*
127
 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
128
 */
129
# define OMAP_INT_730_IH2_FIQ                0
130
# define OMAP_INT_730_IH2_IRQ                1
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# define OMAP_INT_730_USB_NON_ISO        2
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# define OMAP_INT_730_USB_ISO                3
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# define OMAP_INT_730_ICR                4
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# define OMAP_INT_730_EAC                5
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# define OMAP_INT_730_GPIO_BANK1        6
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# define OMAP_INT_730_GPIO_BANK2        7
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# define OMAP_INT_730_GPIO_BANK3        8
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# define OMAP_INT_730_McBSP2TX                10
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# define OMAP_INT_730_McBSP2RX                11
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# define OMAP_INT_730_McBSP2RX_OVF        12
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# define OMAP_INT_730_LCD_LINE                14
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# define OMAP_INT_730_GSM_PROTECT        15
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# define OMAP_INT_730_TIMER3                16
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# define OMAP_INT_730_GPIO_BANK5        17
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# define OMAP_INT_730_GPIO_BANK6        18
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# define OMAP_INT_730_SPGIO_WR                29
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148
/*
149
 * Common IRQ numbers for level 2 interrupt handler
150
 */
151
# define OMAP_INT_KEYBOARD                1
152
# define OMAP_INT_uWireTX                2
153
# define OMAP_INT_uWireRX                3
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# define OMAP_INT_I2C                        4
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# define OMAP_INT_MPUIO                        5
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# define OMAP_INT_USB_HHC_1                6
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# define OMAP_INT_McBSP3TX                10
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# define OMAP_INT_McBSP3RX                11
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# define OMAP_INT_McBSP1TX                12
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# define OMAP_INT_McBSP1RX                13
161
# define OMAP_INT_UART1                        14
162
# define OMAP_INT_UART2                        15
163
# define OMAP_INT_USB_W2FC                20
164
# define OMAP_INT_1WIRE                        21
165
# define OMAP_INT_OS_TIMER                22
166
# define OMAP_INT_OQN                        23
167
# define OMAP_INT_GAUGE_32K                24
168
# define OMAP_INT_RTC_TIMER                25
169
# define OMAP_INT_RTC_ALARM                26
170
# define OMAP_INT_DSP_MMU                28
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172
/*
173
 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
174
 */
175
# define OMAP_INT_1510_BT_MCSI1TX        16
176
# define OMAP_INT_1510_BT_MCSI1RX        17
177
# define OMAP_INT_1510_SoSSI_MATCH        19
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# define OMAP_INT_1510_MEM_STICK        27
179
# define OMAP_INT_1510_COM_SPI_RO        31
180

    
181
/*
182
 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
183
 */
184
# define OMAP_INT_310_FAC                0
185
# define OMAP_INT_310_USB_HHC_2                7
186
# define OMAP_INT_310_MCSI1_FE                16
187
# define OMAP_INT_310_MCSI2_FE                17
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# define OMAP_INT_310_USB_W2FC_ISO        29
189
# define OMAP_INT_310_USB_W2FC_NON_ISO        30
190
# define OMAP_INT_310_McBSP2RX_OF        31
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192
/*
193
 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
194
 */
195
# define OMAP_INT_1610_FAC                0
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# define OMAP_INT_1610_USB_HHC_2        7
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# define OMAP_INT_1610_USB_OTG                8
198
# define OMAP_INT_1610_SoSSI                9
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# define OMAP_INT_1610_BT_MCSI1TX        16
200
# define OMAP_INT_1610_BT_MCSI1RX        17
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# define OMAP_INT_1610_SoSSI_MATCH        19
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# define OMAP_INT_1610_MEM_STICK        27
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# define OMAP_INT_1610_McBSP2RX_OF        31
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# define OMAP_INT_1610_STI                32
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# define OMAP_INT_1610_STI_WAKEUP        33
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# define OMAP_INT_1610_GPTIMER3                34
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# define OMAP_INT_1610_GPTIMER4                35
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# define OMAP_INT_1610_GPTIMER5                36
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# define OMAP_INT_1610_GPTIMER6                37
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# define OMAP_INT_1610_GPTIMER7                38
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# define OMAP_INT_1610_GPTIMER8                39
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# define OMAP_INT_1610_GPIO_BANK2        40
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# define OMAP_INT_1610_GPIO_BANK3        41
214
# define OMAP_INT_1610_MMC2                42
215
# define OMAP_INT_1610_CF                43
216
# define OMAP_INT_1610_WAKE_UP_REQ        46
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# define OMAP_INT_1610_GPIO_BANK4        48
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# define OMAP_INT_1610_SPI                49
219
# define OMAP_INT_1610_DMA_CH6                53
220
# define OMAP_INT_1610_DMA_CH7                54
221
# define OMAP_INT_1610_DMA_CH8                55
222
# define OMAP_INT_1610_DMA_CH9                56
223
# define OMAP_INT_1610_DMA_CH10                57
224
# define OMAP_INT_1610_DMA_CH11                58
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# define OMAP_INT_1610_DMA_CH12                59
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# define OMAP_INT_1610_DMA_CH13                60
227
# define OMAP_INT_1610_DMA_CH14                61
228
# define OMAP_INT_1610_DMA_CH15                62
229
# define OMAP_INT_1610_NAND                63
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231
/*
232
 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
233
 */
234
# define OMAP_INT_730_HW_ERRORS                0
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# define OMAP_INT_730_NFIQ_PWR_FAIL        1
236
# define OMAP_INT_730_CFCD                2
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# define OMAP_INT_730_CFIREQ                3
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# define OMAP_INT_730_I2C                4
239
# define OMAP_INT_730_PCC                5
240
# define OMAP_INT_730_MPU_EXT_NIRQ        6
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# define OMAP_INT_730_SPI_100K_1        7
242
# define OMAP_INT_730_SYREN_SPI                8
243
# define OMAP_INT_730_VLYNQ                9
244
# define OMAP_INT_730_GPIO_BANK4        10
245
# define OMAP_INT_730_McBSP1TX                11
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# define OMAP_INT_730_McBSP1RX                12
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# define OMAP_INT_730_McBSP1RX_OF        13
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# define OMAP_INT_730_UART_MODEM_IRDA_2        14
249
# define OMAP_INT_730_UART_MODEM_1        15
250
# define OMAP_INT_730_MCSI                16
251
# define OMAP_INT_730_uWireTX                17
252
# define OMAP_INT_730_uWireRX                18
253
# define OMAP_INT_730_SMC_CD                19
254
# define OMAP_INT_730_SMC_IREQ                20
255
# define OMAP_INT_730_HDQ_1WIRE                21
256
# define OMAP_INT_730_TIMER32K                22
257
# define OMAP_INT_730_MMC_SDIO                23
258
# define OMAP_INT_730_UPLD                24
259
# define OMAP_INT_730_USB_HHC_1                27
260
# define OMAP_INT_730_USB_HHC_2                28
261
# define OMAP_INT_730_USB_GENI                29
262
# define OMAP_INT_730_USB_OTG                30
263
# define OMAP_INT_730_CAMERA_IF                31
264
# define OMAP_INT_730_RNG                32
265
# define OMAP_INT_730_DUAL_MODE_TIMER        33
266
# define OMAP_INT_730_DBB_RF_EN                34
267
# define OMAP_INT_730_MPUIO_KEYPAD        35
268
# define OMAP_INT_730_SHA1_MD5                36
269
# define OMAP_INT_730_SPI_100K_2        37
270
# define OMAP_INT_730_RNG_IDLE                38
271
# define OMAP_INT_730_MPUIO                39
272
# define OMAP_INT_730_LLPC_LCD_CTRL_OFF        40
273
# define OMAP_INT_730_LLPC_OE_FALLING        41
274
# define OMAP_INT_730_LLPC_OE_RISING        42
275
# define OMAP_INT_730_LLPC_VSYNC        43
276
# define OMAP_INT_730_WAKE_UP_REQ        46
277
# define OMAP_INT_730_DMA_CH6                53
278
# define OMAP_INT_730_DMA_CH7                54
279
# define OMAP_INT_730_DMA_CH8                55
280
# define OMAP_INT_730_DMA_CH9                56
281
# define OMAP_INT_730_DMA_CH10                57
282
# define OMAP_INT_730_DMA_CH11                58
283
# define OMAP_INT_730_DMA_CH12                59
284
# define OMAP_INT_730_DMA_CH13                60
285
# define OMAP_INT_730_DMA_CH14                61
286
# define OMAP_INT_730_DMA_CH15                62
287
# define OMAP_INT_730_NAND                63
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/*
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 * OMAP-24xx common IRQ numbers
291
 */
292
# define OMAP_INT_24XX_SYS_NIRQ                7
293
# define OMAP_INT_24XX_SDMA_IRQ0        12
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# define OMAP_INT_24XX_SDMA_IRQ1        13
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# define OMAP_INT_24XX_SDMA_IRQ2        14
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# define OMAP_INT_24XX_SDMA_IRQ3        15
297
# define OMAP_INT_24XX_CAM_IRQ                24
298
# define OMAP_INT_24XX_DSS_IRQ                25
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# define OMAP_INT_24XX_MAIL_U0_MPU        26
300
# define OMAP_INT_24XX_DSP_UMA                27
301
# define OMAP_INT_24XX_DSP_MMU                28
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# define OMAP_INT_24XX_GPIO_BANK1        29
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# define OMAP_INT_24XX_GPIO_BANK2        30
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# define OMAP_INT_24XX_GPIO_BANK3        31
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# define OMAP_INT_24XX_GPIO_BANK4        32
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# define OMAP_INT_24XX_GPIO_BANK5        33
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# define OMAP_INT_24XX_MAIL_U3_MPU        34
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# define OMAP_INT_24XX_GPTIMER1                37
309
# define OMAP_INT_24XX_GPTIMER2                38
310
# define OMAP_INT_24XX_GPTIMER3                39
311
# define OMAP_INT_24XX_GPTIMER4                40
312
# define OMAP_INT_24XX_GPTIMER5                41
313
# define OMAP_INT_24XX_GPTIMER6                42
314
# define OMAP_INT_24XX_GPTIMER7                43
315
# define OMAP_INT_24XX_GPTIMER8                44
316
# define OMAP_INT_24XX_GPTIMER9                45
317
# define OMAP_INT_24XX_GPTIMER10        46
318
# define OMAP_INT_24XX_GPTIMER11        47
319
# define OMAP_INT_24XX_GPTIMER12        48
320
# define OMAP_INT_24XX_MCBSP1_IRQ_TX        59
321
# define OMAP_INT_24XX_MCBSP1_IRQ_RX        60
322
# define OMAP_INT_24XX_MCBSP2_IRQ_TX        62
323
# define OMAP_INT_24XX_MCBSP2_IRQ_RX        63
324
# define OMAP_INT_24XX_UART1_IRQ        72
325
# define OMAP_INT_24XX_UART2_IRQ        73
326
# define OMAP_INT_24XX_UART3_IRQ        74
327
# define OMAP_INT_24XX_USB_IRQ_GEN        75
328
# define OMAP_INT_24XX_USB_IRQ_NISO        76
329
# define OMAP_INT_24XX_USB_IRQ_ISO        77
330
# define OMAP_INT_24XX_USB_IRQ_HGEN        78
331
# define OMAP_INT_24XX_USB_IRQ_HSOF        79
332
# define OMAP_INT_24XX_USB_IRQ_OTG        80
333
# define OMAP_INT_24XX_MMC_IRQ                83
334
# define OMAP_INT_243X_HS_USB_MC        92
335
# define OMAP_INT_243X_HS_USB_DMA        93
336
# define OMAP_INT_243X_CARKIT                94
337

    
338
struct omap_dma_s;
339
struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
340
                qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk);
341

    
342
enum omap_dma_port {
343
    emiff = 0,
344
    emifs,
345
    imif,
346
    tipb,
347
    local,
348
    tipb_mpui,
349
    omap_dma_port_last,
350
};
351

    
352
struct omap_dma_lcd_channel_s {
353
    enum omap_dma_port src;
354
    target_phys_addr_t src_f1_top;
355
    target_phys_addr_t src_f1_bottom;
356
    target_phys_addr_t src_f2_top;
357
    target_phys_addr_t src_f2_bottom;
358
    /* Destination port is fixed.  */
359
    int interrupts;
360
    int condition;
361
    int dual;
362

    
363
    int current_frame;
364
    ram_addr_t phys_framebuffer[2];
365
    qemu_irq irq;
366
    struct omap_mpu_state_s *mpu;
367
};
368

    
369
/*
370
 * DMA request numbers for OMAP1
371
 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
372
 */
373
# define OMAP_DMA_NO_DEVICE                0
374
# define OMAP_DMA_MCSI1_TX                1
375
# define OMAP_DMA_MCSI1_RX                2
376
# define OMAP_DMA_I2C_RX                3
377
# define OMAP_DMA_I2C_TX                4
378
# define OMAP_DMA_EXT_NDMA_REQ0                5
379
# define OMAP_DMA_EXT_NDMA_REQ1                6
380
# define OMAP_DMA_UWIRE_TX                7
381
# define OMAP_DMA_MCBSP1_TX                8
382
# define OMAP_DMA_MCBSP1_RX                9
383
# define OMAP_DMA_MCBSP3_TX                10
384
# define OMAP_DMA_MCBSP3_RX                11
385
# define OMAP_DMA_UART1_TX                12
386
# define OMAP_DMA_UART1_RX                13
387
# define OMAP_DMA_UART2_TX                14
388
# define OMAP_DMA_UART2_RX                15
389
# define OMAP_DMA_MCBSP2_TX                16
390
# define OMAP_DMA_MCBSP2_RX                17
391
# define OMAP_DMA_UART3_TX                18
392
# define OMAP_DMA_UART3_RX                19
393
# define OMAP_DMA_CAMERA_IF_RX                20
394
# define OMAP_DMA_MMC_TX                21
395
# define OMAP_DMA_MMC_RX                22
396
# define OMAP_DMA_NAND                        23        /* Not in OMAP310 */
397
# define OMAP_DMA_IRQ_LCD_LINE                24        /* Not in OMAP310 */
398
# define OMAP_DMA_MEMORY_STICK                25        /* Not in OMAP310 */
399
# define OMAP_DMA_USB_W2FC_RX0                26
400
# define OMAP_DMA_USB_W2FC_RX1                27
401
# define OMAP_DMA_USB_W2FC_RX2                28
402
# define OMAP_DMA_USB_W2FC_TX0                29
403
# define OMAP_DMA_USB_W2FC_TX1                30
404
# define OMAP_DMA_USB_W2FC_TX2                31
405

    
406
/* These are only for 1610 */
407
# define OMAP_DMA_CRYPTO_DES_IN                32
408
# define OMAP_DMA_SPI_TX                33
409
# define OMAP_DMA_SPI_RX                34
410
# define OMAP_DMA_CRYPTO_HASH                35
411
# define OMAP_DMA_CCP_ATTN                36
412
# define OMAP_DMA_CCP_FIFO_NOT_EMPTY        37
413
# define OMAP_DMA_CMT_APE_TX_CHAN_0        38
414
# define OMAP_DMA_CMT_APE_RV_CHAN_0        39
415
# define OMAP_DMA_CMT_APE_TX_CHAN_1        40
416
# define OMAP_DMA_CMT_APE_RV_CHAN_1        41
417
# define OMAP_DMA_CMT_APE_TX_CHAN_2        42
418
# define OMAP_DMA_CMT_APE_RV_CHAN_2        43
419
# define OMAP_DMA_CMT_APE_TX_CHAN_3        44
420
# define OMAP_DMA_CMT_APE_RV_CHAN_3        45
421
# define OMAP_DMA_CMT_APE_TX_CHAN_4        46
422
# define OMAP_DMA_CMT_APE_RV_CHAN_4        47
423
# define OMAP_DMA_CMT_APE_TX_CHAN_5        48
424
# define OMAP_DMA_CMT_APE_RV_CHAN_5        49
425
# define OMAP_DMA_CMT_APE_TX_CHAN_6        50
426
# define OMAP_DMA_CMT_APE_RV_CHAN_6        51
427
# define OMAP_DMA_CMT_APE_TX_CHAN_7        52
428
# define OMAP_DMA_CMT_APE_RV_CHAN_7        53
429
# define OMAP_DMA_MMC2_TX                54
430
# define OMAP_DMA_MMC2_RX                55
431
# define OMAP_DMA_CRYPTO_DES_OUT        56
432

    
433
struct omap_mpu_timer_s;
434
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
435
                qemu_irq irq, omap_clk clk);
436

    
437
struct omap_watchdog_timer_s;
438
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
439
                qemu_irq irq, omap_clk clk);
440

    
441
struct omap_32khz_timer_s;
442
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
443
                qemu_irq irq, omap_clk clk);
444

    
445
struct omap_tipb_bridge_s;
446
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
447
                qemu_irq abort_irq, omap_clk clk);
448

    
449
struct omap_uart_s;
450
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
451
                qemu_irq irq, omap_clk clk, CharDriverState *chr);
452

    
453
/* omap_lcdc.c */
454
struct omap_lcd_panel_s;
455
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
456
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
457
                struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
458
                ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
459

    
460
/* omap_mmc.c */
461
struct omap_mmc_s;
462
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
463
                qemu_irq irq, qemu_irq dma[], omap_clk clk);
464
void omap_mmc_reset(struct omap_mmc_s *s);
465

    
466
# define cpu_is_omap310(cpu)                (cpu->mpu_model == omap310)
467
# define cpu_is_omap1510(cpu)                (cpu->mpu_model == omap1510)
468
# define cpu_is_omap15xx(cpu)                \
469
        (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
470
# define cpu_class_omap1(cpu)                1
471

    
472
struct omap_mpu_state_s {
473
    enum omap1_mpu_model {
474
        omap310,
475
        omap1510,
476
    } mpu_model;
477

    
478
    CPUState *env;
479

    
480
    qemu_irq *irq[2];
481
    qemu_irq *drq;
482

    
483
    qemu_irq wakeup;
484

    
485
    struct omap_dma_port_if_s {
486
        uint32_t (*read[3])(struct omap_mpu_state_s *s, 
487
                        target_phys_addr_t offset);
488
        void (*write[3])(struct omap_mpu_state_s *s,
489
                        target_phys_addr_t offset, uint32_t value);
490
        int (*addr_valid)(struct omap_mpu_state_s *s,
491
                        target_phys_addr_t addr);
492
    } port[omap_dma_port_last];
493

    
494
    unsigned long sdram_size;
495
    unsigned long sram_size;
496

    
497
    /* MPUI-TIPB peripherals */
498
    struct omap_uart_s *uart3;
499

    
500
    /* MPU public TIPB peripherals */
501
    struct omap_32khz_timer_s *os_timer;
502

    
503
    struct omap_uart_s *uart1;
504
    struct omap_uart_s *uart2;
505

    
506
    struct omap_mmc_s *mmc;
507

    
508
    /* MPU private TIPB peripherals */
509
    struct omap_intr_handler_s *ih[2];
510

    
511
    struct omap_dma_s *dma;
512

    
513
    struct omap_mpu_timer_s *timer[3];
514
    struct omap_watchdog_timer_s *wdt;
515

    
516
    struct omap_lcd_panel_s *lcd;
517

    
518
    target_phys_addr_t ulpd_pm_base;
519
    uint32_t ulpd_pm_regs[21];
520
    int64_t ulpd_gauge_start;
521

    
522
    target_phys_addr_t pin_cfg_base;
523
    uint32_t func_mux_ctrl[14];
524
    uint32_t comp_mode_ctrl[1];
525
    uint32_t pull_dwn_ctrl[4];
526
    uint32_t gate_inh_ctrl[1];
527
    uint32_t voltage_ctrl[1];
528
    uint32_t test_dbg_ctrl[1];
529
    uint32_t mod_conf_ctrl[1];
530
    int compat1509;
531

    
532
    uint32_t mpui_ctrl;
533
    target_phys_addr_t mpui_base;
534

    
535
    struct omap_tipb_bridge_s *private_tipb;
536
    struct omap_tipb_bridge_s *public_tipb;
537

    
538
    target_phys_addr_t tcmi_base;
539
    uint32_t tcmi_regs[17];
540

    
541
    struct dpll_ctl_s {
542
        target_phys_addr_t base;
543
        uint16_t mode;
544
        omap_clk dpll;
545
    } dpll[3];
546

    
547
    omap_clk clks;
548
    struct {
549
        target_phys_addr_t mpu_base;
550
        target_phys_addr_t dsp_base;
551

    
552
        int cold_start;
553
        int clocking_scheme;
554
        uint16_t arm_ckctl;
555
        uint16_t arm_idlect1;
556
        uint16_t arm_idlect2;
557
        uint16_t arm_ewupct;
558
        uint16_t arm_rstct1;
559
        uint16_t arm_rstct2;
560
        uint16_t arm_ckout1;
561
        int dpll1_mode;
562
        uint16_t dsp_idlect1;
563
        uint16_t dsp_idlect2;
564
        uint16_t dsp_rstct2;
565
    } clkm;
566
} *omap310_mpu_init(unsigned long sdram_size,
567
                DisplayState *ds, const char *core);
568

    
569
# if TARGET_PHYS_ADDR_BITS == 32
570
#  define OMAP_FMT_plx "%#08x"
571
# elif TARGET_PHYS_ADDR_BITS == 64
572
#  define OMAP_FMT_plx "%#08" PRIx64
573
# else
574
#  error TARGET_PHYS_ADDR_BITS undefined
575
# endif
576

    
577
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
578
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
579
                uint32_t value);
580
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
581
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
582
                uint32_t value);
583

    
584
# define OMAP_BAD_REG(paddr)                \
585
        printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)
586
# define OMAP_RO_REG(paddr)                \
587
        printf("%s: Read-only register " OMAP_FMT_plx "\n",        \
588
                        __FUNCTION__, paddr)
589
# define OMAP_16B_REG(paddr)                \
590
        printf("%s: 16-bit register " OMAP_FMT_plx "\n",        \
591
                        __FUNCTION__, paddr)
592
# define OMAP_32B_REG(paddr)                \
593
        printf("%s: 32-bit register " OMAP_FMT_plx "\n",        \
594
                        __FUNCTION__, paddr)
595

    
596
#endif /* hw_omap_h */