Revision b30d4608 hw/cirrus_vga.c
b/hw/cirrus_vga.c | ||
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456 | 456 |
ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), |
457 | 457 |
}; |
458 | 458 |
|
459 |
static const cirrus_bitblt_rop_t cirrus_colorexpand_transp_inv[16][4] = { |
|
460 |
ROP2(cirrus_colorexpand_transp_inv_0), |
|
461 |
ROP2(cirrus_colorexpand_transp_inv_src_and_dst), |
|
462 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
|
463 |
ROP2(cirrus_colorexpand_transp_inv_src_and_notdst), |
|
464 |
ROP2(cirrus_colorexpand_transp_inv_notdst), |
|
465 |
ROP2(cirrus_colorexpand_transp_inv_src), |
|
466 |
ROP2(cirrus_colorexpand_transp_inv_1), |
|
467 |
ROP2(cirrus_colorexpand_transp_inv_notsrc_and_dst), |
|
468 |
ROP2(cirrus_colorexpand_transp_inv_src_xor_dst), |
|
469 |
ROP2(cirrus_colorexpand_transp_inv_src_or_dst), |
|
470 |
ROP2(cirrus_colorexpand_transp_inv_notsrc_or_notdst), |
|
471 |
ROP2(cirrus_colorexpand_transp_inv_src_notxor_dst), |
|
472 |
ROP2(cirrus_colorexpand_transp_inv_src_or_notdst), |
|
473 |
ROP2(cirrus_colorexpand_transp_inv_notsrc), |
|
474 |
ROP2(cirrus_colorexpand_transp_inv_notsrc_or_dst), |
|
475 |
ROP2(cirrus_colorexpand_transp_inv_notsrc_and_notdst), |
|
476 |
}; |
|
477 |
|
|
478 | 459 |
static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { |
479 | 460 |
ROP2(cirrus_colorexpand_0), |
480 | 461 |
ROP2(cirrus_colorexpand_src_and_dst), |
... | ... | |
494 | 475 |
ROP2(cirrus_colorexpand_notsrc_and_notdst), |
495 | 476 |
}; |
496 | 477 |
|
478 |
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { |
|
479 |
ROP2(cirrus_colorexpand_pattern_transp_0), |
|
480 |
ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), |
|
481 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
|
482 |
ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), |
|
483 |
ROP2(cirrus_colorexpand_pattern_transp_notdst), |
|
484 |
ROP2(cirrus_colorexpand_pattern_transp_src), |
|
485 |
ROP2(cirrus_colorexpand_pattern_transp_1), |
|
486 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), |
|
487 |
ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), |
|
488 |
ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), |
|
489 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), |
|
490 |
ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), |
|
491 |
ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), |
|
492 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc), |
|
493 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), |
|
494 |
ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), |
|
495 |
}; |
|
496 |
|
|
497 |
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { |
|
498 |
ROP2(cirrus_colorexpand_pattern_0), |
|
499 |
ROP2(cirrus_colorexpand_pattern_src_and_dst), |
|
500 |
ROP_NOP2(cirrus_bitblt_rop_nop), |
|
501 |
ROP2(cirrus_colorexpand_pattern_src_and_notdst), |
|
502 |
ROP2(cirrus_colorexpand_pattern_notdst), |
|
503 |
ROP2(cirrus_colorexpand_pattern_src), |
|
504 |
ROP2(cirrus_colorexpand_pattern_1), |
|
505 |
ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), |
|
506 |
ROP2(cirrus_colorexpand_pattern_src_xor_dst), |
|
507 |
ROP2(cirrus_colorexpand_pattern_src_or_dst), |
|
508 |
ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), |
|
509 |
ROP2(cirrus_colorexpand_pattern_src_notxor_dst), |
|
510 |
ROP2(cirrus_colorexpand_pattern_src_or_notdst), |
|
511 |
ROP2(cirrus_colorexpand_pattern_notsrc), |
|
512 |
ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), |
|
513 |
ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), |
|
514 |
}; |
|
515 |
|
|
497 | 516 |
static const cirrus_fill_t cirrus_fill[16][4] = { |
498 | 517 |
ROP2(cirrus_fill_0), |
499 | 518 |
ROP2(cirrus_fill_src_and_dst), |
... | ... | |
584 | 603 |
static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
585 | 604 |
const uint8_t * src) |
586 | 605 |
{ |
587 |
uint8_t work_colorexp[256]; |
|
588 | 606 |
uint8_t *dst; |
589 |
int patternbytes = s->cirrus_blt_pixelwidth * 8; |
|
590 | 607 |
|
591 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { |
|
592 |
cirrus_bitblt_rop_t rop_func; |
|
593 |
cirrus_bitblt_fgcol(s); |
|
594 |
cirrus_bitblt_bgcol(s); |
|
595 |
rop_func = cirrus_colorexpand[CIRRUS_ROP_SRC_INDEX][s->cirrus_blt_pixelwidth - 1]; |
|
596 |
rop_func(s, work_colorexp, src, patternbytes, 1, patternbytes, 8); |
|
597 |
src = work_colorexp; |
|
598 |
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_COLOREXPAND; |
|
599 |
} |
|
600 |
if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_PATTERNCOPY) { |
|
601 |
#ifdef DEBUG_BITBLT |
|
602 |
printf("cirrus: blt mode %02x (pattercopy) - unimplemented\n", |
|
603 |
s->cirrus_blt_mode); |
|
604 |
#endif |
|
605 |
return 0; |
|
606 |
} |
|
607 |
|
|
608 | 608 |
dst = s->vram_ptr + s->cirrus_blt_dstaddr; |
609 | 609 |
(*s->cirrus_rop) (s, dst, src, |
610 | 610 |
s->cirrus_blt_dstpitch, 0, |
... | ... | |
728 | 728 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { |
729 | 729 |
s->cirrus_blt_srcpitch = 8; |
730 | 730 |
} else { |
731 |
/* XXX: check for 24 bpp */ |
|
731 | 732 |
s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; |
732 | 733 |
} |
733 | 734 |
s->cirrus_srccounter = s->cirrus_blt_srcpitch; |
... | ... | |
848 | 849 |
CIRRUS_BLTMODE_COLOREXPAND) { |
849 | 850 |
|
850 | 851 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { |
851 |
if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
|
|
852 |
if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) |
|
852 | 853 |
cirrus_bitblt_bgcol(s); |
853 |
s->cirrus_rop = cirrus_colorexpand_transp_inv[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
|
854 |
} else { |
|
854 |
else |
|
855 | 855 |
cirrus_bitblt_fgcol(s); |
856 |
s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
|
857 |
} |
|
856 |
s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
|
858 | 857 |
} else { |
859 | 858 |
cirrus_bitblt_fgcol(s); |
860 | 859 |
cirrus_bitblt_bgcol(s); |
861 | 860 |
s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
862 | 861 |
} |
863 | 862 |
} else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
864 |
s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
|
863 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) { |
|
864 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) { |
|
865 |
if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) |
|
866 |
cirrus_bitblt_bgcol(s); |
|
867 |
else |
|
868 |
cirrus_bitblt_fgcol(s); |
|
869 |
s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
|
870 |
} else { |
|
871 |
cirrus_bitblt_fgcol(s); |
|
872 |
cirrus_bitblt_bgcol(s); |
|
873 |
s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
|
874 |
} |
|
875 |
} else { |
|
876 |
s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1]; |
|
877 |
} |
|
865 | 878 |
} else { |
866 | 879 |
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) { |
867 | 880 |
s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
... | ... | |
2793 | 2806 |
vga_io_memory); |
2794 | 2807 |
|
2795 | 2808 |
s->sr[0x06] = 0x0f; |
2796 |
s->sr[0x1F] = 0x22; // MemClock |
|
2797 | 2809 |
if (device_id == CIRRUS_ID_CLGD5446) { |
2798 | 2810 |
/* 4MB 64 bit memory config, always PCI */ |
2811 |
s->sr[0x1F] = 0x2d; // MemClock |
|
2812 |
s->gr[0x18] = 0x0f; // fastest memory configuration |
|
2799 | 2813 |
#if 1 |
2800 | 2814 |
s->sr[0x0f] = 0x98; |
2801 | 2815 |
s->sr[0x17] = 0x20; |
... | ... | |
2808 | 2822 |
s->real_vram_size = 2048 * 1024; |
2809 | 2823 |
#endif |
2810 | 2824 |
} else { |
2825 |
s->sr[0x1F] = 0x22; // MemClock |
|
2811 | 2826 |
s->sr[0x0F] = CIRRUS_MEMSIZE_2M; |
2812 | 2827 |
if (is_pci) |
2813 | 2828 |
s->sr[0x17] = CIRRUS_BUSTYPE_PCI; |
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