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root / target-alpha @ b3249f63

Name Size
STATUS 1.6 kB
cpu.h 9.8 kB
exec.h 2.3 kB
helper.c 11.6 kB
helper.h 1.2 kB
op.c 10 kB
op_helper.c 21.6 kB
op_helper.h 3.6 kB
op_helper_mem.h 1.2 kB
op_mem.h 4.3 kB
op_template.h 1.8 kB
translate.c 77.5 kB

Latest revisions

# Date Author Comment
b3249f63 09/18/2008 01:04 am aurel32

target-alpha: convert byte manipulation instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
9c29504e 09/18/2008 01:04 am aurel32

alpha: convert cmov and bcond to TCG

Patch mostly by Tristan Gingold

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5245 c046a42c-6fe2-441c-8c8c-71466251a162
1ef4ef4e 09/17/2008 01:44 am aurel32

target-alpha: small optimizations

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5238 c046a42c-6fe2-441c-8c8c-71466251a162
6ba8dcd7 09/17/2008 01:44 am aurel32

target-alpha: fix TCG register names

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5237 c046a42c-6fe2-441c-8c8c-71466251a162
30c7183b 09/17/2008 01:44 am aurel32

target-alpha: convert some arith3 instructions to TCG

Replace gen_arith3 generic macro and dyngen ops by instruction specific
optimized TCG code.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5236 c046a42c-6fe2-441c-8c8c-71466251a162
ae8ecd42 09/17/2008 01:44 am aurel32

target-alpha: convert arith2 instructions to TCG

Replace gen_arith2 generic macro and dyngon ops by instruction specific
optimized TCG code.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
fdbbb5d9 09/14/2008 07:09 pm aurel32

alpha: fix helper.h

the content of target-alpha/helper.h is duplicated twice

(Tristan Gingold)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5212 c046a42c-6fe2-441c-8c8c-71466251a162
9e85e9bd 09/14/2008 07:09 pm aurel32

alpha: fix lit sign

according to the alpha arch reference, the literal field of an operate
instruction is unsigned:

If bit <12> of the instruction is 1, an 8-bit zero-extended literal
constant is formed by bits
<20:13> of the instruction. The l teral is interpreted as a positive...
7ccfb2eb 09/14/2008 09:45 am blueswir1

Fix warnings that would be caused by gcc flag -Wwrite-strings

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5206 c046a42c-6fe2-441c-8c8c-71466251a162
29d26d20 09/05/2008 10:07 pm aurel32

fix alpha cmovxx instruction

The CMOV instruction is defined by the alpha manual as:

CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format

Operation:
IF TEST THEN
Rc ← Rbv

The current qemu behavior inverses Ra and Rb. This is fixed by this...

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