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/*
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* vm86 linux syscall support
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <errno.h> |
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#include <unistd.h> |
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|
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#include "qemu.h" |
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|
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//#define DEBUG_VM86
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#define set_flags(X,new,mask) \
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((X) = ((X) & ~(mask)) | ((new) & (mask))) |
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|
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#define SAFE_MASK (0xDD5) |
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#define RETURN_MASK (0xDFF) |
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|
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static inline int is_revectored(int nr, struct target_revectored_struct *bitmap) |
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{
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return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1; |
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} |
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|
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static inline void vm_putw(uint8_t *segptr, unsigned int reg16, unsigned int val) |
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{
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*(uint16_t *)(segptr + (reg16 & 0xffff)) = tswap16(val);
|
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} |
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|
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static inline void vm_putl(uint8_t *segptr, unsigned int reg16, unsigned int val) |
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{
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*(uint32_t *)(segptr + (reg16 & 0xffff)) = tswap32(val);
|
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} |
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|
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static inline unsigned int vm_getw(uint8_t *segptr, unsigned int reg16) |
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{
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return tswap16(*(uint16_t *)(segptr + (reg16 & 0xffff))); |
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} |
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|
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static inline unsigned int vm_getl(uint8_t *segptr, unsigned int reg16) |
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{
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return tswap32(*(uint16_t *)(segptr + (reg16 & 0xffff))); |
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} |
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|
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void save_v86_state(CPUX86State *env)
|
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{
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TaskState *ts = env->opaque; |
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|
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/* put the VM86 registers in the userspace register structure */
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ts->target_v86->regs.eax = tswap32(env->regs[R_EAX]); |
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ts->target_v86->regs.ebx = tswap32(env->regs[R_EBX]); |
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ts->target_v86->regs.ecx = tswap32(env->regs[R_ECX]); |
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ts->target_v86->regs.edx = tswap32(env->regs[R_EDX]); |
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ts->target_v86->regs.esi = tswap32(env->regs[R_ESI]); |
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ts->target_v86->regs.edi = tswap32(env->regs[R_EDI]); |
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ts->target_v86->regs.ebp = tswap32(env->regs[R_EBP]); |
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ts->target_v86->regs.esp = tswap32(env->regs[R_ESP]); |
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ts->target_v86->regs.eip = tswap32(env->eip); |
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ts->target_v86->regs.cs = tswap16(env->segs[R_CS]); |
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ts->target_v86->regs.ss = tswap16(env->segs[R_SS]); |
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ts->target_v86->regs.ds = tswap16(env->segs[R_DS]); |
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ts->target_v86->regs.es = tswap16(env->segs[R_ES]); |
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ts->target_v86->regs.fs = tswap16(env->segs[R_FS]); |
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ts->target_v86->regs.gs = tswap16(env->segs[R_GS]); |
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set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask); |
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ts->target_v86->regs.eflags = tswap32(env->eflags); |
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#ifdef DEBUG_VM86
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fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
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env->eflags, env->segs[R_CS], env->eip); |
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#endif
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|
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/* restore 32 bit registers */
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env->regs[R_EAX] = ts->vm86_saved_regs.eax; |
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env->regs[R_EBX] = ts->vm86_saved_regs.ebx; |
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env->regs[R_ECX] = ts->vm86_saved_regs.ecx; |
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env->regs[R_EDX] = ts->vm86_saved_regs.edx; |
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env->regs[R_ESI] = ts->vm86_saved_regs.esi; |
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env->regs[R_EDI] = ts->vm86_saved_regs.edi; |
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env->regs[R_EBP] = ts->vm86_saved_regs.ebp; |
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env->regs[R_ESP] = ts->vm86_saved_regs.esp; |
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env->eflags = ts->vm86_saved_regs.eflags; |
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env->eip = ts->vm86_saved_regs.eip; |
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|
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cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs); |
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cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss); |
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cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds); |
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cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es); |
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cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs); |
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cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs); |
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} |
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|
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/* return from vm86 mode to 32 bit. The vm86() syscall will return
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'retval' */
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static inline void return_to_32bit(CPUX86State *env, int retval) |
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{
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#ifdef DEBUG_VM86
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fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval);
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#endif
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save_v86_state(env); |
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env->regs[R_EAX] = retval; |
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} |
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|
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static inline int set_IF(CPUX86State *env) |
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{
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TaskState *ts = env->opaque; |
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ts->v86flags |= VIF_MASK; |
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if (ts->v86flags & VIP_MASK) {
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return_to_32bit(env, TARGET_VM86_STI); |
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return 1; |
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} |
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return 0; |
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} |
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|
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static inline void clear_IF(CPUX86State *env) |
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{
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TaskState *ts = env->opaque; |
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ts->v86flags &= ~VIF_MASK; |
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} |
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|
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static inline void clear_TF(CPUX86State *env) |
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{
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env->eflags &= ~TF_MASK; |
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} |
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|
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static inline void clear_AC(CPUX86State *env) |
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{
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env->eflags &= ~AC_MASK; |
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} |
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|
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static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) |
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{
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TaskState *ts = env->opaque; |
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set_flags(ts->v86flags, eflags, ts->v86mask); |
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set_flags(env->eflags, eflags, SAFE_MASK); |
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if (eflags & IF_MASK)
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return set_IF(env);
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else
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clear_IF(env); |
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return 0; |
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} |
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|
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static inline int set_vflags_short(unsigned short flags, CPUX86State *env) |
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{
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TaskState *ts = env->opaque; |
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set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
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set_flags(env->eflags, flags, SAFE_MASK); |
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if (flags & IF_MASK)
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return set_IF(env);
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else
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clear_IF(env); |
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return 0; |
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} |
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static inline unsigned int get_vflags(CPUX86State *env) |
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{
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TaskState *ts = env->opaque; |
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unsigned int flags; |
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flags = env->eflags & RETURN_MASK; |
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if (ts->v86flags & VIF_MASK)
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flags |= IF_MASK; |
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return flags | (ts->v86flags & ts->v86mask);
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} |
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|
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#define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff) |
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|
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/* handle VM86 interrupt (NOTE: the CPU core currently does not
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support TSS interrupt revectoring, so this code is always executed) */
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static void do_int(CPUX86State *env, int intno) |
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{
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TaskState *ts = env->opaque; |
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uint32_t *int_ptr, segoffs; |
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uint8_t *ssp; |
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unsigned int sp; |
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if (env->segs[R_CS] == TARGET_BIOSSEG)
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goto cannot_handle;
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if (is_revectored(intno, &ts->vm86plus.int_revectored))
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goto cannot_handle;
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if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff, |
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&ts->vm86plus.int21_revectored)) |
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goto cannot_handle;
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int_ptr = (uint32_t *)(intno << 2);
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segoffs = tswap32(*int_ptr); |
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if ((segoffs >> 16) == TARGET_BIOSSEG) |
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goto cannot_handle;
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#if defined(DEBUG_VM86)
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fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
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intno, segoffs >> 16, segoffs & 0xffff); |
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#endif
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/* save old state */
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ssp = (uint8_t *)(env->segs[R_SS] << 4);
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sp = env->regs[R_ESP] & 0xffff;
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vm_putw(ssp, sp - 2, get_vflags(env));
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vm_putw(ssp, sp - 4, env->segs[R_CS]);
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vm_putw(ssp, sp - 6, env->eip);
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ADD16(env->regs[R_ESP], -6);
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/* goto interrupt handler */
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env->eip = segoffs & 0xffff;
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cpu_x86_load_seg(env, R_CS, segoffs >> 16);
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clear_TF(env); |
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clear_IF(env); |
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clear_AC(env); |
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return;
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cannot_handle:
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#if defined(DEBUG_VM86)
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fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno);
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#endif
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return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
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} |
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|
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void handle_vm86_trap(CPUX86State *env, int trapno) |
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{
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if (trapno == 1 || trapno == 3) { |
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return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
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} else {
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do_int(env, trapno); |
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} |
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} |
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|
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#define CHECK_IF_IN_TRAP() \
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if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
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(ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \ |
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newflags |= TF_MASK |
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|
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#define VM86_FAULT_RETURN \
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if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
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(ts->v86flags & (IF_MASK | VIF_MASK))) \ |
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return_to_32bit(env, TARGET_VM86_PICRETURN); \ |
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return
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|
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void handle_vm86_fault(CPUX86State *env)
|
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{
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TaskState *ts = env->opaque; |
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uint8_t *csp, *pc, *ssp; |
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unsigned int ip, sp, newflags, newip, newcs, opcode, intno; |
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int data32, pref_done;
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csp = (uint8_t *)(env->segs[R_CS] << 4);
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ip = env->eip & 0xffff;
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pc = csp + ip; |
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ssp = (uint8_t *)(env->segs[R_SS] << 4);
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sp = env->regs[R_ESP] & 0xffff;
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#if defined(DEBUG_VM86)
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fprintf(logfile, "VM86 exception %04x:%08x %02x %02x\n",
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env->segs[R_CS], env->eip, pc[0], pc[1]); |
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#endif
|
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|
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data32 = 0;
|
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pref_done = 0;
|
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do {
|
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opcode = csp[ip]; |
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ADD16(ip, 1);
|
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switch (opcode) {
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case 0x66: /* 32-bit data */ data32=1; break; |
| 279 |
case 0x67: /* 32-bit address */ break; |
| 280 |
case 0x2e: /* CS */ break; |
| 281 |
case 0x3e: /* DS */ break; |
| 282 |
case 0x26: /* ES */ break; |
| 283 |
case 0x36: /* SS */ break; |
| 284 |
case 0x65: /* GS */ break; |
| 285 |
case 0x64: /* FS */ break; |
| 286 |
case 0xf2: /* repnz */ break; |
| 287 |
case 0xf3: /* rep */ break; |
| 288 |
default: pref_done = 1; |
| 289 |
} |
| 290 |
} while (!pref_done);
|
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|
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/* VM86 mode */
|
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switch(opcode) {
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case 0x9c: /* pushf */ |
| 295 |
ADD16(env->eip, 2);
|
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if (data32) {
|
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vm_putl(ssp, sp - 4, get_vflags(env));
|
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ADD16(env->regs[R_ESP], -4);
|
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} else {
|
| 300 |
vm_putw(ssp, sp - 2, get_vflags(env));
|
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ADD16(env->regs[R_ESP], -2);
|
| 302 |
} |
| 303 |
env->eip = ip; |
| 304 |
VM86_FAULT_RETURN; |
| 305 |
|
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case 0x9d: /* popf */ |
| 307 |
if (data32) {
|
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newflags = vm_getl(ssp, sp); |
| 309 |
ADD16(env->regs[R_ESP], 4);
|
| 310 |
} else {
|
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newflags = vm_getw(ssp, sp); |
| 312 |
ADD16(env->regs[R_ESP], 2);
|
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} |
| 314 |
env->eip = ip; |
| 315 |
CHECK_IF_IN_TRAP(); |
| 316 |
if (data32) {
|
| 317 |
if (set_vflags_long(newflags, env))
|
| 318 |
return;
|
| 319 |
} else {
|
| 320 |
if (set_vflags_short(newflags, env))
|
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return;
|
| 322 |
} |
| 323 |
VM86_FAULT_RETURN; |
| 324 |
|
| 325 |
case 0xcd: /* int */ |
| 326 |
intno = csp[ip]; |
| 327 |
ADD16(ip, 1);
|
| 328 |
env->eip = ip; |
| 329 |
if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
|
| 330 |
if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >> |
| 331 |
(intno &7)) & 1) { |
| 332 |
return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
|
| 333 |
return;
|
| 334 |
} |
| 335 |
} |
| 336 |
do_int(env, intno); |
| 337 |
break;
|
| 338 |
|
| 339 |
case 0xcf: /* iret */ |
| 340 |
if (data32) {
|
| 341 |
newip = vm_getl(ssp, sp) & 0xffff;
|
| 342 |
newcs = vm_getl(ssp, sp + 4) & 0xffff; |
| 343 |
newflags = vm_getl(ssp, sp + 8);
|
| 344 |
ADD16(env->regs[R_ESP], 12);
|
| 345 |
} else {
|
| 346 |
newip = vm_getw(ssp, sp); |
| 347 |
newcs = vm_getw(ssp, sp + 2);
|
| 348 |
newflags = vm_getw(ssp, sp + 4);
|
| 349 |
ADD16(env->regs[R_ESP], 6);
|
| 350 |
} |
| 351 |
env->eip = newip; |
| 352 |
cpu_x86_load_seg(env, R_CS, newcs); |
| 353 |
CHECK_IF_IN_TRAP(); |
| 354 |
if (data32) {
|
| 355 |
if (set_vflags_long(newflags, env))
|
| 356 |
return;
|
| 357 |
} else {
|
| 358 |
if (set_vflags_short(newflags, env))
|
| 359 |
return;
|
| 360 |
} |
| 361 |
VM86_FAULT_RETURN; |
| 362 |
|
| 363 |
case 0xfa: /* cli */ |
| 364 |
env->eip = ip; |
| 365 |
clear_IF(env); |
| 366 |
VM86_FAULT_RETURN; |
| 367 |
|
| 368 |
case 0xfb: /* sti */ |
| 369 |
env->eip = ip; |
| 370 |
if (set_IF(env))
|
| 371 |
return;
|
| 372 |
VM86_FAULT_RETURN; |
| 373 |
|
| 374 |
default:
|
| 375 |
/* real VM86 GPF exception */
|
| 376 |
return_to_32bit(env, TARGET_VM86_UNKNOWN); |
| 377 |
break;
|
| 378 |
} |
| 379 |
} |
| 380 |
|
| 381 |
int do_vm86(CPUX86State *env, long subfunction, |
| 382 |
struct target_vm86plus_struct * target_v86)
|
| 383 |
{
|
| 384 |
TaskState *ts = env->opaque; |
| 385 |
int ret;
|
| 386 |
|
| 387 |
switch (subfunction) {
|
| 388 |
case TARGET_VM86_REQUEST_IRQ:
|
| 389 |
case TARGET_VM86_FREE_IRQ:
|
| 390 |
case TARGET_VM86_GET_IRQ_BITS:
|
| 391 |
case TARGET_VM86_GET_AND_RESET_IRQ:
|
| 392 |
gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
|
| 393 |
ret = -EINVAL; |
| 394 |
goto out;
|
| 395 |
case TARGET_VM86_PLUS_INSTALL_CHECK:
|
| 396 |
/* NOTE: on old vm86 stuff this will return the error
|
| 397 |
from verify_area(), because the subfunction is
|
| 398 |
interpreted as (invalid) address to vm86_struct.
|
| 399 |
So the installation check works.
|
| 400 |
*/
|
| 401 |
ret = 0;
|
| 402 |
goto out;
|
| 403 |
} |
| 404 |
|
| 405 |
ts->target_v86 = target_v86; |
| 406 |
/* save current CPU regs */
|
| 407 |
ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */ |
| 408 |
ts->vm86_saved_regs.ebx = env->regs[R_EBX]; |
| 409 |
ts->vm86_saved_regs.ecx = env->regs[R_ECX]; |
| 410 |
ts->vm86_saved_regs.edx = env->regs[R_EDX]; |
| 411 |
ts->vm86_saved_regs.esi = env->regs[R_ESI]; |
| 412 |
ts->vm86_saved_regs.edi = env->regs[R_EDI]; |
| 413 |
ts->vm86_saved_regs.ebp = env->regs[R_EBP]; |
| 414 |
ts->vm86_saved_regs.esp = env->regs[R_ESP]; |
| 415 |
ts->vm86_saved_regs.eflags = env->eflags; |
| 416 |
ts->vm86_saved_regs.eip = env->eip; |
| 417 |
ts->vm86_saved_regs.cs = env->segs[R_CS]; |
| 418 |
ts->vm86_saved_regs.ss = env->segs[R_SS]; |
| 419 |
ts->vm86_saved_regs.ds = env->segs[R_DS]; |
| 420 |
ts->vm86_saved_regs.es = env->segs[R_ES]; |
| 421 |
ts->vm86_saved_regs.fs = env->segs[R_FS]; |
| 422 |
ts->vm86_saved_regs.gs = env->segs[R_GS]; |
| 423 |
|
| 424 |
/* build vm86 CPU state */
|
| 425 |
ts->v86flags = tswap32(target_v86->regs.eflags); |
| 426 |
env->eflags = (env->eflags & ~SAFE_MASK) | |
| 427 |
(tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK; |
| 428 |
|
| 429 |
ts->vm86plus.cpu_type = tswapl(target_v86->cpu_type); |
| 430 |
switch (ts->vm86plus.cpu_type) {
|
| 431 |
case TARGET_CPU_286:
|
| 432 |
ts->v86mask = 0;
|
| 433 |
break;
|
| 434 |
case TARGET_CPU_386:
|
| 435 |
ts->v86mask = NT_MASK | IOPL_MASK; |
| 436 |
break;
|
| 437 |
case TARGET_CPU_486:
|
| 438 |
ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK; |
| 439 |
break;
|
| 440 |
default:
|
| 441 |
ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK; |
| 442 |
break;
|
| 443 |
} |
| 444 |
|
| 445 |
env->regs[R_EBX] = tswap32(target_v86->regs.ebx); |
| 446 |
env->regs[R_ECX] = tswap32(target_v86->regs.ecx); |
| 447 |
env->regs[R_EDX] = tswap32(target_v86->regs.edx); |
| 448 |
env->regs[R_ESI] = tswap32(target_v86->regs.esi); |
| 449 |
env->regs[R_EDI] = tswap32(target_v86->regs.edi); |
| 450 |
env->regs[R_EBP] = tswap32(target_v86->regs.ebp); |
| 451 |
env->regs[R_ESP] = tswap32(target_v86->regs.esp); |
| 452 |
env->eip = tswap32(target_v86->regs.eip); |
| 453 |
cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs)); |
| 454 |
cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss)); |
| 455 |
cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds)); |
| 456 |
cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es)); |
| 457 |
cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs)); |
| 458 |
cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs)); |
| 459 |
ret = tswap32(target_v86->regs.eax); /* eax will be restored at
|
| 460 |
the end of the syscall */
|
| 461 |
memcpy(&ts->vm86plus.int_revectored, |
| 462 |
&target_v86->int_revectored, 32);
|
| 463 |
memcpy(&ts->vm86plus.int21_revectored, |
| 464 |
&target_v86->int21_revectored, 32);
|
| 465 |
ts->vm86plus.vm86plus.flags = tswapl(target_v86->vm86plus.flags); |
| 466 |
memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab, |
| 467 |
target_v86->vm86plus.vm86dbg_intxxtab, 32);
|
| 468 |
|
| 469 |
#ifdef DEBUG_VM86
|
| 470 |
fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n", env->segs[R_CS], env->eip);
|
| 471 |
#endif
|
| 472 |
/* now the virtual CPU is ready for vm86 execution ! */
|
| 473 |
out:
|
| 474 |
return ret;
|
| 475 |
} |
| 476 |
|