root / target-ppc / cpu.h @ b33c17e1
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation cpu definitions for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__CPU_PPC_H__)
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21 | 79aceca5 | bellard | #define __CPU_PPC_H__
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22 | 79aceca5 | bellard | |
23 | 3fc6c082 | bellard | #include "config.h" |
24 | de270b3c | j_mayer | #include <inttypes.h> |
25 | 3fc6c082 | bellard | |
26 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
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27 | 76a66253 | j_mayer | typedef uint64_t ppc_gpr_t;
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28 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 64 |
29 | d9d7210c | j_mayer | #define TARGET_LONG_BITS 64 |
30 | 76a66253 | j_mayer | #define REGX "%016" PRIx64 |
31 | 35cdaad6 | j_mayer | #define TARGET_PAGE_BITS 12 |
32 | 35cdaad6 | j_mayer | #elif defined(TARGET_PPCEMB)
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33 | 8b67546f | j_mayer | /* BookE have 36 bits physical address space */
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34 | e96efcfc | j_mayer | #define TARGET_PHYS_ADDR_BITS 64 |
35 | 76a66253 | j_mayer | /* GPR are 64 bits: used by vector extension */
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36 | 76a66253 | j_mayer | typedef uint64_t ppc_gpr_t;
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37 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 64 |
38 | d9d7210c | j_mayer | #define TARGET_LONG_BITS 32 |
39 | 1b9eb036 | j_mayer | #define REGX "%016" PRIx64 |
40 | d9d7210c | j_mayer | #if defined(CONFIG_USER_ONLY)
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41 | d9d7210c | j_mayer | /* It looks like a lot of Linux programs assume page size
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42 | d9d7210c | j_mayer | * is 4kB long. This is evil, but we have to deal with it...
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43 | d9d7210c | j_mayer | */
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44 | d9d7210c | j_mayer | #define TARGET_PAGE_BITS 12 |
45 | d9d7210c | j_mayer | #else
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46 | 35cdaad6 | j_mayer | /* Pages can be 1 kB small */
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47 | 35cdaad6 | j_mayer | #define TARGET_PAGE_BITS 10 |
48 | d9d7210c | j_mayer | #endif
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49 | d9d7210c | j_mayer | #else
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50 | d9d7210c | j_mayer | #if (HOST_LONG_BITS >= 64) |
51 | d9d7210c | j_mayer | /* When using 64 bits temporary registers,
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52 | d9d7210c | j_mayer | * we can use 64 bits GPR with no extra cost
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53 | d9d7210c | j_mayer | * It's even an optimization as it will prevent
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54 | d9d7210c | j_mayer | * the compiler to do unuseful masking in the micro-ops.
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55 | d9d7210c | j_mayer | */
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56 | d9d7210c | j_mayer | typedef uint64_t ppc_gpr_t;
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57 | d9d7210c | j_mayer | #define TARGET_GPR_BITS 64 |
58 | 71c8b8fd | j_mayer | #define REGX "%08" PRIx64 |
59 | 76a66253 | j_mayer | #else
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60 | 76a66253 | j_mayer | typedef uint32_t ppc_gpr_t;
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61 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 32 |
62 | 71c8b8fd | j_mayer | #define REGX "%08" PRIx32 |
63 | d9d7210c | j_mayer | #endif
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64 | d9d7210c | j_mayer | #define TARGET_LONG_BITS 32 |
65 | 35cdaad6 | j_mayer | #define TARGET_PAGE_BITS 12 |
66 | 76a66253 | j_mayer | #endif
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67 | 3cf1e035 | bellard | |
68 | 79aceca5 | bellard | #include "cpu-defs.h" |
69 | 79aceca5 | bellard | |
70 | e96efcfc | j_mayer | #define ADDRX TARGET_FMT_lx
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71 | e96efcfc | j_mayer | #define PADDRX TARGET_FMT_plx
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72 | e96efcfc | j_mayer | |
73 | 79aceca5 | bellard | #include <setjmp.h> |
74 | 79aceca5 | bellard | |
75 | 4ecc3190 | bellard | #include "softfloat.h" |
76 | 4ecc3190 | bellard | |
77 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
78 | 1fddef4b | bellard | |
79 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
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80 | 76a66253 | j_mayer | #define ELF_MACHINE EM_PPC64
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81 | 76a66253 | j_mayer | #else
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82 | 76a66253 | j_mayer | #define ELF_MACHINE EM_PPC
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83 | 76a66253 | j_mayer | #endif
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84 | 9042c0e2 | ths | |
85 | 3fc6c082 | bellard | /*****************************************************************************/
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86 | a750fc0b | j_mayer | /* MMU model */
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87 | 3fc6c082 | bellard | enum {
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88 | a750fc0b | j_mayer | POWERPC_MMU_UNKNOWN = 0,
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89 | a750fc0b | j_mayer | /* Standard 32 bits PowerPC MMU */
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90 | a750fc0b | j_mayer | POWERPC_MMU_32B, |
91 | a750fc0b | j_mayer | /* PowerPC 601 MMU */
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92 | a750fc0b | j_mayer | POWERPC_MMU_601, |
93 | a750fc0b | j_mayer | /* PowerPC 6xx MMU with software TLB */
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94 | a750fc0b | j_mayer | POWERPC_MMU_SOFT_6xx, |
95 | a750fc0b | j_mayer | /* PowerPC 74xx MMU with software TLB */
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96 | a750fc0b | j_mayer | POWERPC_MMU_SOFT_74xx, |
97 | a750fc0b | j_mayer | /* PowerPC 4xx MMU with software TLB */
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98 | a750fc0b | j_mayer | POWERPC_MMU_SOFT_4xx, |
99 | a750fc0b | j_mayer | /* PowerPC 4xx MMU with software TLB and zones protections */
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100 | a750fc0b | j_mayer | POWERPC_MMU_SOFT_4xx_Z, |
101 | a750fc0b | j_mayer | /* PowerPC 4xx MMU in real mode only */
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102 | a750fc0b | j_mayer | POWERPC_MMU_REAL_4xx, |
103 | a750fc0b | j_mayer | /* BookE MMU model */
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104 | a750fc0b | j_mayer | POWERPC_MMU_BOOKE, |
105 | a750fc0b | j_mayer | /* BookE FSL MMU model */
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106 | a750fc0b | j_mayer | POWERPC_MMU_BOOKE_FSL, |
107 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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108 | 12de9a39 | j_mayer | /* 64 bits PowerPC MMU */
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109 | 00af685f | j_mayer | POWERPC_MMU_64B, |
110 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
111 | 3fc6c082 | bellard | }; |
112 | 3fc6c082 | bellard | |
113 | 3fc6c082 | bellard | /*****************************************************************************/
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114 | a750fc0b | j_mayer | /* Exception model */
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115 | 3fc6c082 | bellard | enum {
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116 | a750fc0b | j_mayer | POWERPC_EXCP_UNKNOWN = 0,
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117 | 3fc6c082 | bellard | /* Standard PowerPC exception model */
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118 | a750fc0b | j_mayer | POWERPC_EXCP_STD, |
119 | 2662a059 | j_mayer | /* PowerPC 40x exception model */
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120 | a750fc0b | j_mayer | POWERPC_EXCP_40x, |
121 | 2662a059 | j_mayer | /* PowerPC 601 exception model */
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122 | a750fc0b | j_mayer | POWERPC_EXCP_601, |
123 | 2662a059 | j_mayer | /* PowerPC 602 exception model */
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124 | a750fc0b | j_mayer | POWERPC_EXCP_602, |
125 | 2662a059 | j_mayer | /* PowerPC 603 exception model */
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126 | a750fc0b | j_mayer | POWERPC_EXCP_603, |
127 | a750fc0b | j_mayer | /* PowerPC 603e exception model */
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128 | a750fc0b | j_mayer | POWERPC_EXCP_603E, |
129 | a750fc0b | j_mayer | /* PowerPC G2 exception model */
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130 | a750fc0b | j_mayer | POWERPC_EXCP_G2, |
131 | 2662a059 | j_mayer | /* PowerPC 604 exception model */
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132 | a750fc0b | j_mayer | POWERPC_EXCP_604, |
133 | 2662a059 | j_mayer | /* PowerPC 7x0 exception model */
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134 | a750fc0b | j_mayer | POWERPC_EXCP_7x0, |
135 | 2662a059 | j_mayer | /* PowerPC 7x5 exception model */
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136 | a750fc0b | j_mayer | POWERPC_EXCP_7x5, |
137 | 2662a059 | j_mayer | /* PowerPC 74xx exception model */
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138 | a750fc0b | j_mayer | POWERPC_EXCP_74xx, |
139 | 2662a059 | j_mayer | /* BookE exception model */
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140 | a750fc0b | j_mayer | POWERPC_EXCP_BOOKE, |
141 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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142 | 00af685f | j_mayer | /* PowerPC 970 exception model */
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143 | 00af685f | j_mayer | POWERPC_EXCP_970, |
144 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
145 | a750fc0b | j_mayer | }; |
146 | a750fc0b | j_mayer | |
147 | a750fc0b | j_mayer | /*****************************************************************************/
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148 | e1833e1f | j_mayer | /* Exception vectors definitions */
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149 | e1833e1f | j_mayer | enum {
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150 | e1833e1f | j_mayer | POWERPC_EXCP_NONE = -1,
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151 | e1833e1f | j_mayer | /* The 64 first entries are used by the PowerPC embedded specification */
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152 | e1833e1f | j_mayer | POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
153 | e1833e1f | j_mayer | POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
154 | e1833e1f | j_mayer | POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
155 | e1833e1f | j_mayer | POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
156 | e1833e1f | j_mayer | POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
157 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
158 | e1833e1f | j_mayer | POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
159 | e1833e1f | j_mayer | POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
160 | e1833e1f | j_mayer | POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
161 | e1833e1f | j_mayer | POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
162 | e1833e1f | j_mayer | POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
163 | e1833e1f | j_mayer | POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
164 | e1833e1f | j_mayer | POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
165 | e1833e1f | j_mayer | POWERPC_EXCP_DTLB = 13, /* Data TLB error */ |
166 | e1833e1f | j_mayer | POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */ |
167 | e1833e1f | j_mayer | POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
168 | e1833e1f | j_mayer | /* Vectors 16 to 31 are reserved */
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169 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
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170 | e1833e1f | j_mayer | POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
171 | e1833e1f | j_mayer | POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
172 | e1833e1f | j_mayer | POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
173 | e1833e1f | j_mayer | POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
174 | e1833e1f | j_mayer | POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
175 | e1833e1f | j_mayer | POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
176 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPCEMB) */ |
177 | e1833e1f | j_mayer | /* Vectors 38 to 63 are reserved */
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178 | e1833e1f | j_mayer | /* Exceptions defined in the PowerPC server specification */
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179 | e1833e1f | j_mayer | POWERPC_EXCP_RESET = 64, /* System reset exception */ |
180 | e1833e1f | j_mayer | #if defined(TARGET_PPC64) /* PowerPC 64 */ |
181 | e1833e1f | j_mayer | POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
182 | e1833e1f | j_mayer | POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
183 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
184 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ |
185 | e1833e1f | j_mayer | POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
186 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64H) */ |
187 | e1833e1f | j_mayer | POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
188 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ |
189 | e1833e1f | j_mayer | POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
190 | e1833e1f | j_mayer | POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
191 | e1833e1f | j_mayer | POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
192 | e1833e1f | j_mayer | POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
193 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64H) */ |
194 | e1833e1f | j_mayer | POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
195 | e1833e1f | j_mayer | /* 40x specific exceptions */
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196 | e1833e1f | j_mayer | POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
197 | e1833e1f | j_mayer | /* 601 specific exceptions */
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198 | e1833e1f | j_mayer | POWERPC_EXCP_IO = 75, /* IO error exception */ |
199 | e1833e1f | j_mayer | POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
200 | e1833e1f | j_mayer | /* 602 specific exceptions */
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201 | e1833e1f | j_mayer | POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
202 | e1833e1f | j_mayer | /* 602/603 specific exceptions */
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203 | e1833e1f | j_mayer | POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */ |
204 | e1833e1f | j_mayer | POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
205 | e1833e1f | j_mayer | POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
206 | e1833e1f | j_mayer | /* Exceptions available on most PowerPC */
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207 | e1833e1f | j_mayer | POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
208 | e1833e1f | j_mayer | POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */ |
209 | e1833e1f | j_mayer | POWERPC_EXCP_SMI = 83, /* System management interrupt */ |
210 | e1833e1f | j_mayer | POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */ |
211 | e1833e1f | j_mayer | /* 7xx/74xx specific exceptions */
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212 | e1833e1f | j_mayer | POWERPC_EXCP_THERM = 85, /* Thermal interrupt */ |
213 | e1833e1f | j_mayer | /* 74xx specific exceptions */
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214 | e1833e1f | j_mayer | POWERPC_EXCP_VPUA = 86, /* Vector assist exception */ |
215 | e1833e1f | j_mayer | /* 970FX specific exceptions */
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216 | e1833e1f | j_mayer | POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */ |
217 | e1833e1f | j_mayer | POWERPC_EXCP_MAINT = 88, /* Maintenance exception */ |
218 | e1833e1f | j_mayer | /* EOL */
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219 | e1833e1f | j_mayer | POWERPC_EXCP_NB = 96,
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220 | e1833e1f | j_mayer | /* Qemu exceptions: used internally during code translation */
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221 | e1833e1f | j_mayer | POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
222 | e1833e1f | j_mayer | POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
223 | e1833e1f | j_mayer | /* Qemu exceptions: special cases we want to stop translation */
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224 | e1833e1f | j_mayer | POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
225 | e1833e1f | j_mayer | POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
226 | e1833e1f | j_mayer | }; |
227 | e1833e1f | j_mayer | |
228 | e1833e1f | j_mayer | /* Exceptions error codes */
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229 | e1833e1f | j_mayer | enum {
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230 | e1833e1f | j_mayer | /* Exception subtypes for POWERPC_EXCP_ALIGN */
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231 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
232 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
233 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
234 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
235 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
236 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
237 | e1833e1f | j_mayer | /* Exception subtypes for POWERPC_EXCP_PROGRAM */
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238 | e1833e1f | j_mayer | /* FP exceptions */
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239 | e1833e1f | j_mayer | POWERPC_EXCP_FP = 0x10,
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240 | e1833e1f | j_mayer | POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
241 | e1833e1f | j_mayer | POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
242 | e1833e1f | j_mayer | POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
243 | e1833e1f | j_mayer | POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
244 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
245 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
246 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
247 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
248 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
249 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
250 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
251 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
252 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
253 | e1833e1f | j_mayer | /* Invalid instruction */
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254 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL = 0x20,
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255 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
256 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
257 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
258 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
259 | e1833e1f | j_mayer | /* Privileged instruction */
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260 | e1833e1f | j_mayer | POWERPC_EXCP_PRIV = 0x30,
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261 | e1833e1f | j_mayer | POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
262 | e1833e1f | j_mayer | POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
263 | e1833e1f | j_mayer | /* Trap */
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264 | e1833e1f | j_mayer | POWERPC_EXCP_TRAP = 0x40,
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265 | e1833e1f | j_mayer | }; |
266 | e1833e1f | j_mayer | |
267 | e1833e1f | j_mayer | /*****************************************************************************/
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268 | a750fc0b | j_mayer | /* Input pins model */
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269 | a750fc0b | j_mayer | enum {
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270 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_UNKNOWN = 0,
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271 | 2662a059 | j_mayer | /* PowerPC 6xx bus */
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272 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_6xx, |
273 | 2662a059 | j_mayer | /* BookE bus */
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274 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_BookE, |
275 | a750fc0b | j_mayer | /* PowerPC 405 bus */
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276 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_405, |
277 | 2662a059 | j_mayer | /* PowerPC 970 bus */
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278 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_970, |
279 | a750fc0b | j_mayer | /* PowerPC 401 bus */
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280 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_401, |
281 | 3fc6c082 | bellard | }; |
282 | 3fc6c082 | bellard | |
283 | a750fc0b | j_mayer | #define PPC_INPUT(env) (env->bus_model)
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284 | 3fc6c082 | bellard | |
285 | be147d08 | j_mayer | /*****************************************************************************/
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286 | 3fc6c082 | bellard | typedef struct ppc_def_t ppc_def_t; |
287 | a750fc0b | j_mayer | typedef struct opc_handler_t opc_handler_t; |
288 | 79aceca5 | bellard | |
289 | 3fc6c082 | bellard | /*****************************************************************************/
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290 | 3fc6c082 | bellard | /* Types used to describe some PowerPC registers */
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291 | 3fc6c082 | bellard | typedef struct CPUPPCState CPUPPCState; |
292 | 9fddaa0c | bellard | typedef struct ppc_tb_t ppc_tb_t; |
293 | 3fc6c082 | bellard | typedef struct ppc_spr_t ppc_spr_t; |
294 | 3fc6c082 | bellard | typedef struct ppc_dcr_t ppc_dcr_t; |
295 | 3fc6c082 | bellard | typedef struct ppc_avr_t ppc_avr_t; |
296 | 1d0a48fb | j_mayer | typedef union ppc_tlb_t ppc_tlb_t; |
297 | 76a66253 | j_mayer | |
298 | 3fc6c082 | bellard | /* SPR access micro-ops generations callbacks */
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299 | 3fc6c082 | bellard | struct ppc_spr_t {
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300 | 3fc6c082 | bellard | void (*uea_read)(void *opaque, int spr_num); |
301 | 3fc6c082 | bellard | void (*uea_write)(void *opaque, int spr_num); |
302 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
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303 | 3fc6c082 | bellard | void (*oea_read)(void *opaque, int spr_num); |
304 | 3fc6c082 | bellard | void (*oea_write)(void *opaque, int spr_num); |
305 | be147d08 | j_mayer | #if defined(TARGET_PPC64H)
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306 | be147d08 | j_mayer | void (*hea_read)(void *opaque, int spr_num); |
307 | be147d08 | j_mayer | void (*hea_write)(void *opaque, int spr_num); |
308 | be147d08 | j_mayer | #endif
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309 | 76a66253 | j_mayer | #endif
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310 | 3fc6c082 | bellard | const unsigned char *name; |
311 | 3fc6c082 | bellard | }; |
312 | 3fc6c082 | bellard | |
313 | 3fc6c082 | bellard | /* Altivec registers (128 bits) */
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314 | 3fc6c082 | bellard | struct ppc_avr_t {
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315 | 3fc6c082 | bellard | uint32_t u[4];
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316 | 3fc6c082 | bellard | }; |
317 | 9fddaa0c | bellard | |
318 | 3fc6c082 | bellard | /* Software TLB cache */
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319 | 1d0a48fb | j_mayer | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
320 | 1d0a48fb | j_mayer | struct ppc6xx_tlb_t {
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321 | 76a66253 | j_mayer | target_ulong pte0; |
322 | 76a66253 | j_mayer | target_ulong pte1; |
323 | 76a66253 | j_mayer | target_ulong EPN; |
324 | 1d0a48fb | j_mayer | }; |
325 | 1d0a48fb | j_mayer | |
326 | 1d0a48fb | j_mayer | typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
327 | 1d0a48fb | j_mayer | struct ppcemb_tlb_t {
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328 | c55e9aef | j_mayer | target_phys_addr_t RPN; |
329 | 1d0a48fb | j_mayer | target_ulong EPN; |
330 | 76a66253 | j_mayer | target_ulong PID; |
331 | c55e9aef | j_mayer | target_ulong size; |
332 | c55e9aef | j_mayer | uint32_t prot; |
333 | c55e9aef | j_mayer | uint32_t attr; /* Storage attributes */
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334 | 1d0a48fb | j_mayer | }; |
335 | 1d0a48fb | j_mayer | |
336 | 1d0a48fb | j_mayer | union ppc_tlb_t {
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337 | 1d0a48fb | j_mayer | ppc6xx_tlb_t tlb6; |
338 | 1d0a48fb | j_mayer | ppcemb_tlb_t tlbe; |
339 | 3fc6c082 | bellard | }; |
340 | 3fc6c082 | bellard | |
341 | 3fc6c082 | bellard | /*****************************************************************************/
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342 | 3fc6c082 | bellard | /* Machine state register bits definition */
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343 | 76a66253 | j_mayer | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
344 | 3fc6c082 | bellard | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
345 | 76a66253 | j_mayer | #define MSR_HV 60 /* hypervisor state hflags */ |
346 | 363be49c | j_mayer | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
347 | 363be49c | j_mayer | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
348 | 363be49c | j_mayer | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
349 | d26bfc9a | j_mayer | #define MSR_VR 25 /* altivec available x hflags */ |
350 | d26bfc9a | j_mayer | #define MSR_SPE 25 /* SPE enable for BookE x hflags */ |
351 | 76a66253 | j_mayer | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
352 | 76a66253 | j_mayer | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
353 | 3fc6c082 | bellard | #define MSR_KEY 19 /* key bit on 603e */ |
354 | d26bfc9a | j_mayer | #define MSR_POW 18 /* Power management x */ |
355 | d26bfc9a | j_mayer | #define MSR_WE 18 /* Wait state enable on embedded PowerPC x */ |
356 | d26bfc9a | j_mayer | #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
357 | d26bfc9a | j_mayer | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ |
358 | 3fc6c082 | bellard | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
359 | 3fc6c082 | bellard | #define MSR_EE 15 /* External interrupt enable */ |
360 | 76a66253 | j_mayer | #define MSR_PR 14 /* Problem state hflags */ |
361 | 76a66253 | j_mayer | #define MSR_FP 13 /* Floating point available hflags */ |
362 | 3fc6c082 | bellard | #define MSR_ME 12 /* Machine check interrupt enable */ |
363 | 76a66253 | j_mayer | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
364 | d26bfc9a | j_mayer | #define MSR_SE 10 /* Single-step trace enable x hflags */ |
365 | d26bfc9a | j_mayer | #define MSR_DWE 10 /* Debug wait enable on 405 x */ |
366 | d26bfc9a | j_mayer | #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ |
367 | d26bfc9a | j_mayer | #define MSR_BE 9 /* Branch trace enable x hflags */ |
368 | d26bfc9a | j_mayer | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ |
369 | 76a66253 | j_mayer | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
370 | 3fc6c082 | bellard | #define MSR_AL 7 /* AL bit on POWER */ |
371 | 3fc6c082 | bellard | #define MSR_IP 6 /* Interrupt prefix */ |
372 | 3fc6c082 | bellard | #define MSR_IR 5 /* Instruction relocate */ |
373 | 3fc6c082 | bellard | #define MSR_DR 4 /* Data relocate */ |
374 | d26bfc9a | j_mayer | #define MSR_PE 3 /* Protection enable on 403 x */ |
375 | d26bfc9a | j_mayer | #define MSR_EP 3 /* Exception prefix on 601 x */ |
376 | d26bfc9a | j_mayer | #define MSR_PX 2 /* Protection exclusive on 403 x */ |
377 | d26bfc9a | j_mayer | #define MSR_PMM 2 /* Performance monitor mark on POWER x */ |
378 | d26bfc9a | j_mayer | #define MSR_RI 1 /* Recoverable interrupt 1 */ |
379 | d26bfc9a | j_mayer | #define MSR_LE 0 /* Little-endian mode 1 hflags */ |
380 | 3fc6c082 | bellard | #define msr_sf env->msr[MSR_SF]
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381 | 3fc6c082 | bellard | #define msr_isf env->msr[MSR_ISF]
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382 | 3fc6c082 | bellard | #define msr_hv env->msr[MSR_HV]
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383 | 363be49c | j_mayer | #define msr_cm env->msr[MSR_CM]
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384 | 363be49c | j_mayer | #define msr_icm env->msr[MSR_ICM]
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385 | 76a66253 | j_mayer | #define msr_ucle env->msr[MSR_UCLE]
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386 | 3fc6c082 | bellard | #define msr_vr env->msr[MSR_VR]
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387 | 76a66253 | j_mayer | #define msr_spe env->msr[MSR_SPE]
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388 | 3fc6c082 | bellard | #define msr_ap env->msr[MSR_AP]
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389 | 3fc6c082 | bellard | #define msr_sa env->msr[MSR_SA]
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390 | 3fc6c082 | bellard | #define msr_key env->msr[MSR_KEY]
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391 | 76a66253 | j_mayer | #define msr_pow env->msr[MSR_POW]
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392 | 3fc6c082 | bellard | #define msr_we env->msr[MSR_WE]
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393 | 3fc6c082 | bellard | #define msr_tgpr env->msr[MSR_TGPR]
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394 | 3fc6c082 | bellard | #define msr_ce env->msr[MSR_CE]
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395 | 76a66253 | j_mayer | #define msr_ile env->msr[MSR_ILE]
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396 | 76a66253 | j_mayer | #define msr_ee env->msr[MSR_EE]
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397 | 76a66253 | j_mayer | #define msr_pr env->msr[MSR_PR]
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398 | 76a66253 | j_mayer | #define msr_fp env->msr[MSR_FP]
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399 | 76a66253 | j_mayer | #define msr_me env->msr[MSR_ME]
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400 | 76a66253 | j_mayer | #define msr_fe0 env->msr[MSR_FE0]
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401 | 76a66253 | j_mayer | #define msr_se env->msr[MSR_SE]
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402 | 3fc6c082 | bellard | #define msr_dwe env->msr[MSR_DWE]
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403 | 76a66253 | j_mayer | #define msr_uble env->msr[MSR_UBLE]
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404 | 76a66253 | j_mayer | #define msr_be env->msr[MSR_BE]
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405 | 3fc6c082 | bellard | #define msr_de env->msr[MSR_DE]
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406 | 76a66253 | j_mayer | #define msr_fe1 env->msr[MSR_FE1]
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407 | 3fc6c082 | bellard | #define msr_al env->msr[MSR_AL]
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408 | 76a66253 | j_mayer | #define msr_ip env->msr[MSR_IP]
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409 | 76a66253 | j_mayer | #define msr_ir env->msr[MSR_IR]
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410 | 76a66253 | j_mayer | #define msr_dr env->msr[MSR_DR]
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411 | 3fc6c082 | bellard | #define msr_pe env->msr[MSR_PE]
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412 | 3fc6c082 | bellard | #define msr_ep env->msr[MSR_EP]
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413 | 3fc6c082 | bellard | #define msr_px env->msr[MSR_PX]
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414 | 3fc6c082 | bellard | #define msr_pmm env->msr[MSR_PMM]
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415 | 76a66253 | j_mayer | #define msr_ri env->msr[MSR_RI]
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416 | 76a66253 | j_mayer | #define msr_le env->msr[MSR_LE]
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417 | 79aceca5 | bellard | |
418 | d26bfc9a | j_mayer | enum {
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419 | d26bfc9a | j_mayer | /* Beware that MSR bits are given using IBM standard (ie MSB is 0 !) */
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420 | d26bfc9a | j_mayer | POWERPC_FLAG_NONE = 0x00000000,
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421 | d26bfc9a | j_mayer | /* Flag for MSR bit 25 signification (VRE/SPE) */
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422 | d26bfc9a | j_mayer | POWERPC_FLAG_SPE = 0x00000001,
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423 | d26bfc9a | j_mayer | POWERPC_FLAG_VRE = 0x00000002,
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424 | d26bfc9a | j_mayer | /* Flag for MSR bit 18 may not be needed... */
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425 | d26bfc9a | j_mayer | POWERPC_FLAG_POW = 0x00000004,
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426 | d26bfc9a | j_mayer | POWERPC_FLAG_WE = 0x00000008,
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427 | d26bfc9a | j_mayer | /* Flag for MSR bit 17 signification (TGPR/CE) */
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428 | d26bfc9a | j_mayer | POWERPC_FLAG_TGPR = 0x00000010,
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429 | d26bfc9a | j_mayer | POWERPC_FLAG_CE = 0x00000020,
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430 | d26bfc9a | j_mayer | /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
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431 | d26bfc9a | j_mayer | POWERPC_FLAG_SE = 0x00000040,
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432 | d26bfc9a | j_mayer | POWERPC_FLAG_DWE = 0x00000080,
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433 | d26bfc9a | j_mayer | POWERPC_FLAG_UBLE = 0x00000100,
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434 | d26bfc9a | j_mayer | /* Flag for MSR bit 9 signification (BE/DE) */
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435 | d26bfc9a | j_mayer | POWERPC_FLAG_BE = 0x00000200,
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436 | d26bfc9a | j_mayer | POWERPC_FLAG_DE = 0x00000400,
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437 | d26bfc9a | j_mayer | /* Flag for MSR bit 3 signification (PE/EP) */
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438 | d26bfc9a | j_mayer | POWERPC_FLAG_PE = 0x00000800,
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439 | d26bfc9a | j_mayer | POWERPC_FLAG_EP = 0x00001000,
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440 | d26bfc9a | j_mayer | /* Flag for MSR but 2 signification (PX/PMM) */
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441 | d26bfc9a | j_mayer | POWERPC_FLAG_PX = 0x00002000,
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442 | d26bfc9a | j_mayer | POWERPC_FLAG_PMM = 0x00004000,
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443 | d26bfc9a | j_mayer | }; |
444 | d26bfc9a | j_mayer | |
445 | 3fc6c082 | bellard | /*****************************************************************************/
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446 | 3fc6c082 | bellard | /* The whole PowerPC CPU context */
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447 | 3fc6c082 | bellard | struct CPUPPCState {
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448 | 3fc6c082 | bellard | /* First are the most commonly used resources
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449 | 3fc6c082 | bellard | * during translated code execution
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450 | 3fc6c082 | bellard | */
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451 | 0487d6a8 | j_mayer | #if TARGET_GPR_BITS > HOST_LONG_BITS
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452 | 3fc6c082 | bellard | /* temporary fixed-point registers
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453 | 3fc6c082 | bellard | * used to emulate 64 bits target on 32 bits hosts
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454 | 5fafdf24 | ths | */
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455 | 3c4c9f9f | ths | ppc_gpr_t t0, t1, t2; |
456 | 3fc6c082 | bellard | #endif
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457 | d9bce9d9 | j_mayer | ppc_avr_t t0_avr, t1_avr, t2_avr; |
458 | d9bce9d9 | j_mayer | |
459 | 79aceca5 | bellard | /* general purpose registers */
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460 | 76a66253 | j_mayer | ppc_gpr_t gpr[32];
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461 | 3fc6c082 | bellard | /* LR */
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462 | 3fc6c082 | bellard | target_ulong lr; |
463 | 3fc6c082 | bellard | /* CTR */
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464 | 3fc6c082 | bellard | target_ulong ctr; |
465 | 3fc6c082 | bellard | /* condition register */
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466 | 3fc6c082 | bellard | uint8_t crf[8];
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467 | 79aceca5 | bellard | /* XER */
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468 | 3fc6c082 | bellard | /* XXX: We use only 5 fields, but we want to keep the structure aligned */
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469 | 3fc6c082 | bellard | uint8_t xer[8];
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470 | 79aceca5 | bellard | /* Reservation address */
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471 | 3fc6c082 | bellard | target_ulong reserve; |
472 | 3fc6c082 | bellard | |
473 | 3fc6c082 | bellard | /* Those ones are used in supervisor mode only */
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474 | 79aceca5 | bellard | /* machine state register */
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475 | 3fc6c082 | bellard | uint8_t msr[64];
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476 | 3fc6c082 | bellard | /* temporary general purpose registers */
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477 | 76a66253 | j_mayer | ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
478 | 3fc6c082 | bellard | |
479 | 3fc6c082 | bellard | /* Floating point execution context */
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480 | 76a66253 | j_mayer | /* temporary float registers */
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481 | 4ecc3190 | bellard | float64 ft0; |
482 | 4ecc3190 | bellard | float64 ft1; |
483 | 4ecc3190 | bellard | float64 ft2; |
484 | 4ecc3190 | bellard | float_status fp_status; |
485 | 3fc6c082 | bellard | /* floating point registers */
|
486 | 3fc6c082 | bellard | float64 fpr[32];
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487 | 3fc6c082 | bellard | /* floating point status and control register */
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488 | 3fc6c082 | bellard | uint8_t fpscr[8];
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489 | 4ecc3190 | bellard | |
490 | a316d335 | bellard | CPU_COMMON |
491 | a316d335 | bellard | |
492 | 50443c98 | bellard | int halted; /* TRUE if the CPU is in suspend state */ |
493 | 50443c98 | bellard | |
494 | ac9eb073 | bellard | int access_type; /* when a memory exception occurs, the access |
495 | ac9eb073 | bellard | type is stored here */
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496 | a541f297 | bellard | |
497 | f2e63a42 | j_mayer | /* MMU context - only relevant for full system emulation */
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498 | f2e63a42 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
499 | f2e63a42 | j_mayer | #if defined(TARGET_PPC64)
|
500 | 3fc6c082 | bellard | /* Address space register */
|
501 | 3fc6c082 | bellard | target_ulong asr; |
502 | f2e63a42 | j_mayer | /* PowerPC 64 SLB area */
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503 | f2e63a42 | j_mayer | int slb_nr;
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504 | f2e63a42 | j_mayer | #endif
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505 | 3fc6c082 | bellard | /* segment registers */
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506 | 3fc6c082 | bellard | target_ulong sdr1; |
507 | 3fc6c082 | bellard | target_ulong sr[16];
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508 | 3fc6c082 | bellard | /* BATs */
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509 | 3fc6c082 | bellard | int nb_BATs;
|
510 | 3fc6c082 | bellard | target_ulong DBAT[2][8]; |
511 | 3fc6c082 | bellard | target_ulong IBAT[2][8]; |
512 | f2e63a42 | j_mayer | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
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513 | f2e63a42 | j_mayer | int nb_tlb; /* Total number of TLB */ |
514 | f2e63a42 | j_mayer | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
515 | f2e63a42 | j_mayer | int nb_ways; /* Number of ways in the TLB set */ |
516 | f2e63a42 | j_mayer | int last_way; /* Last used way used to allocate TLB in a LRU way */ |
517 | f2e63a42 | j_mayer | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
518 | f2e63a42 | j_mayer | int nb_pids; /* Number of available PID registers */ |
519 | f2e63a42 | j_mayer | ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
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520 | f2e63a42 | j_mayer | /* 403 dedicated access protection registers */
|
521 | f2e63a42 | j_mayer | target_ulong pb[4];
|
522 | f2e63a42 | j_mayer | #endif
|
523 | 9fddaa0c | bellard | |
524 | 3fc6c082 | bellard | /* Other registers */
|
525 | 3fc6c082 | bellard | /* Special purpose registers */
|
526 | 3fc6c082 | bellard | target_ulong spr[1024];
|
527 | f2e63a42 | j_mayer | ppc_spr_t spr_cb[1024];
|
528 | 3fc6c082 | bellard | /* Altivec registers */
|
529 | 3fc6c082 | bellard | ppc_avr_t avr[32];
|
530 | 3fc6c082 | bellard | uint32_t vscr; |
531 | f2e63a42 | j_mayer | #if defined(TARGET_PPCEMB)
|
532 | d9bce9d9 | j_mayer | /* SPE registers */
|
533 | d9bce9d9 | j_mayer | ppc_gpr_t spe_acc; |
534 | 0487d6a8 | j_mayer | float_status spe_status; |
535 | d9bce9d9 | j_mayer | uint32_t spe_fscr; |
536 | f2e63a42 | j_mayer | #endif
|
537 | 3fc6c082 | bellard | |
538 | 3fc6c082 | bellard | /* Internal devices resources */
|
539 | 9fddaa0c | bellard | /* Time base and decrementer */
|
540 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
541 | 3fc6c082 | bellard | /* Device control registers */
|
542 | 3fc6c082 | bellard | ppc_dcr_t *dcr_env; |
543 | 3fc6c082 | bellard | |
544 | d63001d1 | j_mayer | int dcache_line_size;
|
545 | d63001d1 | j_mayer | int icache_line_size;
|
546 | d63001d1 | j_mayer | |
547 | 3fc6c082 | bellard | /* Those resources are used during exception processing */
|
548 | 3fc6c082 | bellard | /* CPU model definition */
|
549 | a750fc0b | j_mayer | target_ulong msr_mask; |
550 | a750fc0b | j_mayer | uint8_t mmu_model; |
551 | a750fc0b | j_mayer | uint8_t excp_model; |
552 | a750fc0b | j_mayer | uint8_t bus_model; |
553 | a750fc0b | j_mayer | uint8_t pad; |
554 | 237c0af0 | j_mayer | int bfd_mach;
|
555 | 3fc6c082 | bellard | uint32_t flags; |
556 | 3fc6c082 | bellard | |
557 | 3fc6c082 | bellard | int exception_index;
|
558 | 3fc6c082 | bellard | int error_code;
|
559 | 3fc6c082 | bellard | int interrupt_request;
|
560 | 47103572 | j_mayer | uint32_t pending_interrupts; |
561 | e9df014c | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
562 | e9df014c | j_mayer | /* This is the IRQ controller, which is implementation dependant
|
563 | e9df014c | j_mayer | * and only relevant when emulating a complete machine.
|
564 | e9df014c | j_mayer | */
|
565 | e9df014c | j_mayer | uint32_t irq_input_state; |
566 | e9df014c | j_mayer | void **irq_inputs;
|
567 | e1833e1f | j_mayer | /* Exception vectors */
|
568 | e1833e1f | j_mayer | target_ulong excp_vectors[POWERPC_EXCP_NB]; |
569 | e1833e1f | j_mayer | target_ulong excp_prefix; |
570 | e1833e1f | j_mayer | target_ulong ivor_mask; |
571 | e1833e1f | j_mayer | target_ulong ivpr_mask; |
572 | d63001d1 | j_mayer | target_ulong hreset_vector; |
573 | e9df014c | j_mayer | #endif
|
574 | 3fc6c082 | bellard | |
575 | 3fc6c082 | bellard | /* Those resources are used only during code translation */
|
576 | 3fc6c082 | bellard | /* Next instruction pointer */
|
577 | 3fc6c082 | bellard | target_ulong nip; |
578 | f2e63a42 | j_mayer | |
579 | 3fc6c082 | bellard | /* opcode handlers */
|
580 | 3fc6c082 | bellard | opc_handler_t *opcodes[0x40];
|
581 | 3fc6c082 | bellard | |
582 | 3fc6c082 | bellard | /* Those resources are used only in Qemu core */
|
583 | 3fc6c082 | bellard | jmp_buf jmp_env; |
584 | 3fc6c082 | bellard | int user_mode_only; /* user mode only simulation */ |
585 | 4296f459 | j_mayer | target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
|
586 | 3fc6c082 | bellard | |
587 | 9fddaa0c | bellard | /* Power management */
|
588 | 9fddaa0c | bellard | int power_mode;
|
589 | a541f297 | bellard | |
590 | 6d506e6d | bellard | /* temporary hack to handle OSI calls (only used if non NULL) */
|
591 | 6d506e6d | bellard | int (*osi_call)(struct CPUPPCState *env); |
592 | 3fc6c082 | bellard | }; |
593 | 79aceca5 | bellard | |
594 | 76a66253 | j_mayer | /* Context used internally during MMU translations */
|
595 | 76a66253 | j_mayer | typedef struct mmu_ctx_t mmu_ctx_t; |
596 | 76a66253 | j_mayer | struct mmu_ctx_t {
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597 | 76a66253 | j_mayer | target_phys_addr_t raddr; /* Real address */
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598 | 76a66253 | j_mayer | int prot; /* Protection bits */ |
599 | 76a66253 | j_mayer | target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ |
600 | 76a66253 | j_mayer | target_ulong ptem; /* Virtual segment ID | API */
|
601 | 76a66253 | j_mayer | int key; /* Access key */ |
602 | 76a66253 | j_mayer | }; |
603 | 76a66253 | j_mayer | |
604 | 3fc6c082 | bellard | /*****************************************************************************/
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605 | 36081602 | j_mayer | CPUPPCState *cpu_ppc_init (void);
|
606 | 36081602 | j_mayer | int cpu_ppc_exec (CPUPPCState *s);
|
607 | 36081602 | j_mayer | void cpu_ppc_close (CPUPPCState *s);
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608 | 79aceca5 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
609 | 79aceca5 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
|
610 | 79aceca5 | bellard | is returned if the signal was handled by the virtual CPU. */
|
611 | 36081602 | j_mayer | int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
612 | 36081602 | j_mayer | void *puc);
|
613 | 79aceca5 | bellard | |
614 | a541f297 | bellard | void do_interrupt (CPUPPCState *env);
|
615 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUPPCState *env);
|
616 | 36081602 | j_mayer | void cpu_loop_exit (void); |
617 | a541f297 | bellard | |
618 | 9a64fbe4 | bellard | void dump_stack (CPUPPCState *env);
|
619 | a541f297 | bellard | |
620 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
621 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr);
|
622 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr);
|
623 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
624 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
625 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr);
|
626 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr);
|
627 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
628 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
629 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env); |
630 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value);
|
631 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
632 | d9bce9d9 | j_mayer | target_ulong ppc_load_asr (CPUPPCState *env); |
633 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value);
|
634 | 12de9a39 | j_mayer | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
|
635 | 12de9a39 | j_mayer | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs); |
636 | 12de9a39 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
637 | 12de9a39 | j_mayer | #if 0 // Unused
|
638 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum);
|
639 | 76a66253 | j_mayer | #endif
|
640 | 12de9a39 | j_mayer | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
641 | 12de9a39 | j_mayer | #endif /* !defined(CONFIG_USER_ONLY) */ |
642 | bfa1e5cf | j_mayer | target_ulong ppc_load_xer (CPUPPCState *env); |
643 | bfa1e5cf | j_mayer | void ppc_store_xer (CPUPPCState *env, target_ulong value);
|
644 | 3fc6c082 | bellard | target_ulong do_load_msr (CPUPPCState *env); |
645 | a97fed52 | j_mayer | int do_store_msr (CPUPPCState *env, target_ulong value);
|
646 | be147d08 | j_mayer | #if defined(TARGET_PPC64)
|
647 | a97fed52 | j_mayer | int ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
|
648 | be147d08 | j_mayer | #endif
|
649 | 3fc6c082 | bellard | |
650 | 3fc6c082 | bellard | void do_compute_hflags (CPUPPCState *env);
|
651 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque); |
652 | 0a032cbe | j_mayer | CPUPPCState *cpu_ppc_init (void);
|
653 | 0a032cbe | j_mayer | void cpu_ppc_close(CPUPPCState *env);
|
654 | a541f297 | bellard | |
655 | 3fc6c082 | bellard | int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
656 | 3fc6c082 | bellard | int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
|
657 | 3fc6c082 | bellard | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
658 | 3fc6c082 | bellard | int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
|
659 | 85c4adf6 | bellard | |
660 | 9fddaa0c | bellard | /* Time-base and decrementer management */
|
661 | 9fddaa0c | bellard | #ifndef NO_CPU_IO_DEFS
|
662 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
663 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
664 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
|
665 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
|
666 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbl (CPUPPCState *env); |
667 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbu (CPUPPCState *env); |
668 | a062e36c | j_mayer | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
|
669 | a062e36c | j_mayer | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
|
670 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
671 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
|
672 | 58a7d328 | j_mayer | #if defined(TARGET_PPC64H)
|
673 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); |
674 | 58a7d328 | j_mayer | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
|
675 | 58a7d328 | j_mayer | uint64_t cpu_ppc_load_purr (CPUPPCState *env); |
676 | 58a7d328 | j_mayer | void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
|
677 | 58a7d328 | j_mayer | #endif
|
678 | d9bce9d9 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
679 | d9bce9d9 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
680 | d9bce9d9 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
681 | d9bce9d9 | j_mayer | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
|
682 | d9bce9d9 | j_mayer | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
|
683 | d9bce9d9 | j_mayer | target_ulong load_40x_pit (CPUPPCState *env); |
684 | d9bce9d9 | j_mayer | void store_40x_pit (CPUPPCState *env, target_ulong val);
|
685 | 8ecc7913 | j_mayer | void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
|
686 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val);
|
687 | d9bce9d9 | j_mayer | void store_booke_tcr (CPUPPCState *env, target_ulong val);
|
688 | d9bce9d9 | j_mayer | void store_booke_tsr (CPUPPCState *env, target_ulong val);
|
689 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env);
|
690 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
|
691 | daf4f96e | j_mayer | #if defined(TARGET_PPC64)
|
692 | daf4f96e | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env);
|
693 | daf4f96e | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
|
694 | daf4f96e | j_mayer | #endif
|
695 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
|
696 | d9bce9d9 | j_mayer | #endif
|
697 | 9fddaa0c | bellard | #endif
|
698 | 79aceca5 | bellard | |
699 | 2e719ba3 | j_mayer | /* Device control registers */
|
700 | 2e719ba3 | j_mayer | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); |
701 | 2e719ba3 | j_mayer | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); |
702 | 2e719ba3 | j_mayer | |
703 | 9467d44c | ths | #define CPUState CPUPPCState
|
704 | 9467d44c | ths | #define cpu_init cpu_ppc_init
|
705 | 9467d44c | ths | #define cpu_exec cpu_ppc_exec
|
706 | 9467d44c | ths | #define cpu_gen_code cpu_ppc_gen_code
|
707 | 9467d44c | ths | #define cpu_signal_handler cpu_ppc_signal_handler
|
708 | 9467d44c | ths | |
709 | 79aceca5 | bellard | #include "cpu-all.h" |
710 | 79aceca5 | bellard | |
711 | 3fc6c082 | bellard | /*****************************************************************************/
|
712 | 3fc6c082 | bellard | /* Registers definitions */
|
713 | 79aceca5 | bellard | #define XER_SO 31 |
714 | 79aceca5 | bellard | #define XER_OV 30 |
715 | 79aceca5 | bellard | #define XER_CA 29 |
716 | 3fc6c082 | bellard | #define XER_CMP 8 |
717 | 36081602 | j_mayer | #define XER_BC 0 |
718 | 3fc6c082 | bellard | #define xer_so env->xer[4] |
719 | 3fc6c082 | bellard | #define xer_ov env->xer[6] |
720 | 3fc6c082 | bellard | #define xer_ca env->xer[2] |
721 | 3fc6c082 | bellard | #define xer_cmp env->xer[1] |
722 | 36081602 | j_mayer | #define xer_bc env->xer[0] |
723 | 79aceca5 | bellard | |
724 | 3fc6c082 | bellard | /* SPR definitions */
|
725 | 76a66253 | j_mayer | #define SPR_MQ (0x000) |
726 | 76a66253 | j_mayer | #define SPR_XER (0x001) |
727 | 76a66253 | j_mayer | #define SPR_601_VRTCU (0x004) |
728 | 76a66253 | j_mayer | #define SPR_601_VRTCL (0x005) |
729 | 76a66253 | j_mayer | #define SPR_601_UDECR (0x006) |
730 | 76a66253 | j_mayer | #define SPR_LR (0x008) |
731 | 76a66253 | j_mayer | #define SPR_CTR (0x009) |
732 | 76a66253 | j_mayer | #define SPR_DSISR (0x012) |
733 | a750fc0b | j_mayer | #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
734 | 76a66253 | j_mayer | #define SPR_601_RTCU (0x014) |
735 | 76a66253 | j_mayer | #define SPR_601_RTCL (0x015) |
736 | 76a66253 | j_mayer | #define SPR_DECR (0x016) |
737 | 76a66253 | j_mayer | #define SPR_SDR1 (0x019) |
738 | 76a66253 | j_mayer | #define SPR_SRR0 (0x01A) |
739 | 76a66253 | j_mayer | #define SPR_SRR1 (0x01B) |
740 | 2662a059 | j_mayer | #define SPR_AMR (0x01D) |
741 | 76a66253 | j_mayer | #define SPR_BOOKE_PID (0x030) |
742 | 76a66253 | j_mayer | #define SPR_BOOKE_DECAR (0x036) |
743 | 363be49c | j_mayer | #define SPR_BOOKE_CSRR0 (0x03A) |
744 | 363be49c | j_mayer | #define SPR_BOOKE_CSRR1 (0x03B) |
745 | 76a66253 | j_mayer | #define SPR_BOOKE_DEAR (0x03D) |
746 | 76a66253 | j_mayer | #define SPR_BOOKE_ESR (0x03E) |
747 | 363be49c | j_mayer | #define SPR_BOOKE_IVPR (0x03F) |
748 | 76a66253 | j_mayer | #define SPR_8xx_EIE (0x050) |
749 | 76a66253 | j_mayer | #define SPR_8xx_EID (0x051) |
750 | 76a66253 | j_mayer | #define SPR_8xx_NRE (0x052) |
751 | 2662a059 | j_mayer | #define SPR_CTRL (0x088) |
752 | 76a66253 | j_mayer | #define SPR_58x_CMPA (0x090) |
753 | 76a66253 | j_mayer | #define SPR_58x_CMPB (0x091) |
754 | 76a66253 | j_mayer | #define SPR_58x_CMPC (0x092) |
755 | 76a66253 | j_mayer | #define SPR_58x_CMPD (0x093) |
756 | 76a66253 | j_mayer | #define SPR_58x_ICR (0x094) |
757 | 76a66253 | j_mayer | #define SPR_58x_DER (0x094) |
758 | 76a66253 | j_mayer | #define SPR_58x_COUNTA (0x096) |
759 | 76a66253 | j_mayer | #define SPR_58x_COUNTB (0x097) |
760 | 2662a059 | j_mayer | #define SPR_UCTRL (0x098) |
761 | 76a66253 | j_mayer | #define SPR_58x_CMPE (0x098) |
762 | 76a66253 | j_mayer | #define SPR_58x_CMPF (0x099) |
763 | 76a66253 | j_mayer | #define SPR_58x_CMPG (0x09A) |
764 | 76a66253 | j_mayer | #define SPR_58x_CMPH (0x09B) |
765 | 76a66253 | j_mayer | #define SPR_58x_LCTRL1 (0x09C) |
766 | 76a66253 | j_mayer | #define SPR_58x_LCTRL2 (0x09D) |
767 | 76a66253 | j_mayer | #define SPR_58x_ICTRL (0x09E) |
768 | 76a66253 | j_mayer | #define SPR_58x_BAR (0x09F) |
769 | 76a66253 | j_mayer | #define SPR_VRSAVE (0x100) |
770 | 76a66253 | j_mayer | #define SPR_USPRG0 (0x100) |
771 | 363be49c | j_mayer | #define SPR_USPRG1 (0x101) |
772 | 363be49c | j_mayer | #define SPR_USPRG2 (0x102) |
773 | 363be49c | j_mayer | #define SPR_USPRG3 (0x103) |
774 | 76a66253 | j_mayer | #define SPR_USPRG4 (0x104) |
775 | 76a66253 | j_mayer | #define SPR_USPRG5 (0x105) |
776 | 76a66253 | j_mayer | #define SPR_USPRG6 (0x106) |
777 | 76a66253 | j_mayer | #define SPR_USPRG7 (0x107) |
778 | 76a66253 | j_mayer | #define SPR_VTBL (0x10C) |
779 | 76a66253 | j_mayer | #define SPR_VTBU (0x10D) |
780 | 76a66253 | j_mayer | #define SPR_SPRG0 (0x110) |
781 | 76a66253 | j_mayer | #define SPR_SPRG1 (0x111) |
782 | 76a66253 | j_mayer | #define SPR_SPRG2 (0x112) |
783 | 76a66253 | j_mayer | #define SPR_SPRG3 (0x113) |
784 | 76a66253 | j_mayer | #define SPR_SPRG4 (0x114) |
785 | 76a66253 | j_mayer | #define SPR_SCOMC (0x114) |
786 | 76a66253 | j_mayer | #define SPR_SPRG5 (0x115) |
787 | 76a66253 | j_mayer | #define SPR_SCOMD (0x115) |
788 | 76a66253 | j_mayer | #define SPR_SPRG6 (0x116) |
789 | 76a66253 | j_mayer | #define SPR_SPRG7 (0x117) |
790 | 76a66253 | j_mayer | #define SPR_ASR (0x118) |
791 | 76a66253 | j_mayer | #define SPR_EAR (0x11A) |
792 | 76a66253 | j_mayer | #define SPR_TBL (0x11C) |
793 | 76a66253 | j_mayer | #define SPR_TBU (0x11D) |
794 | 2662a059 | j_mayer | #define SPR_TBU40 (0x11E) |
795 | 76a66253 | j_mayer | #define SPR_SVR (0x11E) |
796 | 76a66253 | j_mayer | #define SPR_BOOKE_PIR (0x11E) |
797 | 76a66253 | j_mayer | #define SPR_PVR (0x11F) |
798 | 76a66253 | j_mayer | #define SPR_HSPRG0 (0x130) |
799 | 76a66253 | j_mayer | #define SPR_BOOKE_DBSR (0x130) |
800 | 76a66253 | j_mayer | #define SPR_HSPRG1 (0x131) |
801 | 2662a059 | j_mayer | #define SPR_HDSISR (0x132) |
802 | 2662a059 | j_mayer | #define SPR_HDAR (0x133) |
803 | 76a66253 | j_mayer | #define SPR_BOOKE_DBCR0 (0x134) |
804 | 76a66253 | j_mayer | #define SPR_IBCR (0x135) |
805 | 2662a059 | j_mayer | #define SPR_PURR (0x135) |
806 | 76a66253 | j_mayer | #define SPR_BOOKE_DBCR1 (0x135) |
807 | 76a66253 | j_mayer | #define SPR_DBCR (0x136) |
808 | 76a66253 | j_mayer | #define SPR_HDEC (0x136) |
809 | 76a66253 | j_mayer | #define SPR_BOOKE_DBCR2 (0x136) |
810 | 76a66253 | j_mayer | #define SPR_HIOR (0x137) |
811 | 76a66253 | j_mayer | #define SPR_MBAR (0x137) |
812 | 76a66253 | j_mayer | #define SPR_RMOR (0x138) |
813 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC1 (0x138) |
814 | 76a66253 | j_mayer | #define SPR_HRMOR (0x139) |
815 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC2 (0x139) |
816 | e1833e1f | j_mayer | #define SPR_HSRR0 (0x13A) |
817 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC3 (0x13A) |
818 | e1833e1f | j_mayer | #define SPR_HSRR1 (0x13B) |
819 | 76a66253 | j_mayer | #define SPR_BOOKE_IAC4 (0x13B) |
820 | 76a66253 | j_mayer | #define SPR_LPCR (0x13C) |
821 | 76a66253 | j_mayer | #define SPR_BOOKE_DAC1 (0x13C) |
822 | 76a66253 | j_mayer | #define SPR_LPIDR (0x13D) |
823 | 76a66253 | j_mayer | #define SPR_DABR2 (0x13D) |
824 | 76a66253 | j_mayer | #define SPR_BOOKE_DAC2 (0x13D) |
825 | 76a66253 | j_mayer | #define SPR_BOOKE_DVC1 (0x13E) |
826 | 76a66253 | j_mayer | #define SPR_BOOKE_DVC2 (0x13F) |
827 | 76a66253 | j_mayer | #define SPR_BOOKE_TSR (0x150) |
828 | 76a66253 | j_mayer | #define SPR_BOOKE_TCR (0x154) |
829 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR0 (0x190) |
830 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR1 (0x191) |
831 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR2 (0x192) |
832 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR3 (0x193) |
833 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR4 (0x194) |
834 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR5 (0x195) |
835 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR6 (0x196) |
836 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR7 (0x197) |
837 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR8 (0x198) |
838 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR9 (0x199) |
839 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR10 (0x19A) |
840 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR11 (0x19B) |
841 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR12 (0x19C) |
842 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR13 (0x19D) |
843 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR14 (0x19E) |
844 | 76a66253 | j_mayer | #define SPR_BOOKE_IVOR15 (0x19F) |
845 | 2662a059 | j_mayer | #define SPR_BOOKE_SPEFSCR (0x200) |
846 | 76a66253 | j_mayer | #define SPR_E500_BBEAR (0x201) |
847 | 76a66253 | j_mayer | #define SPR_E500_BBTAR (0x202) |
848 | a062e36c | j_mayer | #define SPR_ATBL (0x20E) |
849 | a062e36c | j_mayer | #define SPR_ATBU (0x20F) |
850 | 76a66253 | j_mayer | #define SPR_IBAT0U (0x210) |
851 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR32 (0x210) |
852 | 76a66253 | j_mayer | #define SPR_IBAT0L (0x211) |
853 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR33 (0x211) |
854 | 76a66253 | j_mayer | #define SPR_IBAT1U (0x212) |
855 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR34 (0x212) |
856 | 76a66253 | j_mayer | #define SPR_IBAT1L (0x213) |
857 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR35 (0x213) |
858 | 76a66253 | j_mayer | #define SPR_IBAT2U (0x214) |
859 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR36 (0x214) |
860 | 76a66253 | j_mayer | #define SPR_IBAT2L (0x215) |
861 | 76a66253 | j_mayer | #define SPR_E500_L1CFG0 (0x215) |
862 | 363be49c | j_mayer | #define SPR_BOOKE_IVOR37 (0x215) |
863 | 76a66253 | j_mayer | #define SPR_IBAT3U (0x216) |
864 | 76a66253 | j_mayer | #define SPR_E500_L1CFG1 (0x216) |
865 | 76a66253 | j_mayer | #define SPR_IBAT3L (0x217) |
866 | 76a66253 | j_mayer | #define SPR_DBAT0U (0x218) |
867 | 76a66253 | j_mayer | #define SPR_DBAT0L (0x219) |
868 | 76a66253 | j_mayer | #define SPR_DBAT1U (0x21A) |
869 | 76a66253 | j_mayer | #define SPR_DBAT1L (0x21B) |
870 | 76a66253 | j_mayer | #define SPR_DBAT2U (0x21C) |
871 | 76a66253 | j_mayer | #define SPR_DBAT2L (0x21D) |
872 | 76a66253 | j_mayer | #define SPR_DBAT3U (0x21E) |
873 | 76a66253 | j_mayer | #define SPR_DBAT3L (0x21F) |
874 | 76a66253 | j_mayer | #define SPR_IBAT4U (0x230) |
875 | 76a66253 | j_mayer | #define SPR_IBAT4L (0x231) |
876 | 76a66253 | j_mayer | #define SPR_IBAT5U (0x232) |
877 | 76a66253 | j_mayer | #define SPR_IBAT5L (0x233) |
878 | 76a66253 | j_mayer | #define SPR_IBAT6U (0x234) |
879 | 76a66253 | j_mayer | #define SPR_IBAT6L (0x235) |
880 | 76a66253 | j_mayer | #define SPR_IBAT7U (0x236) |
881 | 76a66253 | j_mayer | #define SPR_IBAT7L (0x237) |
882 | 76a66253 | j_mayer | #define SPR_DBAT4U (0x238) |
883 | 76a66253 | j_mayer | #define SPR_DBAT4L (0x239) |
884 | 76a66253 | j_mayer | #define SPR_DBAT5U (0x23A) |
885 | 363be49c | j_mayer | #define SPR_BOOKE_MCSRR0 (0x23A) |
886 | 76a66253 | j_mayer | #define SPR_DBAT5L (0x23B) |
887 | 363be49c | j_mayer | #define SPR_BOOKE_MCSRR1 (0x23B) |
888 | 76a66253 | j_mayer | #define SPR_DBAT6U (0x23C) |
889 | 363be49c | j_mayer | #define SPR_BOOKE_MCSR (0x23C) |
890 | 76a66253 | j_mayer | #define SPR_DBAT6L (0x23D) |
891 | 76a66253 | j_mayer | #define SPR_E500_MCAR (0x23D) |
892 | 76a66253 | j_mayer | #define SPR_DBAT7U (0x23E) |
893 | 363be49c | j_mayer | #define SPR_BOOKE_DSRR0 (0x23E) |
894 | 76a66253 | j_mayer | #define SPR_DBAT7L (0x23F) |
895 | 363be49c | j_mayer | #define SPR_BOOKE_DSRR1 (0x23F) |
896 | 363be49c | j_mayer | #define SPR_BOOKE_SPRG8 (0x25C) |
897 | 363be49c | j_mayer | #define SPR_BOOKE_SPRG9 (0x25D) |
898 | 363be49c | j_mayer | #define SPR_BOOKE_MAS0 (0x270) |
899 | 363be49c | j_mayer | #define SPR_BOOKE_MAS1 (0x271) |
900 | 363be49c | j_mayer | #define SPR_BOOKE_MAS2 (0x272) |
901 | 363be49c | j_mayer | #define SPR_BOOKE_MAS3 (0x273) |
902 | 363be49c | j_mayer | #define SPR_BOOKE_MAS4 (0x274) |
903 | 363be49c | j_mayer | #define SPR_BOOKE_MAS6 (0x276) |
904 | 363be49c | j_mayer | #define SPR_BOOKE_PID1 (0x279) |
905 | 363be49c | j_mayer | #define SPR_BOOKE_PID2 (0x27A) |
906 | 363be49c | j_mayer | #define SPR_BOOKE_TLB0CFG (0x2B0) |
907 | 363be49c | j_mayer | #define SPR_BOOKE_TLB1CFG (0x2B1) |
908 | 363be49c | j_mayer | #define SPR_BOOKE_TLB2CFG (0x2B2) |
909 | 363be49c | j_mayer | #define SPR_BOOKE_TLB3CFG (0x2B3) |
910 | 363be49c | j_mayer | #define SPR_BOOKE_EPR (0x2BE) |
911 | 2662a059 | j_mayer | #define SPR_PERF0 (0x300) |
912 | 2662a059 | j_mayer | #define SPR_PERF1 (0x301) |
913 | 2662a059 | j_mayer | #define SPR_PERF2 (0x302) |
914 | 2662a059 | j_mayer | #define SPR_PERF3 (0x303) |
915 | 2662a059 | j_mayer | #define SPR_PERF4 (0x304) |
916 | 2662a059 | j_mayer | #define SPR_PERF5 (0x305) |
917 | 2662a059 | j_mayer | #define SPR_PERF6 (0x306) |
918 | 2662a059 | j_mayer | #define SPR_PERF7 (0x307) |
919 | 2662a059 | j_mayer | #define SPR_PERF8 (0x308) |
920 | 2662a059 | j_mayer | #define SPR_PERF9 (0x309) |
921 | 2662a059 | j_mayer | #define SPR_PERFA (0x30A) |
922 | 2662a059 | j_mayer | #define SPR_PERFB (0x30B) |
923 | 2662a059 | j_mayer | #define SPR_PERFC (0x30C) |
924 | 2662a059 | j_mayer | #define SPR_PERFD (0x30D) |
925 | 2662a059 | j_mayer | #define SPR_PERFE (0x30E) |
926 | 2662a059 | j_mayer | #define SPR_PERFF (0x30F) |
927 | 2662a059 | j_mayer | #define SPR_UPERF0 (0x310) |
928 | 2662a059 | j_mayer | #define SPR_UPERF1 (0x311) |
929 | 2662a059 | j_mayer | #define SPR_UPERF2 (0x312) |
930 | 2662a059 | j_mayer | #define SPR_UPERF3 (0x313) |
931 | 2662a059 | j_mayer | #define SPR_UPERF4 (0x314) |
932 | 2662a059 | j_mayer | #define SPR_UPERF5 (0x315) |
933 | 2662a059 | j_mayer | #define SPR_UPERF6 (0x316) |
934 | 2662a059 | j_mayer | #define SPR_UPERF7 (0x317) |
935 | 2662a059 | j_mayer | #define SPR_UPERF8 (0x318) |
936 | 2662a059 | j_mayer | #define SPR_UPERF9 (0x319) |
937 | 2662a059 | j_mayer | #define SPR_UPERFA (0x31A) |
938 | 2662a059 | j_mayer | #define SPR_UPERFB (0x31B) |
939 | 2662a059 | j_mayer | #define SPR_UPERFC (0x31C) |
940 | 2662a059 | j_mayer | #define SPR_UPERFD (0x31D) |
941 | 2662a059 | j_mayer | #define SPR_UPERFE (0x31E) |
942 | 2662a059 | j_mayer | #define SPR_UPERFF (0x31F) |
943 | 76a66253 | j_mayer | #define SPR_440_INV0 (0x370) |
944 | 76a66253 | j_mayer | #define SPR_440_INV1 (0x371) |
945 | 76a66253 | j_mayer | #define SPR_440_INV2 (0x372) |
946 | 76a66253 | j_mayer | #define SPR_440_INV3 (0x373) |
947 | 2662a059 | j_mayer | #define SPR_440_ITV0 (0x374) |
948 | 2662a059 | j_mayer | #define SPR_440_ITV1 (0x375) |
949 | 2662a059 | j_mayer | #define SPR_440_ITV2 (0x376) |
950 | 2662a059 | j_mayer | #define SPR_440_ITV3 (0x377) |
951 | a750fc0b | j_mayer | #define SPR_440_CCR1 (0x378) |
952 | a750fc0b | j_mayer | #define SPR_DCRIPR (0x37B) |
953 | 2662a059 | j_mayer | #define SPR_PPR (0x380) |
954 | 76a66253 | j_mayer | #define SPR_440_DNV0 (0x390) |
955 | 76a66253 | j_mayer | #define SPR_440_DNV1 (0x391) |
956 | 76a66253 | j_mayer | #define SPR_440_DNV2 (0x392) |
957 | 76a66253 | j_mayer | #define SPR_440_DNV3 (0x393) |
958 | 2662a059 | j_mayer | #define SPR_440_DTV0 (0x394) |
959 | 2662a059 | j_mayer | #define SPR_440_DTV1 (0x395) |
960 | 2662a059 | j_mayer | #define SPR_440_DTV2 (0x396) |
961 | 2662a059 | j_mayer | #define SPR_440_DTV3 (0x397) |
962 | 76a66253 | j_mayer | #define SPR_440_DVLIM (0x398) |
963 | 76a66253 | j_mayer | #define SPR_440_IVLIM (0x399) |
964 | 76a66253 | j_mayer | #define SPR_440_RSTCFG (0x39B) |
965 | 2662a059 | j_mayer | #define SPR_BOOKE_DCDBTRL (0x39C) |
966 | 2662a059 | j_mayer | #define SPR_BOOKE_DCDBTRH (0x39D) |
967 | 2662a059 | j_mayer | #define SPR_BOOKE_ICDBTRL (0x39E) |
968 | 2662a059 | j_mayer | #define SPR_BOOKE_ICDBTRH (0x39F) |
969 | a750fc0b | j_mayer | #define SPR_UMMCR2 (0x3A0) |
970 | a750fc0b | j_mayer | #define SPR_UPMC5 (0x3A1) |
971 | a750fc0b | j_mayer | #define SPR_UPMC6 (0x3A2) |
972 | a750fc0b | j_mayer | #define SPR_UBAMR (0x3A7) |
973 | 76a66253 | j_mayer | #define SPR_UMMCR0 (0x3A8) |
974 | 76a66253 | j_mayer | #define SPR_UPMC1 (0x3A9) |
975 | 76a66253 | j_mayer | #define SPR_UPMC2 (0x3AA) |
976 | a750fc0b | j_mayer | #define SPR_USIAR (0x3AB) |
977 | 76a66253 | j_mayer | #define SPR_UMMCR1 (0x3AC) |
978 | 76a66253 | j_mayer | #define SPR_UPMC3 (0x3AD) |
979 | 76a66253 | j_mayer | #define SPR_UPMC4 (0x3AE) |
980 | 76a66253 | j_mayer | #define SPR_USDA (0x3AF) |
981 | 76a66253 | j_mayer | #define SPR_40x_ZPR (0x3B0) |
982 | 363be49c | j_mayer | #define SPR_BOOKE_MAS7 (0x3B0) |
983 | a750fc0b | j_mayer | #define SPR_620_PMR0 (0x3B0) |
984 | a750fc0b | j_mayer | #define SPR_MMCR2 (0x3B0) |
985 | a750fc0b | j_mayer | #define SPR_PMC5 (0x3B1) |
986 | 76a66253 | j_mayer | #define SPR_40x_PID (0x3B1) |
987 | a750fc0b | j_mayer | #define SPR_620_PMR1 (0x3B1) |
988 | a750fc0b | j_mayer | #define SPR_PMC6 (0x3B2) |
989 | 76a66253 | j_mayer | #define SPR_440_MMUCR (0x3B2) |
990 | a750fc0b | j_mayer | #define SPR_620_PMR2 (0x3B2) |
991 | 76a66253 | j_mayer | #define SPR_4xx_CCR0 (0x3B3) |
992 | 363be49c | j_mayer | #define SPR_BOOKE_EPLC (0x3B3) |
993 | a750fc0b | j_mayer | #define SPR_620_PMR3 (0x3B3) |
994 | 76a66253 | j_mayer | #define SPR_405_IAC3 (0x3B4) |
995 | 363be49c | j_mayer | #define SPR_BOOKE_EPSC (0x3B4) |
996 | a750fc0b | j_mayer | #define SPR_620_PMR4 (0x3B4) |
997 | 76a66253 | j_mayer | #define SPR_405_IAC4 (0x3B5) |
998 | a750fc0b | j_mayer | #define SPR_620_PMR5 (0x3B5) |
999 | 76a66253 | j_mayer | #define SPR_405_DVC1 (0x3B6) |
1000 | a750fc0b | j_mayer | #define SPR_620_PMR6 (0x3B6) |
1001 | 76a66253 | j_mayer | #define SPR_405_DVC2 (0x3B7) |
1002 | a750fc0b | j_mayer | #define SPR_620_PMR7 (0x3B7) |
1003 | a750fc0b | j_mayer | #define SPR_BAMR (0x3B7) |
1004 | 76a66253 | j_mayer | #define SPR_MMCR0 (0x3B8) |
1005 | a750fc0b | j_mayer | #define SPR_620_PMR8 (0x3B8) |
1006 | 76a66253 | j_mayer | #define SPR_PMC1 (0x3B9) |
1007 | 76a66253 | j_mayer | #define SPR_40x_SGR (0x3B9) |
1008 | a750fc0b | j_mayer | #define SPR_620_PMR9 (0x3B9) |
1009 | 76a66253 | j_mayer | #define SPR_PMC2 (0x3BA) |
1010 | 76a66253 | j_mayer | #define SPR_40x_DCWR (0x3BA) |
1011 | a750fc0b | j_mayer | #define SPR_620_PMRA (0x3BA) |
1012 | a750fc0b | j_mayer | #define SPR_SIAR (0x3BB) |
1013 | 76a66253 | j_mayer | #define SPR_405_SLER (0x3BB) |
1014 | a750fc0b | j_mayer | #define SPR_620_PMRB (0x3BB) |
1015 | 76a66253 | j_mayer | #define SPR_MMCR1 (0x3BC) |
1016 | 76a66253 | j_mayer | #define SPR_405_SU0R (0x3BC) |
1017 | a750fc0b | j_mayer | #define SPR_620_PMRC (0x3BC) |
1018 | a750fc0b | j_mayer | #define SPR_401_SKR (0x3BC) |
1019 | 76a66253 | j_mayer | #define SPR_PMC3 (0x3BD) |
1020 | 76a66253 | j_mayer | #define SPR_405_DBCR1 (0x3BD) |
1021 | a750fc0b | j_mayer | #define SPR_620_PMRD (0x3BD) |
1022 | 76a66253 | j_mayer | #define SPR_PMC4 (0x3BE) |
1023 | a750fc0b | j_mayer | #define SPR_620_PMRE (0x3BE) |
1024 | 76a66253 | j_mayer | #define SPR_SDA (0x3BF) |
1025 | a750fc0b | j_mayer | #define SPR_620_PMRF (0x3BF) |
1026 | 76a66253 | j_mayer | #define SPR_403_VTBL (0x3CC) |
1027 | 76a66253 | j_mayer | #define SPR_403_VTBU (0x3CD) |
1028 | 76a66253 | j_mayer | #define SPR_DMISS (0x3D0) |
1029 | 76a66253 | j_mayer | #define SPR_DCMP (0x3D1) |
1030 | 76a66253 | j_mayer | #define SPR_HASH1 (0x3D2) |
1031 | 76a66253 | j_mayer | #define SPR_HASH2 (0x3D3) |
1032 | 2662a059 | j_mayer | #define SPR_BOOKE_ICDBDR (0x3D3) |
1033 | a750fc0b | j_mayer | #define SPR_TLBMISS (0x3D4) |
1034 | 76a66253 | j_mayer | #define SPR_IMISS (0x3D4) |
1035 | 76a66253 | j_mayer | #define SPR_40x_ESR (0x3D4) |
1036 | a750fc0b | j_mayer | #define SPR_PTEHI (0x3D5) |
1037 | 76a66253 | j_mayer | #define SPR_ICMP (0x3D5) |
1038 | 76a66253 | j_mayer | #define SPR_40x_DEAR (0x3D5) |
1039 | a750fc0b | j_mayer | #define SPR_PTELO (0x3D6) |
1040 | 76a66253 | j_mayer | #define SPR_RPA (0x3D6) |
1041 | 76a66253 | j_mayer | #define SPR_40x_EVPR (0x3D6) |
1042 | a750fc0b | j_mayer | #define SPR_L3PM (0x3D7) |
1043 | 76a66253 | j_mayer | #define SPR_403_CDBCR (0x3D7) |
1044 | a750fc0b | j_mayer | #define SPR_L3OHCR (0x3D8) |
1045 | 76a66253 | j_mayer | #define SPR_TCR (0x3D8) |
1046 | 76a66253 | j_mayer | #define SPR_40x_TSR (0x3D8) |
1047 | 76a66253 | j_mayer | #define SPR_IBR (0x3DA) |
1048 | 76a66253 | j_mayer | #define SPR_40x_TCR (0x3DA) |
1049 | a750fc0b | j_mayer | #define SPR_ESASRR (0x3DB) |
1050 | 76a66253 | j_mayer | #define SPR_40x_PIT (0x3DB) |
1051 | 76a66253 | j_mayer | #define SPR_403_TBL (0x3DC) |
1052 | 76a66253 | j_mayer | #define SPR_403_TBU (0x3DD) |
1053 | 76a66253 | j_mayer | #define SPR_SEBR (0x3DE) |
1054 | 76a66253 | j_mayer | #define SPR_40x_SRR2 (0x3DE) |
1055 | 76a66253 | j_mayer | #define SPR_SER (0x3DF) |
1056 | 76a66253 | j_mayer | #define SPR_40x_SRR3 (0x3DF) |
1057 | a750fc0b | j_mayer | #define SPR_L3ITCR0 (0x3E8) |
1058 | a750fc0b | j_mayer | #define SPR_L3ITCR1 (0x3E9) |
1059 | a750fc0b | j_mayer | #define SPR_L3ITCR2 (0x3EA) |
1060 | a750fc0b | j_mayer | #define SPR_L3ITCR3 (0x3EB) |
1061 | 76a66253 | j_mayer | #define SPR_HID0 (0x3F0) |
1062 | 76a66253 | j_mayer | #define SPR_40x_DBSR (0x3F0) |
1063 | 76a66253 | j_mayer | #define SPR_HID1 (0x3F1) |
1064 | 76a66253 | j_mayer | #define SPR_IABR (0x3F2) |
1065 | 76a66253 | j_mayer | #define SPR_40x_DBCR0 (0x3F2) |
1066 | 76a66253 | j_mayer | #define SPR_601_HID2 (0x3F2) |
1067 | 76a66253 | j_mayer | #define SPR_E500_L1CSR0 (0x3F2) |
1068 | a750fc0b | j_mayer | #define SPR_ICTRL (0x3F3) |
1069 | 76a66253 | j_mayer | #define SPR_HID2 (0x3F3) |
1070 | 76a66253 | j_mayer | #define SPR_E500_L1CSR1 (0x3F3) |
1071 | 76a66253 | j_mayer | #define SPR_440_DBDR (0x3F3) |
1072 | a750fc0b | j_mayer | #define SPR_LDSTDB (0x3F4) |
1073 | 76a66253 | j_mayer | #define SPR_40x_IAC1 (0x3F4) |
1074 | 65f9ee8d | j_mayer | #define SPR_MMUCSR0 (0x3F4) |
1075 | 76a66253 | j_mayer | #define SPR_DABR (0x3F5) |
1076 | 3fc6c082 | bellard | #define DABR_MASK (~(target_ulong)0x7) |
1077 | 76a66253 | j_mayer | #define SPR_E500_BUCSR (0x3F5) |
1078 | 76a66253 | j_mayer | #define SPR_40x_IAC2 (0x3F5) |
1079 | 76a66253 | j_mayer | #define SPR_601_HID5 (0x3F5) |
1080 | 76a66253 | j_mayer | #define SPR_40x_DAC1 (0x3F6) |
1081 | a750fc0b | j_mayer | #define SPR_MSSCR0 (0x3F6) |
1082 | d63001d1 | j_mayer | #define SPR_970_HID5 (0x3F6) |
1083 | a750fc0b | j_mayer | #define SPR_MSSSR0 (0x3F7) |
1084 | 2662a059 | j_mayer | #define SPR_DABRX (0x3F7) |
1085 | 76a66253 | j_mayer | #define SPR_40x_DAC2 (0x3F7) |
1086 | 65f9ee8d | j_mayer | #define SPR_MMUCFG (0x3F7) |
1087 | a750fc0b | j_mayer | #define SPR_LDSTCR (0x3F8) |
1088 | a750fc0b | j_mayer | #define SPR_L2PMCR (0x3F8) |
1089 | 76a66253 | j_mayer | #define SPR_750_HID2 (0x3F8) |
1090 | a750fc0b | j_mayer | #define SPR_620_HID8 (0x3F8) |
1091 | 76a66253 | j_mayer | #define SPR_L2CR (0x3F9) |
1092 | a750fc0b | j_mayer | #define SPR_620_HID9 (0x3F9) |
1093 | a750fc0b | j_mayer | #define SPR_L3CR (0x3FA) |
1094 | 76a66253 | j_mayer | #define SPR_IABR2 (0x3FA) |
1095 | 76a66253 | j_mayer | #define SPR_40x_DCCR (0x3FA) |
1096 | 76a66253 | j_mayer | #define SPR_ICTC (0x3FB) |
1097 | 76a66253 | j_mayer | #define SPR_40x_ICCR (0x3FB) |
1098 | 76a66253 | j_mayer | #define SPR_THRM1 (0x3FC) |
1099 | 76a66253 | j_mayer | #define SPR_403_PBL1 (0x3FC) |
1100 | 76a66253 | j_mayer | #define SPR_SP (0x3FD) |
1101 | 76a66253 | j_mayer | #define SPR_THRM2 (0x3FD) |
1102 | 76a66253 | j_mayer | #define SPR_403_PBU1 (0x3FD) |
1103 | a750fc0b | j_mayer | #define SPR_604_HID13 (0x3FD) |
1104 | 76a66253 | j_mayer | #define SPR_LT (0x3FE) |
1105 | 76a66253 | j_mayer | #define SPR_THRM3 (0x3FE) |
1106 | 76a66253 | j_mayer | #define SPR_FPECR (0x3FE) |
1107 | 76a66253 | j_mayer | #define SPR_403_PBL2 (0x3FE) |
1108 | 76a66253 | j_mayer | #define SPR_PIR (0x3FF) |
1109 | 76a66253 | j_mayer | #define SPR_403_PBU2 (0x3FF) |
1110 | 76a66253 | j_mayer | #define SPR_601_HID15 (0x3FF) |
1111 | a750fc0b | j_mayer | #define SPR_604_HID15 (0x3FF) |
1112 | 76a66253 | j_mayer | #define SPR_E500_SVR (0x3FF) |
1113 | 79aceca5 | bellard | |
1114 | 76a66253 | j_mayer | /*****************************************************************************/
|
1115 | 9a64fbe4 | bellard | /* Memory access type :
|
1116 | 9a64fbe4 | bellard | * may be needed for precise access rights control and precise exceptions.
|
1117 | 9a64fbe4 | bellard | */
|
1118 | 79aceca5 | bellard | enum {
|
1119 | 9a64fbe4 | bellard | /* 1 bit to define user level / supervisor access */
|
1120 | 9a64fbe4 | bellard | ACCESS_USER = 0x00,
|
1121 | 9a64fbe4 | bellard | ACCESS_SUPER = 0x01,
|
1122 | 9a64fbe4 | bellard | /* Type of instruction that generated the access */
|
1123 | 9a64fbe4 | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
1124 | 9a64fbe4 | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
1125 | 9a64fbe4 | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
1126 | 9a64fbe4 | bellard | ACCESS_RES = 0x40, /* load/store with reservation */ |
1127 | 9a64fbe4 | bellard | ACCESS_EXT = 0x50, /* external access */ |
1128 | 9a64fbe4 | bellard | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
1129 | 9a64fbe4 | bellard | }; |
1130 | 9a64fbe4 | bellard | |
1131 | 47103572 | j_mayer | /* Hardware interruption sources:
|
1132 | 47103572 | j_mayer | * all those exception can be raised simulteaneously
|
1133 | 47103572 | j_mayer | */
|
1134 | e9df014c | j_mayer | /* Input pins definitions */
|
1135 | e9df014c | j_mayer | enum {
|
1136 | e9df014c | j_mayer | /* 6xx bus input pins */
|
1137 | 24be5ae3 | j_mayer | PPC6xx_INPUT_HRESET = 0,
|
1138 | 24be5ae3 | j_mayer | PPC6xx_INPUT_SRESET = 1,
|
1139 | 24be5ae3 | j_mayer | PPC6xx_INPUT_CKSTP_IN = 2,
|
1140 | 24be5ae3 | j_mayer | PPC6xx_INPUT_MCP = 3,
|
1141 | 24be5ae3 | j_mayer | PPC6xx_INPUT_SMI = 4,
|
1142 | 24be5ae3 | j_mayer | PPC6xx_INPUT_INT = 5,
|
1143 | 24be5ae3 | j_mayer | }; |
1144 | 24be5ae3 | j_mayer | |
1145 | 24be5ae3 | j_mayer | enum {
|
1146 | e9df014c | j_mayer | /* Embedded PowerPC input pins */
|
1147 | 24be5ae3 | j_mayer | PPCBookE_INPUT_HRESET = 0,
|
1148 | 24be5ae3 | j_mayer | PPCBookE_INPUT_SRESET = 1,
|
1149 | 24be5ae3 | j_mayer | PPCBookE_INPUT_CKSTP_IN = 2,
|
1150 | 24be5ae3 | j_mayer | PPCBookE_INPUT_MCP = 3,
|
1151 | 24be5ae3 | j_mayer | PPCBookE_INPUT_SMI = 4,
|
1152 | 24be5ae3 | j_mayer | PPCBookE_INPUT_INT = 5,
|
1153 | 24be5ae3 | j_mayer | PPCBookE_INPUT_CINT = 6,
|
1154 | 24be5ae3 | j_mayer | }; |
1155 | 24be5ae3 | j_mayer | |
1156 | 24be5ae3 | j_mayer | enum {
|
1157 | 4e290a0b | j_mayer | /* PowerPC 40x input pins */
|
1158 | 4e290a0b | j_mayer | PPC40x_INPUT_RESET_CORE = 0,
|
1159 | 4e290a0b | j_mayer | PPC40x_INPUT_RESET_CHIP = 1,
|
1160 | 4e290a0b | j_mayer | PPC40x_INPUT_RESET_SYS = 2,
|
1161 | 4e290a0b | j_mayer | PPC40x_INPUT_CINT = 3,
|
1162 | 4e290a0b | j_mayer | PPC40x_INPUT_INT = 4,
|
1163 | 4e290a0b | j_mayer | PPC40x_INPUT_HALT = 5,
|
1164 | 4e290a0b | j_mayer | PPC40x_INPUT_DEBUG = 6,
|
1165 | 4e290a0b | j_mayer | PPC40x_INPUT_NB, |
1166 | e9df014c | j_mayer | }; |
1167 | e9df014c | j_mayer | |
1168 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1169 | d0dfae6e | j_mayer | enum {
|
1170 | a750fc0b | j_mayer | /* PowerPC 620 (and probably others) input pins */
|
1171 | a750fc0b | j_mayer | PPC620_INPUT_HRESET = 0,
|
1172 | a750fc0b | j_mayer | PPC620_INPUT_SRESET = 1,
|
1173 | a750fc0b | j_mayer | PPC620_INPUT_CKSTP = 2,
|
1174 | a750fc0b | j_mayer | PPC620_INPUT_TBEN = 3,
|
1175 | a750fc0b | j_mayer | PPC620_INPUT_WAKEUP = 4,
|
1176 | a750fc0b | j_mayer | PPC620_INPUT_MCP = 5,
|
1177 | a750fc0b | j_mayer | PPC620_INPUT_SMI = 6,
|
1178 | a750fc0b | j_mayer | PPC620_INPUT_INT = 7,
|
1179 | a750fc0b | j_mayer | }; |
1180 | a750fc0b | j_mayer | |
1181 | a750fc0b | j_mayer | enum {
|
1182 | d0dfae6e | j_mayer | /* PowerPC 970 input pins */
|
1183 | d0dfae6e | j_mayer | PPC970_INPUT_HRESET = 0,
|
1184 | d0dfae6e | j_mayer | PPC970_INPUT_SRESET = 1,
|
1185 | d0dfae6e | j_mayer | PPC970_INPUT_CKSTP = 2,
|
1186 | d0dfae6e | j_mayer | PPC970_INPUT_TBEN = 3,
|
1187 | d0dfae6e | j_mayer | PPC970_INPUT_MCP = 4,
|
1188 | d0dfae6e | j_mayer | PPC970_INPUT_INT = 5,
|
1189 | d0dfae6e | j_mayer | PPC970_INPUT_THINT = 6,
|
1190 | d0dfae6e | j_mayer | }; |
1191 | 00af685f | j_mayer | #endif
|
1192 | d0dfae6e | j_mayer | |
1193 | e9df014c | j_mayer | /* Hardware exceptions definitions */
|
1194 | 47103572 | j_mayer | enum {
|
1195 | e9df014c | j_mayer | /* External hardware exception sources */
|
1196 | e1833e1f | j_mayer | PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
1197 | e1833e1f | j_mayer | PPC_INTERRUPT_MCK = 1, /* Machine check exception */ |
1198 | e1833e1f | j_mayer | PPC_INTERRUPT_EXT = 2, /* External interrupt */ |
1199 | e1833e1f | j_mayer | PPC_INTERRUPT_SMI = 3, /* System management interrupt */ |
1200 | e1833e1f | j_mayer | PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */ |
1201 | e1833e1f | j_mayer | PPC_INTERRUPT_DEBUG = 5, /* External debug exception */ |
1202 | e1833e1f | j_mayer | PPC_INTERRUPT_THERM = 6, /* Thermal exception */ |
1203 | e9df014c | j_mayer | /* Internal hardware exception sources */
|
1204 | e1833e1f | j_mayer | PPC_INTERRUPT_DECR = 7, /* Decrementer exception */ |
1205 | e1833e1f | j_mayer | PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */ |
1206 | e1833e1f | j_mayer | PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */ |
1207 | e1833e1f | j_mayer | PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */ |
1208 | e1833e1f | j_mayer | PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */ |
1209 | e1833e1f | j_mayer | PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt */ |
1210 | e1833e1f | j_mayer | PPC_INTERRUPT_DOORBELL = 13, /* Doorbell interrupt */ |
1211 | e1833e1f | j_mayer | PPC_INTERRUPT_PERFM = 14, /* Performance monitor interrupt */ |
1212 | 47103572 | j_mayer | }; |
1213 | 47103572 | j_mayer | |
1214 | 9a64fbe4 | bellard | /*****************************************************************************/
|
1215 | 9a64fbe4 | bellard | |
1216 | 79aceca5 | bellard | #endif /* !defined (__CPU_PPC_H__) */ |