Revision b3c7724c

b/exec.c
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#include "exec-all.h"
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#include "qemu-common.h"
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#include "tcg.h"
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#include "hw/hw.h"
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#if defined(CONFIG_USER_ONLY)
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#include <qemu.h>
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#endif
......
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    env->cpu_index = cpu_index;
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    env->nb_watchpoints = 0;
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    *penv = env;
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#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
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    register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
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                    cpu_save, cpu_load, env);
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#endif
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}
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static inline void invalidate_page_bitmap(PageDesc *p)
b/hw/etraxfs.c
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        cpu_model = "crisv32";
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    }
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    env = cpu_init(cpu_model);
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    register_savevm("cpu", 0, 1, cpu_save, cpu_load, env);
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    qemu_register_reset(main_cpu_reset, env);
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    /* allocate RAM */
b/hw/mips_jazz.c
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        fprintf(stderr, "Unable to find CPU definition\n");
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        exit(1);
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    }
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    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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    qemu_register_reset(main_cpu_reset, env);
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    /* allocate RAM */
b/hw/mips_malta.c
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        fprintf(stderr, "Unable to find CPU definition\n");
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        exit(1);
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    }
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    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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    qemu_register_reset(main_cpu_reset, env);
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    /* allocate RAM */
b/hw/mips_mipssim.c
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        fprintf(stderr, "Unable to find CPU definition\n");
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        exit(1);
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    }
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    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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    qemu_register_reset(main_cpu_reset, env);
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    /* Allocate RAM. */
b/hw/mips_r4k.c
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        fprintf(stderr, "Unable to find CPU definition\n");
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        exit(1);
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    }
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    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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    qemu_register_reset(main_cpu_reset, env);
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    /* allocate RAM */
b/hw/pc.c
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            /* XXX: enable it in all cases */
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            env->cpuid_features |= CPUID_APIC;
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        }
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        register_savevm("cpu", i, 5, cpu_save, cpu_load, env);
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        qemu_register_reset(main_cpu_reset, env);
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        if (pci_enabled) {
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            apic_init(env);
b/hw/ppc4xx_devs.c
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    ppc_dcr_init(env, NULL, NULL);
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    /* Register qemu callbacks */
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    qemu_register_reset(&cpu_ppc_reset, env);
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    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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    return env;
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}
b/hw/ppc_chrp.c
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        env->osi_call = vga_osi_call;
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#endif
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        qemu_register_reset(&cpu_ppc_reset, env);
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        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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        envs[i] = env;
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    }
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    if (env->nip < 0xFFF80000) {
b/hw/ppc_oldworld.c
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        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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        env->osi_call = vga_osi_call;
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        qemu_register_reset(&cpu_ppc_reset, env);
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        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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        envs[i] = env;
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    }
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    if (env->nip < 0xFFF80000) {
b/hw/ppc_prep.c
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            cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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        }
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        qemu_register_reset(&cpu_ppc_reset, env);
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        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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        envs[i] = env;
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    }
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b/hw/pxa2xx.c
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        fprintf(stderr, "Unable to find CPU definition\n");
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        exit(1);
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    }
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    register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
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                    s->env);
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    s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
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    /* SDRAM & Internal Memory Storage */
......
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        fprintf(stderr, "Unable to find CPU definition\n");
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        exit(1);
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    }
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    register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
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                    s->env);
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    s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
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    /* SDRAM & Internal Memory Storage */
b/hw/sun4m.c
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            qemu_register_reset(secondary_cpu_reset, env);
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            env->halted = 1;
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        }
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        register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
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        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
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        env->prom_addr = hwdef->slavio_base;
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    }
......
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    cpu_sparc_set_id(env, 0);
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    qemu_register_reset(main_cpu_reset, env);
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    register_savevm("cpu", 0, 4, cpu_save, cpu_load, env);
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    cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
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    env->prom_addr = hwdef->slavio_base;
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......
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            qemu_register_reset(secondary_cpu_reset, env);
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            env->halted = 1;
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        }
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        register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
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        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
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        env->prom_addr = hwdef->slavio_base;
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    }
b/hw/sun4u.c
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    bh = qemu_bh_new(hstick_irq, env);
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    env->hstick = ptimer_init(bh);
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    ptimer_set_period(env->hstick, 1ULL);
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    register_savevm("cpu", 0, 4, cpu_save, cpu_load, env);
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    qemu_register_reset(main_cpu_reset, env);
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    main_cpu_reset(env);
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b/qemu-common.h
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typedef struct IRQState *qemu_irq;
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struct pcmcia_card_s;
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/* CPU save/load.  */
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void cpu_save(QEMUFile *f, void *opaque);
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int cpu_load(QEMUFile *f, void *opaque, int version_id);
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#endif
b/sysemu.h
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#endif
42 42
void qemu_system_reset(void);
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void cpu_save(QEMUFile *f, void *opaque);
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int cpu_load(QEMUFile *f, void *opaque, int version_id);
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void do_savevm(const char *name);
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void do_loadvm(const char *name);
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void do_delvm(const char *name);
b/target-arm/cpu.h
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#define cpu_signal_handler cpu_arm_signal_handler
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#define cpu_list arm_cpu_list
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#define ARM_CPU_SAVE_VERSION 1
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#define CPU_SAVE_VERSION 1
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
b/target-arm/machine.c
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    CPUARMState *env = (CPUARMState *)opaque;
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    int i;
122 122

  
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    if (version_id != ARM_CPU_SAVE_VERSION)
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    if (version_id != CPU_SAVE_VERSION)
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        return -EINVAL;
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126 126
    for (i = 0; i < 16; i++) {
b/target-cris/cpu.h
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#define cpu_gen_code cpu_cris_gen_code
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#define cpu_signal_handler cpu_cris_signal_handler
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213
#define CPU_SAVE_VERSION 1
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
b/target-i386/cpu.h
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#define cpu_signal_handler cpu_x86_signal_handler
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#define cpu_list x86_cpu_list
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#define CPU_SAVE_VERSION 5
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
b/target-mips/cpu.h
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#define cpu_signal_handler cpu_mips_signal_handler
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#define cpu_list mips_cpu_list
491 491

  
492
#define CPU_SAVE_VERSION 3
493

  
492 494
/* MMU modes definitions. We carefully match the indices with our
493 495
   hflags layout. */
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#define MMU_MODE0_SUFFIX _kernel
b/target-ppc/cpu.h
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#define cpu_signal_handler cpu_ppc_signal_handler
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#define cpu_list ppc_cpu_list
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816
#define CPU_SAVE_VERSION 3
817

  
816 818
/* MMU modes definitions */
817 819
#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel
b/target-sparc/cpu.h
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#define cpu_signal_handler cpu_sparc_signal_handler
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#define cpu_list sparc_cpu_list
390 390

  
391
#define CPU_SAVE_VERSION 4
392

  
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _user
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#define MMU_MODE1_SUFFIX _kernel

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