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1
/*
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 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3
 *
4
 * Copyright (c) 2003-2005 Fabrice Bellard
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "qemu-timer.h"
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#include "sun4m.h"
27
#include "nvram.h"
28
#include "sparc32_dma.h"
29
#include "fdc.h"
30
#include "sysemu.h"
31
#include "net.h"
32
#include "boards.h"
33
#include "firmware_abi.h"
34
#include "scsi.h"
35
#include "pc.h"
36
#include "isa.h"
37

    
38
//#define DEBUG_IRQ
39

    
40
/*
41
 * Sun4m architecture was used in the following machines:
42
 *
43
 * SPARCserver 6xxMP/xx
44
 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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 * SPARCclassic X (4/10)
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 * SPARCstation LX/ZX (4/30)
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 * SPARCstation Voyager
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 * SPARCstation 10/xx, SPARCserver 10/xx
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 * SPARCstation 5, SPARCserver 5
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 * SPARCstation 20/xx, SPARCserver 20
51
 * SPARCstation 4
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 *
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 * Sun4d architecture was used in the following machines:
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 *
55
 * SPARCcenter 2000
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 * SPARCserver 1000
57
 *
58
 * Sun4c architecture was used in the following machines:
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 * SPARCstation 1/1+, SPARCserver 1/1+
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 * SPARCstation SLC
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 * SPARCstation IPC
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 * SPARCstation ELC
63
 * SPARCstation IPX
64
 *
65
 * See for example: http://www.sunhelp.org/faq/sunref1.html
66
 */
67

    
68
#ifdef DEBUG_IRQ
69
#define DPRINTF(fmt, args...)                           \
70
    do { printf("CPUIRQ: " fmt , ##args); } while (0)
71
#else
72
#define DPRINTF(fmt, args...)
73
#endif
74

    
75
#define KERNEL_LOAD_ADDR     0x00004000
76
#define CMDLINE_ADDR         0x007ff000
77
#define INITRD_LOAD_ADDR     0x00800000
78
#define PROM_SIZE_MAX        (512 * 1024)
79
#define PROM_VADDR           0xffd00000
80
#define PROM_FILENAME        "openbios-sparc32"
81

    
82
// Control plane, 8-bit and 24-bit planes
83
#define TCX_SIZE             (9 * 1024 * 1024)
84

    
85
#define MAX_CPUS 16
86
#define MAX_PILS 16
87

    
88
struct hwdef {
89
    target_phys_addr_t iommu_base, slavio_base;
90
    target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
91
    target_phys_addr_t serial_base, fd_base;
92
    target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
93
    target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
94
    target_phys_addr_t ecc_base;
95
    uint32_t ecc_version;
96
    target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
97
    long vram_size, nvram_size;
98
    // IRQ numbers are not PIL ones, but master interrupt controller
99
    // register bit numbers
100
    int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
101
    int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
102
    int machine_id; // For NVRAM
103
    uint32_t iommu_version;
104
    uint32_t intbit_to_level[32];
105
    uint64_t max_mem;
106
    const char * const default_cpu_model;
107
};
108

    
109
#define MAX_IOUNITS 5
110

    
111
struct sun4d_hwdef {
112
    target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
113
    target_phys_addr_t counter_base, nvram_base, ms_kb_base;
114
    target_phys_addr_t serial_base;
115
    target_phys_addr_t espdma_base, esp_base;
116
    target_phys_addr_t ledma_base, le_base;
117
    target_phys_addr_t tcx_base;
118
    target_phys_addr_t sbi_base;
119
    unsigned long vram_size, nvram_size;
120
    // IRQ numbers are not PIL ones, but SBI register bit numbers
121
    int esp_irq, le_irq, clock_irq, clock1_irq;
122
    int ser_irq, ms_kb_irq, me_irq;
123
    int machine_id; // For NVRAM
124
    uint32_t iounit_version;
125
    uint64_t max_mem;
126
    const char * const default_cpu_model;
127
};
128

    
129
int DMA_get_channel_mode (int nchan)
130
{
131
    return 0;
132
}
133
int DMA_read_memory (int nchan, void *buf, int pos, int size)
134
{
135
    return 0;
136
}
137
int DMA_write_memory (int nchan, void *buf, int pos, int size)
138
{
139
    return 0;
140
}
141
void DMA_hold_DREQ (int nchan) {}
142
void DMA_release_DREQ (int nchan) {}
143
void DMA_schedule(int nchan) {}
144
void DMA_run (void) {}
145
void DMA_init (int high_page_enable) {}
146
void DMA_register_channel (int nchan,
147
                           DMA_transfer_handler transfer_handler,
148
                           void *opaque)
149
{
150
}
151

    
152
static int nvram_boot_set(void *opaque, const char *boot_device)
153
{
154
    unsigned int i;
155
    uint8_t image[sizeof(ohwcfg_v3_t)];
156
    ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
157
    m48t59_t *nvram = (m48t59_t *)opaque;
158

    
159
    for (i = 0; i < sizeof(image); i++)
160
        image[i] = m48t59_read(nvram, i) & 0xff;
161

    
162
    strcpy((char *)header->boot_devices, boot_device);
163
    header->nboot_devices = strlen(boot_device) & 0xff;
164
    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
165

    
166
    for (i = 0; i < sizeof(image); i++)
167
        m48t59_write(nvram, i, image[i]);
168

    
169
    return 0;
170
}
171

    
172
extern int nographic;
173

    
174
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
175
                       const char *boot_devices, ram_addr_t RAM_size,
176
                       uint32_t kernel_size,
177
                       int width, int height, int depth,
178
                       int machine_id, const char *arch)
179
{
180
    unsigned int i;
181
    uint32_t start, end;
182
    uint8_t image[0x1ff0];
183
    ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
184
    struct sparc_arch_cfg *sparc_header;
185
    struct OpenBIOS_nvpart_v1 *part_header;
186

    
187
    memset(image, '\0', sizeof(image));
188

    
189
    // Try to match PPC NVRAM
190
    strcpy((char *)header->struct_ident, "QEMU_BIOS");
191
    header->struct_version = cpu_to_be32(3); /* structure v3 */
192

    
193
    header->nvram_size = cpu_to_be16(0x2000);
194
    header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
195
    header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
196
    strcpy((char *)header->arch, arch);
197
    header->nb_cpus = smp_cpus & 0xff;
198
    header->RAM0_base = 0;
199
    header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
200
    strcpy((char *)header->boot_devices, boot_devices);
201
    header->nboot_devices = strlen(boot_devices) & 0xff;
202
    header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
203
    header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
204
    if (cmdline) {
205
        pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
206
        header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
207
        header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
208
    }
209
    // XXX add initrd_image, initrd_size
210
    header->width = cpu_to_be16(width);
211
    header->height = cpu_to_be16(height);
212
    header->depth = cpu_to_be16(depth);
213
    if (nographic)
214
        header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
215

    
216
    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
217

    
218
    // Architecture specific header
219
    start = sizeof(ohwcfg_v3_t);
220
    sparc_header = (struct sparc_arch_cfg *)&image[start];
221
    sparc_header->valid = 0;
222
    start += sizeof(struct sparc_arch_cfg);
223

    
224
    // OpenBIOS nvram variables
225
    // Variable partition
226
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
227
    part_header->signature = OPENBIOS_PART_SYSTEM;
228
    strcpy(part_header->name, "system");
229

    
230
    end = start + sizeof(struct OpenBIOS_nvpart_v1);
231
    for (i = 0; i < nb_prom_envs; i++)
232
        end = OpenBIOS_set_var(image, end, prom_envs[i]);
233

    
234
    // End marker
235
    image[end++] = '\0';
236

    
237
    end = start + ((end - start + 15) & ~15);
238
    OpenBIOS_finish_partition(part_header, end - start);
239

    
240
    // free partition
241
    start = end;
242
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
243
    part_header->signature = OPENBIOS_PART_FREE;
244
    strcpy(part_header->name, "free");
245

    
246
    end = 0x1fd0;
247
    OpenBIOS_finish_partition(part_header, end - start);
248

    
249
    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
250

    
251
    for (i = 0; i < sizeof(image); i++)
252
        m48t59_write(nvram, i, image[i]);
253

    
254
    qemu_register_boot_set(nvram_boot_set, nvram);
255
}
256

    
257
static void *slavio_intctl;
258

    
259
void pic_info(void)
260
{
261
    if (slavio_intctl)
262
        slavio_pic_info(slavio_intctl);
263
}
264

    
265
void irq_info(void)
266
{
267
    if (slavio_intctl)
268
        slavio_irq_info(slavio_intctl);
269
}
270

    
271
void cpu_check_irqs(CPUState *env)
272
{
273
    if (env->pil_in && (env->interrupt_index == 0 ||
274
                        (env->interrupt_index & ~15) == TT_EXTINT)) {
275
        unsigned int i;
276

    
277
        for (i = 15; i > 0; i--) {
278
            if (env->pil_in & (1 << i)) {
279
                int old_interrupt = env->interrupt_index;
280

    
281
                env->interrupt_index = TT_EXTINT | i;
282
                if (old_interrupt != env->interrupt_index) {
283
                    DPRINTF("Set CPU IRQ %d\n", i);
284
                    cpu_interrupt(env, CPU_INTERRUPT_HARD);
285
                }
286
                break;
287
            }
288
        }
289
    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
290
        DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
291
        env->interrupt_index = 0;
292
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
293
    }
294
}
295

    
296
static void cpu_set_irq(void *opaque, int irq, int level)
297
{
298
    CPUState *env = opaque;
299

    
300
    if (level) {
301
        DPRINTF("Raise CPU IRQ %d\n", irq);
302
        env->halted = 0;
303
        env->pil_in |= 1 << irq;
304
        cpu_check_irqs(env);
305
    } else {
306
        DPRINTF("Lower CPU IRQ %d\n", irq);
307
        env->pil_in &= ~(1 << irq);
308
        cpu_check_irqs(env);
309
    }
310
}
311

    
312
static void dummy_cpu_set_irq(void *opaque, int irq, int level)
313
{
314
}
315

    
316
static void *slavio_misc;
317

    
318
void qemu_system_powerdown(void)
319
{
320
    slavio_set_power_fail(slavio_misc, 1);
321
}
322

    
323
static void main_cpu_reset(void *opaque)
324
{
325
    CPUState *env = opaque;
326

    
327
    cpu_reset(env);
328
    env->halted = 0;
329
}
330

    
331
static void secondary_cpu_reset(void *opaque)
332
{
333
    CPUState *env = opaque;
334

    
335
    cpu_reset(env);
336
    env->halted = 1;
337
}
338

    
339
static unsigned long sun4m_load_kernel(const char *kernel_filename,
340
                                       const char *initrd_filename,
341
                                       ram_addr_t RAM_size)
342
{
343
    int linux_boot;
344
    unsigned int i;
345
    long initrd_size, kernel_size;
346

    
347
    linux_boot = (kernel_filename != NULL);
348

    
349
    kernel_size = 0;
350
    if (linux_boot) {
351
        kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
352
                               NULL);
353
        if (kernel_size < 0)
354
            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
355
                                    RAM_size - KERNEL_LOAD_ADDR);
356
        if (kernel_size < 0)
357
            kernel_size = load_image_targphys(kernel_filename,
358
                                              KERNEL_LOAD_ADDR,
359
                                              RAM_size - KERNEL_LOAD_ADDR);
360
        if (kernel_size < 0) {
361
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
362
                    kernel_filename);
363
            exit(1);
364
        }
365

    
366
        /* load initrd */
367
        initrd_size = 0;
368
        if (initrd_filename) {
369
            initrd_size = load_image_targphys(initrd_filename,
370
                                              INITRD_LOAD_ADDR,
371
                                              RAM_size - INITRD_LOAD_ADDR);
372
            if (initrd_size < 0) {
373
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
374
                        initrd_filename);
375
                exit(1);
376
            }
377
        }
378
        if (initrd_size > 0) {
379
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
380
                if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
381
                    stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
382
                    stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
383
                    break;
384
                }
385
            }
386
        }
387
    }
388
    return kernel_size;
389
}
390

    
391
static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
392
                          const char *boot_device,
393
                          DisplayState *ds, const char *kernel_filename,
394
                          const char *kernel_cmdline,
395
                          const char *initrd_filename, const char *cpu_model)
396

    
397
{
398
    CPUState *env, *envs[MAX_CPUS];
399
    unsigned int i;
400
    void *iommu, *espdma, *ledma, *main_esp, *nvram;
401
    qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
402
        *espdma_irq, *ledma_irq;
403
    qemu_irq *esp_reset, *le_reset;
404
    qemu_irq *fdc_tc;
405
    unsigned long prom_offset, kernel_size;
406
    int ret;
407
    char buf[1024];
408
    BlockDriverState *fd[MAX_FD];
409
    int drive_index;
410

    
411
    /* init CPUs */
412
    if (!cpu_model)
413
        cpu_model = hwdef->default_cpu_model;
414

    
415
    for(i = 0; i < smp_cpus; i++) {
416
        env = cpu_init(cpu_model);
417
        if (!env) {
418
            fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
419
            exit(1);
420
        }
421
        cpu_sparc_set_id(env, i);
422
        envs[i] = env;
423
        if (i == 0) {
424
            qemu_register_reset(main_cpu_reset, env);
425
        } else {
426
            qemu_register_reset(secondary_cpu_reset, env);
427
            env->halted = 1;
428
        }
429
        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
430
        env->prom_addr = hwdef->slavio_base;
431
    }
432

    
433
    for (i = smp_cpus; i < MAX_CPUS; i++)
434
        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
435

    
436

    
437
    /* allocate RAM */
438
    if ((uint64_t)RAM_size > hwdef->max_mem) {
439
        fprintf(stderr,
440
                "qemu: Too much memory for this machine: %d, maximum %d\n",
441
                (unsigned int)(RAM_size / (1024 * 1024)),
442
                (unsigned int)(hwdef->max_mem / (1024 * 1024)));
443
        exit(1);
444
    }
445
    cpu_register_physical_memory(0, RAM_size, 0);
446

    
447
    /* load boot prom */
448
    prom_offset = RAM_size + hwdef->vram_size;
449
    cpu_register_physical_memory(hwdef->slavio_base,
450
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
451
                                 TARGET_PAGE_MASK,
452
                                 prom_offset | IO_MEM_ROM);
453

    
454
    if (bios_name == NULL)
455
        bios_name = PROM_FILENAME;
456
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
457
    ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
458
    if (ret < 0 || ret > PROM_SIZE_MAX)
459
        ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
460
    if (ret < 0 || ret > PROM_SIZE_MAX) {
461
        fprintf(stderr, "qemu: could not load prom '%s'\n",
462
                buf);
463
        exit(1);
464
    }
465
    prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
466

    
467
    /* set up devices */
468
    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
469
                                       hwdef->intctl_base + 0x10000ULL,
470
                                       &hwdef->intbit_to_level[0],
471
                                       &slavio_irq, &slavio_cpu_irq,
472
                                       cpu_irqs,
473
                                       hwdef->clock_irq);
474

    
475
    if (hwdef->idreg_base != (target_phys_addr_t)-1) {
476
        static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
477

    
478
        cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
479
                                     prom_offset | IO_MEM_ROM);
480
        cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
481
                                      sizeof(idreg_data));
482
    }
483

    
484
    iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
485
                       slavio_irq[hwdef->me_irq]);
486

    
487
    espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
488
                              iommu, &espdma_irq, &esp_reset);
489

    
490
    ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
491
                             slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
492
                             &le_reset);
493

    
494
    if (graphic_depth != 8 && graphic_depth != 24) {
495
        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
496
        exit (1);
497
    }
498
    tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
499
             hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
500

    
501
    if (nd_table[0].model == NULL
502
        || strcmp(nd_table[0].model, "lance") == 0) {
503
        lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
504
    } else if (strcmp(nd_table[0].model, "?") == 0) {
505
        fprintf(stderr, "qemu: Supported NICs: lance\n");
506
        exit (1);
507
    } else {
508
        fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
509
        exit (1);
510
    }
511

    
512
    nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
513
                        hwdef->nvram_size, 8);
514

    
515
    slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
516
                          slavio_cpu_irq, smp_cpus);
517

    
518
    slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
519
                              nographic);
520
    // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
521
    // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
522
    slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
523
                       serial_hds[1], serial_hds[0]);
524

    
525
    slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
526
                                   hwdef->aux1_base, hwdef->aux2_base,
527
                                   slavio_irq[hwdef->me_irq], envs[0],
528
                                   &fdc_tc);
529

    
530
    if (hwdef->fd_base != (target_phys_addr_t)-1) {
531
        /* there is zero or one floppy drive */
532
        memset(fd, 0, sizeof(fd));
533
        drive_index = drive_get_index(IF_FLOPPY, 0, 0);
534
        if (drive_index != -1)
535
            fd[0] = drives_table[drive_index].bdrv;
536

    
537
        sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
538
                          fdc_tc);
539
    }
540

    
541
    if (drive_get_max_bus(IF_SCSI) > 0) {
542
        fprintf(stderr, "qemu: too many SCSI bus\n");
543
        exit(1);
544
    }
545

    
546
    main_esp = esp_init(hwdef->esp_base, 2,
547
                        espdma_memory_read, espdma_memory_write,
548
                        espdma, *espdma_irq, esp_reset);
549

    
550
    for (i = 0; i < ESP_MAX_DEVS; i++) {
551
        drive_index = drive_get_index(IF_SCSI, 0, i);
552
        if (drive_index == -1)
553
            continue;
554
        esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
555
    }
556

    
557
    if (hwdef->cs_base != (target_phys_addr_t)-1)
558
        cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
559

    
560
    kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
561
                                    RAM_size);
562

    
563
    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
564
               boot_device, RAM_size, kernel_size, graphic_width,
565
               graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
566

    
567
    if (hwdef->ecc_base != (target_phys_addr_t)-1)
568
        ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
569
                 hwdef->ecc_version);
570
}
571

    
572
static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
573
                          const char *boot_device,
574
                          DisplayState *ds, const char *kernel_filename,
575
                          const char *kernel_cmdline,
576
                          const char *initrd_filename, const char *cpu_model)
577
{
578
    CPUState *env;
579
    unsigned int i;
580
    void *iommu, *espdma, *ledma, *main_esp, *nvram;
581
    qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
582
    qemu_irq *esp_reset, *le_reset;
583
    qemu_irq *fdc_tc;
584
    unsigned long prom_offset, kernel_size;
585
    int ret;
586
    char buf[1024];
587
    BlockDriverState *fd[MAX_FD];
588
    int drive_index;
589

    
590
    /* init CPU */
591
    if (!cpu_model)
592
        cpu_model = hwdef->default_cpu_model;
593

    
594
    env = cpu_init(cpu_model);
595
    if (!env) {
596
        fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
597
        exit(1);
598
    }
599

    
600
    cpu_sparc_set_id(env, 0);
601

    
602
    qemu_register_reset(main_cpu_reset, env);
603
    cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
604
    env->prom_addr = hwdef->slavio_base;
605

    
606
    /* allocate RAM */
607
    if ((uint64_t)RAM_size > hwdef->max_mem) {
608
        fprintf(stderr,
609
                "qemu: Too much memory for this machine: %d, maximum %d\n",
610
                (unsigned int)(RAM_size / (1024 * 1024)),
611
                (unsigned int)(hwdef->max_mem / (1024 * 1024)));
612
        exit(1);
613
    }
614
    cpu_register_physical_memory(0, RAM_size, 0);
615

    
616
    /* load boot prom */
617
    prom_offset = RAM_size + hwdef->vram_size;
618
    cpu_register_physical_memory(hwdef->slavio_base,
619
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
620
                                 TARGET_PAGE_MASK,
621
                                 prom_offset | IO_MEM_ROM);
622

    
623
    if (bios_name == NULL)
624
        bios_name = PROM_FILENAME;
625
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
626
    ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
627
    if (ret < 0 || ret > PROM_SIZE_MAX)
628
        ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
629
    if (ret < 0 || ret > PROM_SIZE_MAX) {
630
        fprintf(stderr, "qemu: could not load prom '%s'\n",
631
                buf);
632
        exit(1);
633
    }
634
    prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
635

    
636
    /* set up devices */
637
    slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
638
                                      &slavio_irq, cpu_irqs);
639

    
640
    iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
641
                       slavio_irq[hwdef->me_irq]);
642

    
643
    espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
644
                              iommu, &espdma_irq, &esp_reset);
645

    
646
    ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
647
                             slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
648
                             &le_reset);
649

    
650
    if (graphic_depth != 8 && graphic_depth != 24) {
651
        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
652
        exit (1);
653
    }
654
    tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
655
             hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
656

    
657
    if (nd_table[0].model == NULL
658
        || strcmp(nd_table[0].model, "lance") == 0) {
659
        lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
660
    } else if (strcmp(nd_table[0].model, "?") == 0) {
661
        fprintf(stderr, "qemu: Supported NICs: lance\n");
662
        exit (1);
663
    } else {
664
        fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
665
        exit (1);
666
    }
667

    
668
    nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
669
                        hwdef->nvram_size, 2);
670

    
671
    slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
672
                              nographic);
673
    // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
674
    // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
675
    slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
676
                       serial_hds[1], serial_hds[0]);
677

    
678
    slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
679
                                   hwdef->aux1_base, hwdef->aux2_base,
680
                                   slavio_irq[hwdef->me_irq], env, &fdc_tc);
681

    
682
    if (hwdef->fd_base != (target_phys_addr_t)-1) {
683
        /* there is zero or one floppy drive */
684
        fd[1] = fd[0] = NULL;
685
        drive_index = drive_get_index(IF_FLOPPY, 0, 0);
686
        if (drive_index != -1)
687
            fd[0] = drives_table[drive_index].bdrv;
688

    
689
        sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
690
                          fdc_tc);
691
    }
692

    
693
    if (drive_get_max_bus(IF_SCSI) > 0) {
694
        fprintf(stderr, "qemu: too many SCSI bus\n");
695
        exit(1);
696
    }
697

    
698
    main_esp = esp_init(hwdef->esp_base, 2,
699
                        espdma_memory_read, espdma_memory_write,
700
                        espdma, *espdma_irq, esp_reset);
701

    
702
    for (i = 0; i < ESP_MAX_DEVS; i++) {
703
        drive_index = drive_get_index(IF_SCSI, 0, i);
704
        if (drive_index == -1)
705
            continue;
706
        esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
707
    }
708

    
709
    kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
710
                                    RAM_size);
711

    
712
    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
713
               boot_device, RAM_size, kernel_size, graphic_width,
714
               graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
715
}
716

    
717
static const struct hwdef hwdefs[] = {
718
    /* SS-5 */
719
    {
720
        .iommu_base   = 0x10000000,
721
        .tcx_base     = 0x50000000,
722
        .cs_base      = 0x6c000000,
723
        .slavio_base  = 0x70000000,
724
        .ms_kb_base   = 0x71000000,
725
        .serial_base  = 0x71100000,
726
        .nvram_base   = 0x71200000,
727
        .fd_base      = 0x71400000,
728
        .counter_base = 0x71d00000,
729
        .intctl_base  = 0x71e00000,
730
        .idreg_base   = 0x78000000,
731
        .dma_base     = 0x78400000,
732
        .esp_base     = 0x78800000,
733
        .le_base      = 0x78c00000,
734
        .apc_base     = 0x6a000000,
735
        .aux1_base    = 0x71900000,
736
        .aux2_base    = 0x71910000,
737
        .ecc_base     = -1,
738
        .sun4c_intctl_base  = -1,
739
        .sun4c_counter_base = -1,
740
        .vram_size    = 0x00100000,
741
        .nvram_size   = 0x2000,
742
        .esp_irq = 18,
743
        .le_irq = 16,
744
        .clock_irq = 7,
745
        .clock1_irq = 19,
746
        .ms_kb_irq = 14,
747
        .ser_irq = 15,
748
        .fd_irq = 22,
749
        .me_irq = 30,
750
        .cs_irq = 5,
751
        .machine_id = 0x80,
752
        .iommu_version = 0x05000000,
753
        .intbit_to_level = {
754
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
755
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
756
        },
757
        .max_mem = 0x10000000,
758
        .default_cpu_model = "Fujitsu MB86904",
759
    },
760
    /* SS-10 */
761
    {
762
        .iommu_base   = 0xfe0000000ULL,
763
        .tcx_base     = 0xe20000000ULL,
764
        .cs_base      = -1,
765
        .slavio_base  = 0xff0000000ULL,
766
        .ms_kb_base   = 0xff1000000ULL,
767
        .serial_base  = 0xff1100000ULL,
768
        .nvram_base   = 0xff1200000ULL,
769
        .fd_base      = 0xff1700000ULL,
770
        .counter_base = 0xff1300000ULL,
771
        .intctl_base  = 0xff1400000ULL,
772
        .idreg_base   = 0xef0000000ULL,
773
        .dma_base     = 0xef0400000ULL,
774
        .esp_base     = 0xef0800000ULL,
775
        .le_base      = 0xef0c00000ULL,
776
        .apc_base     = 0xefa000000ULL, // XXX should not exist
777
        .aux1_base    = 0xff1800000ULL,
778
        .aux2_base    = 0xff1a01000ULL,
779
        .ecc_base     = 0xf00000000ULL,
780
        .ecc_version  = 0x10000000, // version 0, implementation 1
781
        .sun4c_intctl_base  = -1,
782
        .sun4c_counter_base = -1,
783
        .vram_size    = 0x00100000,
784
        .nvram_size   = 0x2000,
785
        .esp_irq = 18,
786
        .le_irq = 16,
787
        .clock_irq = 7,
788
        .clock1_irq = 19,
789
        .ms_kb_irq = 14,
790
        .ser_irq = 15,
791
        .fd_irq = 22,
792
        .me_irq = 30,
793
        .cs_irq = -1,
794
        .ecc_irq = 28,
795
        .machine_id = 0x72,
796
        .iommu_version = 0x03000000,
797
        .intbit_to_level = {
798
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
799
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
800
        },
801
        .max_mem = 0xf00000000ULL,
802
        .default_cpu_model = "TI SuperSparc II",
803
    },
804
    /* SS-600MP */
805
    {
806
        .iommu_base   = 0xfe0000000ULL,
807
        .tcx_base     = 0xe20000000ULL,
808
        .cs_base      = -1,
809
        .slavio_base  = 0xff0000000ULL,
810
        .ms_kb_base   = 0xff1000000ULL,
811
        .serial_base  = 0xff1100000ULL,
812
        .nvram_base   = 0xff1200000ULL,
813
        .fd_base      = -1,
814
        .counter_base = 0xff1300000ULL,
815
        .intctl_base  = 0xff1400000ULL,
816
        .idreg_base   = -1,
817
        .dma_base     = 0xef0081000ULL,
818
        .esp_base     = 0xef0080000ULL,
819
        .le_base      = 0xef0060000ULL,
820
        .apc_base     = 0xefa000000ULL, // XXX should not exist
821
        .aux1_base    = 0xff1800000ULL,
822
        .aux2_base    = 0xff1a01000ULL, // XXX should not exist
823
        .ecc_base     = 0xf00000000ULL,
824
        .ecc_version  = 0x00000000, // version 0, implementation 0
825
        .sun4c_intctl_base  = -1,
826
        .sun4c_counter_base = -1,
827
        .vram_size    = 0x00100000,
828
        .nvram_size   = 0x2000,
829
        .esp_irq = 18,
830
        .le_irq = 16,
831
        .clock_irq = 7,
832
        .clock1_irq = 19,
833
        .ms_kb_irq = 14,
834
        .ser_irq = 15,
835
        .fd_irq = 22,
836
        .me_irq = 30,
837
        .cs_irq = -1,
838
        .ecc_irq = 28,
839
        .machine_id = 0x71,
840
        .iommu_version = 0x01000000,
841
        .intbit_to_level = {
842
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
843
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
844
        },
845
        .max_mem = 0xf00000000ULL,
846
        .default_cpu_model = "TI SuperSparc II",
847
    },
848
    /* SS-20 */
849
    {
850
        .iommu_base   = 0xfe0000000ULL,
851
        .tcx_base     = 0xe20000000ULL,
852
        .cs_base      = -1,
853
        .slavio_base  = 0xff0000000ULL,
854
        .ms_kb_base   = 0xff1000000ULL,
855
        .serial_base  = 0xff1100000ULL,
856
        .nvram_base   = 0xff1200000ULL,
857
        .fd_base      = 0xff1700000ULL,
858
        .counter_base = 0xff1300000ULL,
859
        .intctl_base  = 0xff1400000ULL,
860
        .idreg_base   = 0xef0000000ULL,
861
        .dma_base     = 0xef0400000ULL,
862
        .esp_base     = 0xef0800000ULL,
863
        .le_base      = 0xef0c00000ULL,
864
        .apc_base     = 0xefa000000ULL, // XXX should not exist
865
        .aux1_base    = 0xff1800000ULL,
866
        .aux2_base    = 0xff1a01000ULL,
867
        .ecc_base     = 0xf00000000ULL,
868
        .ecc_version  = 0x20000000, // version 0, implementation 2
869
        .sun4c_intctl_base  = -1,
870
        .sun4c_counter_base = -1,
871
        .vram_size    = 0x00100000,
872
        .nvram_size   = 0x2000,
873
        .esp_irq = 18,
874
        .le_irq = 16,
875
        .clock_irq = 7,
876
        .clock1_irq = 19,
877
        .ms_kb_irq = 14,
878
        .ser_irq = 15,
879
        .fd_irq = 22,
880
        .me_irq = 30,
881
        .cs_irq = -1,
882
        .ecc_irq = 28,
883
        .machine_id = 0x72,
884
        .iommu_version = 0x13000000,
885
        .intbit_to_level = {
886
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
887
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
888
        },
889
        .max_mem = 0xf00000000ULL,
890
        .default_cpu_model = "TI SuperSparc II",
891
    },
892
    /* SS-2 */
893
    {
894
        .iommu_base   = 0xf8000000,
895
        .tcx_base     = 0xfe000000,
896
        .cs_base      = -1,
897
        .slavio_base  = 0xf6000000,
898
        .ms_kb_base   = 0xf0000000,
899
        .serial_base  = 0xf1000000,
900
        .nvram_base   = 0xf2000000,
901
        .fd_base      = 0xf7200000,
902
        .counter_base = -1,
903
        .intctl_base  = -1,
904
        .dma_base     = 0xf8400000,
905
        .esp_base     = 0xf8800000,
906
        .le_base      = 0xf8c00000,
907
        .apc_base     = -1,
908
        .aux1_base    = 0xf7400003,
909
        .aux2_base    = -1,
910
        .sun4c_intctl_base  = 0xf5000000,
911
        .sun4c_counter_base = 0xf3000000,
912
        .vram_size    = 0x00100000,
913
        .nvram_size   = 0x800,
914
        .esp_irq = 2,
915
        .le_irq = 3,
916
        .clock_irq = 5,
917
        .clock1_irq = 7,
918
        .ms_kb_irq = 1,
919
        .ser_irq = 1,
920
        .fd_irq = 1,
921
        .me_irq = 1,
922
        .cs_irq = -1,
923
        .machine_id = 0x55,
924
        .max_mem = 0x10000000,
925
        .default_cpu_model = "Cypress CY7C601",
926
    },
927
    /* Voyager */
928
    {
929
        .iommu_base   = 0x10000000,
930
        .tcx_base     = 0x50000000,
931
        .cs_base      = -1,
932
        .slavio_base  = 0x70000000,
933
        .ms_kb_base   = 0x71000000,
934
        .serial_base  = 0x71100000,
935
        .nvram_base   = 0x71200000,
936
        .fd_base      = 0x71400000,
937
        .counter_base = 0x71d00000,
938
        .intctl_base  = 0x71e00000,
939
        .idreg_base   = 0x78000000,
940
        .dma_base     = 0x78400000,
941
        .esp_base     = 0x78800000,
942
        .le_base      = 0x78c00000,
943
        .apc_base     = 0x71300000, // pmc
944
        .aux1_base    = 0x71900000,
945
        .aux2_base    = 0x71910000,
946
        .ecc_base     = -1,
947
        .sun4c_intctl_base  = -1,
948
        .sun4c_counter_base = -1,
949
        .vram_size    = 0x00100000,
950
        .nvram_size   = 0x2000,
951
        .esp_irq = 18,
952
        .le_irq = 16,
953
        .clock_irq = 7,
954
        .clock1_irq = 19,
955
        .ms_kb_irq = 14,
956
        .ser_irq = 15,
957
        .fd_irq = 22,
958
        .me_irq = 30,
959
        .cs_irq = -1,
960
        .machine_id = 0x80,
961
        .iommu_version = 0x05000000,
962
        .intbit_to_level = {
963
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
964
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
965
        },
966
        .max_mem = 0x10000000,
967
        .default_cpu_model = "Fujitsu MB86904",
968
    },
969
    /* LX */
970
    {
971
        .iommu_base   = 0x10000000,
972
        .tcx_base     = 0x50000000,
973
        .cs_base      = -1,
974
        .slavio_base  = 0x70000000,
975
        .ms_kb_base   = 0x71000000,
976
        .serial_base  = 0x71100000,
977
        .nvram_base   = 0x71200000,
978
        .fd_base      = 0x71400000,
979
        .counter_base = 0x71d00000,
980
        .intctl_base  = 0x71e00000,
981
        .idreg_base   = 0x78000000,
982
        .dma_base     = 0x78400000,
983
        .esp_base     = 0x78800000,
984
        .le_base      = 0x78c00000,
985
        .apc_base     = -1,
986
        .aux1_base    = 0x71900000,
987
        .aux2_base    = 0x71910000,
988
        .ecc_base     = -1,
989
        .sun4c_intctl_base  = -1,
990
        .sun4c_counter_base = -1,
991
        .vram_size    = 0x00100000,
992
        .nvram_size   = 0x2000,
993
        .esp_irq = 18,
994
        .le_irq = 16,
995
        .clock_irq = 7,
996
        .clock1_irq = 19,
997
        .ms_kb_irq = 14,
998
        .ser_irq = 15,
999
        .fd_irq = 22,
1000
        .me_irq = 30,
1001
        .cs_irq = -1,
1002
        .machine_id = 0x80,
1003
        .iommu_version = 0x04000000,
1004
        .intbit_to_level = {
1005
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
1006
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
1007
        },
1008
        .max_mem = 0x10000000,
1009
        .default_cpu_model = "TI MicroSparc I",
1010
    },
1011
    /* SS-4 */
1012
    {
1013
        .iommu_base   = 0x10000000,
1014
        .tcx_base     = 0x50000000,
1015
        .cs_base      = 0x6c000000,
1016
        .slavio_base  = 0x70000000,
1017
        .ms_kb_base   = 0x71000000,
1018
        .serial_base  = 0x71100000,
1019
        .nvram_base   = 0x71200000,
1020
        .fd_base      = 0x71400000,
1021
        .counter_base = 0x71d00000,
1022
        .intctl_base  = 0x71e00000,
1023
        .idreg_base   = 0x78000000,
1024
        .dma_base     = 0x78400000,
1025
        .esp_base     = 0x78800000,
1026
        .le_base      = 0x78c00000,
1027
        .apc_base     = 0x6a000000,
1028
        .aux1_base    = 0x71900000,
1029
        .aux2_base    = 0x71910000,
1030
        .ecc_base     = -1,
1031
        .sun4c_intctl_base  = -1,
1032
        .sun4c_counter_base = -1,
1033
        .vram_size    = 0x00100000,
1034
        .nvram_size   = 0x2000,
1035
        .esp_irq = 18,
1036
        .le_irq = 16,
1037
        .clock_irq = 7,
1038
        .clock1_irq = 19,
1039
        .ms_kb_irq = 14,
1040
        .ser_irq = 15,
1041
        .fd_irq = 22,
1042
        .me_irq = 30,
1043
        .cs_irq = 5,
1044
        .machine_id = 0x80,
1045
        .iommu_version = 0x05000000,
1046
        .intbit_to_level = {
1047
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
1048
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
1049
        },
1050
        .max_mem = 0x10000000,
1051
        .default_cpu_model = "Fujitsu MB86904",
1052
    },
1053
    /* SPARCClassic */
1054
    {
1055
        .iommu_base   = 0x10000000,
1056
        .tcx_base     = 0x50000000,
1057
        .cs_base      = -1,
1058
        .slavio_base  = 0x70000000,
1059
        .ms_kb_base   = 0x71000000,
1060
        .serial_base  = 0x71100000,
1061
        .nvram_base   = 0x71200000,
1062
        .fd_base      = 0x71400000,
1063
        .counter_base = 0x71d00000,
1064
        .intctl_base  = 0x71e00000,
1065
        .idreg_base   = 0x78000000,
1066
        .dma_base     = 0x78400000,
1067
        .esp_base     = 0x78800000,
1068
        .le_base      = 0x78c00000,
1069
        .apc_base     = 0x6a000000,
1070
        .aux1_base    = 0x71900000,
1071
        .aux2_base    = 0x71910000,
1072
        .ecc_base     = -1,
1073
        .sun4c_intctl_base  = -1,
1074
        .sun4c_counter_base = -1,
1075
        .vram_size    = 0x00100000,
1076
        .nvram_size   = 0x2000,
1077
        .esp_irq = 18,
1078
        .le_irq = 16,
1079
        .clock_irq = 7,
1080
        .clock1_irq = 19,
1081
        .ms_kb_irq = 14,
1082
        .ser_irq = 15,
1083
        .fd_irq = 22,
1084
        .me_irq = 30,
1085
        .cs_irq = -1,
1086
        .machine_id = 0x80,
1087
        .iommu_version = 0x05000000,
1088
        .intbit_to_level = {
1089
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
1090
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
1091
        },
1092
        .max_mem = 0x10000000,
1093
        .default_cpu_model = "TI MicroSparc I",
1094
    },
1095
    /* SPARCbook */
1096
    {
1097
        .iommu_base   = 0x10000000,
1098
        .tcx_base     = 0x50000000, // XXX
1099
        .cs_base      = -1,
1100
        .slavio_base  = 0x70000000,
1101
        .ms_kb_base   = 0x71000000,
1102
        .serial_base  = 0x71100000,
1103
        .nvram_base   = 0x71200000,
1104
        .fd_base      = 0x71400000,
1105
        .counter_base = 0x71d00000,
1106
        .intctl_base  = 0x71e00000,
1107
        .idreg_base   = 0x78000000,
1108
        .dma_base     = 0x78400000,
1109
        .esp_base     = 0x78800000,
1110
        .le_base      = 0x78c00000,
1111
        .apc_base     = 0x6a000000,
1112
        .aux1_base    = 0x71900000,
1113
        .aux2_base    = 0x71910000,
1114
        .ecc_base     = -1,
1115
        .sun4c_intctl_base  = -1,
1116
        .sun4c_counter_base = -1,
1117
        .vram_size    = 0x00100000,
1118
        .nvram_size   = 0x2000,
1119
        .esp_irq = 18,
1120
        .le_irq = 16,
1121
        .clock_irq = 7,
1122
        .clock1_irq = 19,
1123
        .ms_kb_irq = 14,
1124
        .ser_irq = 15,
1125
        .fd_irq = 22,
1126
        .me_irq = 30,
1127
        .cs_irq = -1,
1128
        .machine_id = 0x80,
1129
        .iommu_version = 0x05000000,
1130
        .intbit_to_level = {
1131
            2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
1132
            6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
1133
        },
1134
        .max_mem = 0x10000000,
1135
        .default_cpu_model = "TI MicroSparc I",
1136
    },
1137
};
1138

    
1139
/* SPARCstation 5 hardware initialisation */
1140
static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1141
                     const char *boot_device, DisplayState *ds,
1142
                     const char *kernel_filename, const char *kernel_cmdline,
1143
                     const char *initrd_filename, const char *cpu_model)
1144
{
1145
    sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1146
                  kernel_cmdline, initrd_filename, cpu_model);
1147
}
1148

    
1149
/* SPARCstation 10 hardware initialisation */
1150
static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1151
                      const char *boot_device, DisplayState *ds,
1152
                      const char *kernel_filename, const char *kernel_cmdline,
1153
                      const char *initrd_filename, const char *cpu_model)
1154
{
1155
    sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1156
                  kernel_cmdline, initrd_filename, cpu_model);
1157
}
1158

    
1159
/* SPARCserver 600MP hardware initialisation */
1160
static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1161
                         const char *boot_device, DisplayState *ds,
1162
                         const char *kernel_filename,
1163
                         const char *kernel_cmdline,
1164
                         const char *initrd_filename, const char *cpu_model)
1165
{
1166
    sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1167
                  kernel_cmdline, initrd_filename, cpu_model);
1168
}
1169

    
1170
/* SPARCstation 20 hardware initialisation */
1171
static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1172
                      const char *boot_device, DisplayState *ds,
1173
                      const char *kernel_filename, const char *kernel_cmdline,
1174
                      const char *initrd_filename, const char *cpu_model)
1175
{
1176
    sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1177
                  kernel_cmdline, initrd_filename, cpu_model);
1178
}
1179

    
1180
/* SPARCstation 2 hardware initialisation */
1181
static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1182
                     const char *boot_device, DisplayState *ds,
1183
                     const char *kernel_filename, const char *kernel_cmdline,
1184
                     const char *initrd_filename, const char *cpu_model)
1185
{
1186
    sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1187
                  kernel_cmdline, initrd_filename, cpu_model);
1188
}
1189

    
1190
/* SPARCstation Voyager hardware initialisation */
1191
static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1192
                      const char *boot_device, DisplayState *ds,
1193
                      const char *kernel_filename, const char *kernel_cmdline,
1194
                      const char *initrd_filename, const char *cpu_model)
1195
{
1196
    sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1197
                  kernel_cmdline, initrd_filename, cpu_model);
1198
}
1199

    
1200
/* SPARCstation LX hardware initialisation */
1201
static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1202
                       const char *boot_device, DisplayState *ds,
1203
                       const char *kernel_filename, const char *kernel_cmdline,
1204
                       const char *initrd_filename, const char *cpu_model)
1205
{
1206
    sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1207
                  kernel_cmdline, initrd_filename, cpu_model);
1208
}
1209

    
1210
/* SPARCstation 4 hardware initialisation */
1211
static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1212
                     const char *boot_device, DisplayState *ds,
1213
                     const char *kernel_filename, const char *kernel_cmdline,
1214
                     const char *initrd_filename, const char *cpu_model)
1215
{
1216
    sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1217
                  kernel_cmdline, initrd_filename, cpu_model);
1218
}
1219

    
1220
/* SPARCClassic hardware initialisation */
1221
static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1222
                      const char *boot_device, DisplayState *ds,
1223
                      const char *kernel_filename, const char *kernel_cmdline,
1224
                      const char *initrd_filename, const char *cpu_model)
1225
{
1226
    sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1227
                  kernel_cmdline, initrd_filename, cpu_model);
1228
}
1229

    
1230
/* SPARCbook hardware initialisation */
1231
static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1232
                       const char *boot_device, DisplayState *ds,
1233
                       const char *kernel_filename, const char *kernel_cmdline,
1234
                       const char *initrd_filename, const char *cpu_model)
1235
{
1236
    sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1237
                  kernel_cmdline, initrd_filename, cpu_model);
1238
}
1239

    
1240
QEMUMachine ss5_machine = {
1241
    "SS-5",
1242
    "Sun4m platform, SPARCstation 5",
1243
    ss5_init,
1244
    PROM_SIZE_MAX + TCX_SIZE,
1245
};
1246

    
1247
QEMUMachine ss10_machine = {
1248
    "SS-10",
1249
    "Sun4m platform, SPARCstation 10",
1250
    ss10_init,
1251
    PROM_SIZE_MAX + TCX_SIZE,
1252
};
1253

    
1254
QEMUMachine ss600mp_machine = {
1255
    "SS-600MP",
1256
    "Sun4m platform, SPARCserver 600MP",
1257
    ss600mp_init,
1258
    PROM_SIZE_MAX + TCX_SIZE,
1259
};
1260

    
1261
QEMUMachine ss20_machine = {
1262
    "SS-20",
1263
    "Sun4m platform, SPARCstation 20",
1264
    ss20_init,
1265
    PROM_SIZE_MAX + TCX_SIZE,
1266
};
1267

    
1268
QEMUMachine ss2_machine = {
1269
    "SS-2",
1270
    "Sun4c platform, SPARCstation 2",
1271
    ss2_init,
1272
    PROM_SIZE_MAX + TCX_SIZE,
1273
};
1274

    
1275
QEMUMachine voyager_machine = {
1276
    "Voyager",
1277
    "Sun4m platform, SPARCstation Voyager",
1278
    vger_init,
1279
    PROM_SIZE_MAX + TCX_SIZE,
1280
};
1281

    
1282
QEMUMachine ss_lx_machine = {
1283
    "LX",
1284
    "Sun4m platform, SPARCstation LX",
1285
    ss_lx_init,
1286
    PROM_SIZE_MAX + TCX_SIZE,
1287
};
1288

    
1289
QEMUMachine ss4_machine = {
1290
    "SS-4",
1291
    "Sun4m platform, SPARCstation 4",
1292
    ss4_init,
1293
    PROM_SIZE_MAX + TCX_SIZE,
1294
};
1295

    
1296
QEMUMachine scls_machine = {
1297
    "SPARCClassic",
1298
    "Sun4m platform, SPARCClassic",
1299
    scls_init,
1300
    PROM_SIZE_MAX + TCX_SIZE,
1301
};
1302

    
1303
QEMUMachine sbook_machine = {
1304
    "SPARCbook",
1305
    "Sun4m platform, SPARCbook",
1306
    sbook_init,
1307
    PROM_SIZE_MAX + TCX_SIZE,
1308
};
1309

    
1310
static const struct sun4d_hwdef sun4d_hwdefs[] = {
1311
    /* SS-1000 */
1312
    {
1313
        .iounit_bases   = {
1314
            0xfe0200000ULL,
1315
            0xfe1200000ULL,
1316
            0xfe2200000ULL,
1317
            0xfe3200000ULL,
1318
            -1,
1319
        },
1320
        .tcx_base     = 0x820000000ULL,
1321
        .slavio_base  = 0xf00000000ULL,
1322
        .ms_kb_base   = 0xf00240000ULL,
1323
        .serial_base  = 0xf00200000ULL,
1324
        .nvram_base   = 0xf00280000ULL,
1325
        .counter_base = 0xf00300000ULL,
1326
        .espdma_base  = 0x800081000ULL,
1327
        .esp_base     = 0x800080000ULL,
1328
        .ledma_base   = 0x800040000ULL,
1329
        .le_base      = 0x800060000ULL,
1330
        .sbi_base     = 0xf02800000ULL,
1331
        .vram_size    = 0x00100000,
1332
        .nvram_size   = 0x2000,
1333
        .esp_irq = 3,
1334
        .le_irq = 4,
1335
        .clock_irq = 14,
1336
        .clock1_irq = 10,
1337
        .ms_kb_irq = 12,
1338
        .ser_irq = 12,
1339
        .machine_id = 0x80,
1340
        .iounit_version = 0x03000000,
1341
        .max_mem = 0xf00000000ULL,
1342
        .default_cpu_model = "TI SuperSparc II",
1343
    },
1344
    /* SS-2000 */
1345
    {
1346
        .iounit_bases   = {
1347
            0xfe0200000ULL,
1348
            0xfe1200000ULL,
1349
            0xfe2200000ULL,
1350
            0xfe3200000ULL,
1351
            0xfe4200000ULL,
1352
        },
1353
        .tcx_base     = 0x820000000ULL,
1354
        .slavio_base  = 0xf00000000ULL,
1355
        .ms_kb_base   = 0xf00240000ULL,
1356
        .serial_base  = 0xf00200000ULL,
1357
        .nvram_base   = 0xf00280000ULL,
1358
        .counter_base = 0xf00300000ULL,
1359
        .espdma_base  = 0x800081000ULL,
1360
        .esp_base     = 0x800080000ULL,
1361
        .ledma_base   = 0x800040000ULL,
1362
        .le_base      = 0x800060000ULL,
1363
        .sbi_base     = 0xf02800000ULL,
1364
        .vram_size    = 0x00100000,
1365
        .nvram_size   = 0x2000,
1366
        .esp_irq = 3,
1367
        .le_irq = 4,
1368
        .clock_irq = 14,
1369
        .clock1_irq = 10,
1370
        .ms_kb_irq = 12,
1371
        .ser_irq = 12,
1372
        .machine_id = 0x80,
1373
        .iounit_version = 0x03000000,
1374
        .max_mem = 0xf00000000ULL,
1375
        .default_cpu_model = "TI SuperSparc II",
1376
    },
1377
};
1378

    
1379
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1380
                          const char *boot_device,
1381
                          DisplayState *ds, const char *kernel_filename,
1382
                          const char *kernel_cmdline,
1383
                          const char *initrd_filename, const char *cpu_model)
1384
{
1385
    CPUState *env, *envs[MAX_CPUS];
1386
    unsigned int i;
1387
    void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1388
    qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1389
        *espdma_irq, *ledma_irq;
1390
    qemu_irq *esp_reset, *le_reset;
1391
    unsigned long prom_offset, kernel_size;
1392
    int ret;
1393
    char buf[1024];
1394
    int drive_index;
1395

    
1396
    /* init CPUs */
1397
    if (!cpu_model)
1398
        cpu_model = hwdef->default_cpu_model;
1399

    
1400
    for (i = 0; i < smp_cpus; i++) {
1401
        env = cpu_init(cpu_model);
1402
        if (!env) {
1403
            fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1404
            exit(1);
1405
        }
1406
        cpu_sparc_set_id(env, i);
1407
        envs[i] = env;
1408
        if (i == 0) {
1409
            qemu_register_reset(main_cpu_reset, env);
1410
        } else {
1411
            qemu_register_reset(secondary_cpu_reset, env);
1412
            env->halted = 1;
1413
        }
1414
        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1415
        env->prom_addr = hwdef->slavio_base;
1416
    }
1417

    
1418
    for (i = smp_cpus; i < MAX_CPUS; i++)
1419
        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1420

    
1421
    /* allocate RAM */
1422
    if ((uint64_t)RAM_size > hwdef->max_mem) {
1423
        fprintf(stderr,
1424
                "qemu: Too much memory for this machine: %d, maximum %d\n",
1425
                (unsigned int)(RAM_size / (1024 * 1024)),
1426
                (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1427
        exit(1);
1428
    }
1429
    cpu_register_physical_memory(0, RAM_size, 0);
1430

    
1431
    /* load boot prom */
1432
    prom_offset = RAM_size + hwdef->vram_size;
1433
    cpu_register_physical_memory(hwdef->slavio_base,
1434
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1435
                                 TARGET_PAGE_MASK,
1436
                                 prom_offset | IO_MEM_ROM);
1437

    
1438
    if (bios_name == NULL)
1439
        bios_name = PROM_FILENAME;
1440
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1441
    ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1442
    if (ret < 0 || ret > PROM_SIZE_MAX)
1443
        ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1444
    if (ret < 0 || ret > PROM_SIZE_MAX) {
1445
        fprintf(stderr, "qemu: could not load prom '%s'\n",
1446
                buf);
1447
        exit(1);
1448
    }
1449

    
1450
    /* set up devices */
1451
    sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1452

    
1453
    for (i = 0; i < MAX_IOUNITS; i++)
1454
        if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1455
            iounits[i] = iommu_init(hwdef->iounit_bases[i],
1456
                                    hwdef->iounit_version,
1457
                                    sbi_irq[hwdef->me_irq]);
1458

    
1459
    espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1460
                              iounits[0], &espdma_irq, &esp_reset);
1461

    
1462
    ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1463
                             iounits[0], &ledma_irq, &le_reset);
1464

    
1465
    if (graphic_depth != 8 && graphic_depth != 24) {
1466
        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1467
        exit (1);
1468
    }
1469
    tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1470
             hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1471

    
1472
    if (nd_table[0].model == NULL
1473
        || strcmp(nd_table[0].model, "lance") == 0) {
1474
        lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1475
    } else if (strcmp(nd_table[0].model, "?") == 0) {
1476
        fprintf(stderr, "qemu: Supported NICs: lance\n");
1477
        exit (1);
1478
    } else {
1479
        fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1480
        exit (1);
1481
    }
1482

    
1483
    nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1484
                        hwdef->nvram_size, 8);
1485

    
1486
    slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1487
                          sbi_cpu_irq, smp_cpus);
1488

    
1489
    slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1490
                              nographic);
1491
    // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1492
    // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1493
    slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1494
                       serial_hds[1], serial_hds[0]);
1495

    
1496
    if (drive_get_max_bus(IF_SCSI) > 0) {
1497
        fprintf(stderr, "qemu: too many SCSI bus\n");
1498
        exit(1);
1499
    }
1500

    
1501
    main_esp = esp_init(hwdef->esp_base, 2,
1502
                        espdma_memory_read, espdma_memory_write,
1503
                        espdma, *espdma_irq, esp_reset);
1504

    
1505
    for (i = 0; i < ESP_MAX_DEVS; i++) {
1506
        drive_index = drive_get_index(IF_SCSI, 0, i);
1507
        if (drive_index == -1)
1508
            continue;
1509
        esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1510
    }
1511

    
1512
    kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1513
                                    RAM_size);
1514

    
1515
    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1516
               boot_device, RAM_size, kernel_size, graphic_width,
1517
               graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
1518
}
1519

    
1520
/* SPARCserver 1000 hardware initialisation */
1521
static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1522
                        const char *boot_device, DisplayState *ds,
1523
                        const char *kernel_filename, const char *kernel_cmdline,
1524
                        const char *initrd_filename, const char *cpu_model)
1525
{
1526
    sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1527
                  kernel_cmdline, initrd_filename, cpu_model);
1528
}
1529

    
1530
/* SPARCcenter 2000 hardware initialisation */
1531
static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1532
                        const char *boot_device, DisplayState *ds,
1533
                        const char *kernel_filename, const char *kernel_cmdline,
1534
                        const char *initrd_filename, const char *cpu_model)
1535
{
1536
    sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1537
                  kernel_cmdline, initrd_filename, cpu_model);
1538
}
1539

    
1540
QEMUMachine ss1000_machine = {
1541
    "SS-1000",
1542
    "Sun4d platform, SPARCserver 1000",
1543
    ss1000_init,
1544
    PROM_SIZE_MAX + TCX_SIZE,
1545
};
1546

    
1547
QEMUMachine ss2000_machine = {
1548
    "SS-2000",
1549
    "Sun4d platform, SPARCcenter 2000",
1550
    ss2000_init,
1551
    PROM_SIZE_MAX + TCX_SIZE,
1552
};