Statistics
| Branch: | Revision:

root / target-mips / cpu.h @ b3c7724c

History | View | Annotate | Download (16.1 kB)

1
#if !defined (__MIPS_CPU_H__)
2
#define __MIPS_CPU_H__
3

    
4
#define TARGET_HAS_ICE 1
5

    
6
#define ELF_MACHINE        EM_MIPS
7

    
8
#include "config.h"
9
#include "mips-defs.h"
10
#include "cpu-defs.h"
11
#include "softfloat.h"
12

    
13
// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14
// XXX: move that elsewhere
15
#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16
typedef unsigned char           uint_fast8_t;
17
typedef unsigned int            uint_fast16_t;
18
#endif
19

    
20
struct CPUMIPSState;
21

    
22
typedef struct r4k_tlb_t r4k_tlb_t;
23
struct r4k_tlb_t {
24
    target_ulong VPN;
25
    uint32_t PageMask;
26
    uint_fast8_t ASID;
27
    uint_fast16_t G:1;
28
    uint_fast16_t C0:3;
29
    uint_fast16_t C1:3;
30
    uint_fast16_t V0:1;
31
    uint_fast16_t V1:1;
32
    uint_fast16_t D0:1;
33
    uint_fast16_t D1:1;
34
    target_ulong PFN[2];
35
};
36

    
37
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
38
struct CPUMIPSTLBContext {
39
    uint32_t nb_tlb;
40
    uint32_t tlb_in_use;
41
    int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
42
    void (*do_tlbwi) (void);
43
    void (*do_tlbwr) (void);
44
    void (*do_tlbp) (void);
45
    void (*do_tlbr) (void);
46
    union {
47
        struct {
48
            r4k_tlb_t tlb[MIPS_TLB_MAX];
49
        } r4k;
50
    } mmu;
51
};
52

    
53
typedef union fpr_t fpr_t;
54
union fpr_t {
55
    float64  fd;   /* ieee double precision */
56
    float32  fs[2];/* ieee single precision */
57
    uint64_t d;    /* binary double fixed-point */
58
    uint32_t w[2]; /* binary single fixed-point */
59
};
60
/* define FP_ENDIAN_IDX to access the same location
61
 * in the fpr_t union regardless of the host endianess
62
 */
63
#if defined(WORDS_BIGENDIAN)
64
#  define FP_ENDIAN_IDX 1
65
#else
66
#  define FP_ENDIAN_IDX 0
67
#endif
68

    
69
typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70
struct CPUMIPSFPUContext {
71
    /* Floating point registers */
72
    fpr_t fpr[32];
73
    float_status fp_status;
74
    /* fpu implementation/revision register (fir) */
75
    uint32_t fcr0;
76
#define FCR0_F64 22
77
#define FCR0_L 21
78
#define FCR0_W 20
79
#define FCR0_3D 19
80
#define FCR0_PS 18
81
#define FCR0_D 17
82
#define FCR0_S 16
83
#define FCR0_PRID 8
84
#define FCR0_REV 0
85
    /* fcsr */
86
    uint32_t fcr31;
87
#define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
88
#define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89
#define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
90
#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
91
#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
92
#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
93
#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
94
#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
95
#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
96
#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
97
#define FP_INEXACT        1
98
#define FP_UNDERFLOW      2
99
#define FP_OVERFLOW       4
100
#define FP_DIV0           8
101
#define FP_INVALID        16
102
#define FP_UNIMPLEMENTED  32
103
};
104

    
105
#define NB_MMU_MODES 3
106

    
107
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
108
struct CPUMIPSMVPContext {
109
    int32_t CP0_MVPControl;
110
#define CP0MVPCo_CPA        3
111
#define CP0MVPCo_STLB        2
112
#define CP0MVPCo_VPC        1
113
#define CP0MVPCo_EVP        0
114
    int32_t CP0_MVPConf0;
115
#define CP0MVPC0_M        31
116
#define CP0MVPC0_TLBS        29
117
#define CP0MVPC0_GS        28
118
#define CP0MVPC0_PCP        27
119
#define CP0MVPC0_PTLBE        16
120
#define CP0MVPC0_TCA        15
121
#define CP0MVPC0_PVPE        10
122
#define CP0MVPC0_PTC        0
123
    int32_t CP0_MVPConf1;
124
#define CP0MVPC1_CIM        31
125
#define CP0MVPC1_CIF        30
126
#define CP0MVPC1_PCX        20
127
#define CP0MVPC1_PCP2        10
128
#define CP0MVPC1_PCP1        0
129
};
130

    
131
typedef struct mips_def_t mips_def_t;
132

    
133
#define MIPS_SHADOW_SET_MAX 16
134
#define MIPS_TC_MAX 5
135
#define MIPS_DSP_ACC 4
136

    
137
typedef struct TCState TCState;
138
struct TCState {
139
    target_ulong gpr[32];
140
    target_ulong PC;
141
    target_ulong HI[MIPS_DSP_ACC];
142
    target_ulong LO[MIPS_DSP_ACC];
143
    target_ulong ACX[MIPS_DSP_ACC];
144
    target_ulong DSPControl;
145
    int32_t CP0_TCStatus;
146
#define CP0TCSt_TCU3        31
147
#define CP0TCSt_TCU2        30
148
#define CP0TCSt_TCU1        29
149
#define CP0TCSt_TCU0        28
150
#define CP0TCSt_TMX        27
151
#define CP0TCSt_RNST        23
152
#define CP0TCSt_TDS        21
153
#define CP0TCSt_DT        20
154
#define CP0TCSt_DA        15
155
#define CP0TCSt_A        13
156
#define CP0TCSt_TKSU        11
157
#define CP0TCSt_IXMT        10
158
#define CP0TCSt_TASID        0
159
    int32_t CP0_TCBind;
160
#define CP0TCBd_CurTC        21
161
#define CP0TCBd_TBE        17
162
#define CP0TCBd_CurVPE        0
163
    target_ulong CP0_TCHalt;
164
    target_ulong CP0_TCContext;
165
    target_ulong CP0_TCSchedule;
166
    target_ulong CP0_TCScheFBack;
167
    int32_t CP0_Debug_tcstatus;
168
};
169

    
170
typedef struct CPUMIPSState CPUMIPSState;
171
struct CPUMIPSState {
172
    TCState active_tc;
173

    
174
    /* temporary hack for FP globals */
175
#ifndef USE_HOST_FLOAT_REGS
176
    fpr_t ft0;
177
    fpr_t ft1;
178
    fpr_t ft2;
179
#endif
180
    CPUMIPSMVPContext *mvp;
181
    CPUMIPSTLBContext *tlb;
182
    CPUMIPSFPUContext *fpu;
183
    uint32_t current_tc;
184

    
185
    uint32_t SEGBITS;
186
    target_ulong SEGMask;
187
    uint32_t PABITS;
188
    target_ulong PAMask;
189

    
190
    int32_t CP0_Index;
191
    /* CP0_MVP* are per MVP registers. */
192
    int32_t CP0_Random;
193
    int32_t CP0_VPEControl;
194
#define CP0VPECo_YSI        21
195
#define CP0VPECo_GSI        20
196
#define CP0VPECo_EXCPT        16
197
#define CP0VPECo_TE        15
198
#define CP0VPECo_TargTC        0
199
    int32_t CP0_VPEConf0;
200
#define CP0VPEC0_M        31
201
#define CP0VPEC0_XTC        21
202
#define CP0VPEC0_TCS        19
203
#define CP0VPEC0_SCS        18
204
#define CP0VPEC0_DSC        17
205
#define CP0VPEC0_ICS        16
206
#define CP0VPEC0_MVP        1
207
#define CP0VPEC0_VPA        0
208
    int32_t CP0_VPEConf1;
209
#define CP0VPEC1_NCX        20
210
#define CP0VPEC1_NCP2        10
211
#define CP0VPEC1_NCP1        0
212
    target_ulong CP0_YQMask;
213
    target_ulong CP0_VPESchedule;
214
    target_ulong CP0_VPEScheFBack;
215
    int32_t CP0_VPEOpt;
216
#define CP0VPEOpt_IWX7        15
217
#define CP0VPEOpt_IWX6        14
218
#define CP0VPEOpt_IWX5        13
219
#define CP0VPEOpt_IWX4        12
220
#define CP0VPEOpt_IWX3        11
221
#define CP0VPEOpt_IWX2        10
222
#define CP0VPEOpt_IWX1        9
223
#define CP0VPEOpt_IWX0        8
224
#define CP0VPEOpt_DWX7        7
225
#define CP0VPEOpt_DWX6        6
226
#define CP0VPEOpt_DWX5        5
227
#define CP0VPEOpt_DWX4        4
228
#define CP0VPEOpt_DWX3        3
229
#define CP0VPEOpt_DWX2        2
230
#define CP0VPEOpt_DWX1        1
231
#define CP0VPEOpt_DWX0        0
232
    target_ulong CP0_EntryLo0;
233
    target_ulong CP0_EntryLo1;
234
    target_ulong CP0_Context;
235
    int32_t CP0_PageMask;
236
    int32_t CP0_PageGrain;
237
    int32_t CP0_Wired;
238
    int32_t CP0_SRSConf0_rw_bitmask;
239
    int32_t CP0_SRSConf0;
240
#define CP0SRSC0_M        31
241
#define CP0SRSC0_SRS3        20
242
#define CP0SRSC0_SRS2        10
243
#define CP0SRSC0_SRS1        0
244
    int32_t CP0_SRSConf1_rw_bitmask;
245
    int32_t CP0_SRSConf1;
246
#define CP0SRSC1_M        31
247
#define CP0SRSC1_SRS6        20
248
#define CP0SRSC1_SRS5        10
249
#define CP0SRSC1_SRS4        0
250
    int32_t CP0_SRSConf2_rw_bitmask;
251
    int32_t CP0_SRSConf2;
252
#define CP0SRSC2_M        31
253
#define CP0SRSC2_SRS9        20
254
#define CP0SRSC2_SRS8        10
255
#define CP0SRSC2_SRS7        0
256
    int32_t CP0_SRSConf3_rw_bitmask;
257
    int32_t CP0_SRSConf3;
258
#define CP0SRSC3_M        31
259
#define CP0SRSC3_SRS12        20
260
#define CP0SRSC3_SRS11        10
261
#define CP0SRSC3_SRS10        0
262
    int32_t CP0_SRSConf4_rw_bitmask;
263
    int32_t CP0_SRSConf4;
264
#define CP0SRSC4_SRS15        20
265
#define CP0SRSC4_SRS14        10
266
#define CP0SRSC4_SRS13        0
267
    int32_t CP0_HWREna;
268
    target_ulong CP0_BadVAddr;
269
    int32_t CP0_Count;
270
    target_ulong CP0_EntryHi;
271
    int32_t CP0_Compare;
272
    int32_t CP0_Status;
273
#define CP0St_CU3   31
274
#define CP0St_CU2   30
275
#define CP0St_CU1   29
276
#define CP0St_CU0   28
277
#define CP0St_RP    27
278
#define CP0St_FR    26
279
#define CP0St_RE    25
280
#define CP0St_MX    24
281
#define CP0St_PX    23
282
#define CP0St_BEV   22
283
#define CP0St_TS    21
284
#define CP0St_SR    20
285
#define CP0St_NMI   19
286
#define CP0St_IM    8
287
#define CP0St_KX    7
288
#define CP0St_SX    6
289
#define CP0St_UX    5
290
#define CP0St_KSU   3
291
#define CP0St_ERL   2
292
#define CP0St_EXL   1
293
#define CP0St_IE    0
294
    int32_t CP0_IntCtl;
295
#define CP0IntCtl_IPTI 29
296
#define CP0IntCtl_IPPC1 26
297
#define CP0IntCtl_VS 5
298
    int32_t CP0_SRSCtl;
299
#define CP0SRSCtl_HSS 26
300
#define CP0SRSCtl_EICSS 18
301
#define CP0SRSCtl_ESS 12
302
#define CP0SRSCtl_PSS 6
303
#define CP0SRSCtl_CSS 0
304
    int32_t CP0_SRSMap;
305
#define CP0SRSMap_SSV7 28
306
#define CP0SRSMap_SSV6 24
307
#define CP0SRSMap_SSV5 20
308
#define CP0SRSMap_SSV4 16
309
#define CP0SRSMap_SSV3 12
310
#define CP0SRSMap_SSV2 8
311
#define CP0SRSMap_SSV1 4
312
#define CP0SRSMap_SSV0 0
313
    int32_t CP0_Cause;
314
#define CP0Ca_BD   31
315
#define CP0Ca_TI   30
316
#define CP0Ca_CE   28
317
#define CP0Ca_DC   27
318
#define CP0Ca_PCI  26
319
#define CP0Ca_IV   23
320
#define CP0Ca_WP   22
321
#define CP0Ca_IP    8
322
#define CP0Ca_IP_mask 0x0000FF00
323
#define CP0Ca_EC    2
324
    target_ulong CP0_EPC;
325
    int32_t CP0_PRid;
326
    int32_t CP0_EBase;
327
    int32_t CP0_Config0;
328
#define CP0C0_M    31
329
#define CP0C0_K23  28
330
#define CP0C0_KU   25
331
#define CP0C0_MDU  20
332
#define CP0C0_MM   17
333
#define CP0C0_BM   16
334
#define CP0C0_BE   15
335
#define CP0C0_AT   13
336
#define CP0C0_AR   10
337
#define CP0C0_MT   7
338
#define CP0C0_VI   3
339
#define CP0C0_K0   0
340
    int32_t CP0_Config1;
341
#define CP0C1_M    31
342
#define CP0C1_MMU  25
343
#define CP0C1_IS   22
344
#define CP0C1_IL   19
345
#define CP0C1_IA   16
346
#define CP0C1_DS   13
347
#define CP0C1_DL   10
348
#define CP0C1_DA   7
349
#define CP0C1_C2   6
350
#define CP0C1_MD   5
351
#define CP0C1_PC   4
352
#define CP0C1_WR   3
353
#define CP0C1_CA   2
354
#define CP0C1_EP   1
355
#define CP0C1_FP   0
356
    int32_t CP0_Config2;
357
#define CP0C2_M    31
358
#define CP0C2_TU   28
359
#define CP0C2_TS   24
360
#define CP0C2_TL   20
361
#define CP0C2_TA   16
362
#define CP0C2_SU   12
363
#define CP0C2_SS   8
364
#define CP0C2_SL   4
365
#define CP0C2_SA   0
366
    int32_t CP0_Config3;
367
#define CP0C3_M    31
368
#define CP0C3_DSPP 10
369
#define CP0C3_LPA  7
370
#define CP0C3_VEIC 6
371
#define CP0C3_VInt 5
372
#define CP0C3_SP   4
373
#define CP0C3_MT   2
374
#define CP0C3_SM   1
375
#define CP0C3_TL   0
376
    int32_t CP0_Config6;
377
    int32_t CP0_Config7;
378
    /* XXX: Maybe make LLAddr per-TC? */
379
    target_ulong CP0_LLAddr;
380
    target_ulong CP0_WatchLo[8];
381
    int32_t CP0_WatchHi[8];
382
    target_ulong CP0_XContext;
383
    int32_t CP0_Framemask;
384
    int32_t CP0_Debug;
385
#define CP0DB_DBD  31
386
#define CP0DB_DM   30
387
#define CP0DB_LSNM 28
388
#define CP0DB_Doze 27
389
#define CP0DB_Halt 26
390
#define CP0DB_CNT  25
391
#define CP0DB_IBEP 24
392
#define CP0DB_DBEP 21
393
#define CP0DB_IEXI 20
394
#define CP0DB_VER  15
395
#define CP0DB_DEC  10
396
#define CP0DB_SSt  8
397
#define CP0DB_DINT 5
398
#define CP0DB_DIB  4
399
#define CP0DB_DDBS 3
400
#define CP0DB_DDBL 2
401
#define CP0DB_DBp  1
402
#define CP0DB_DSS  0
403
    target_ulong CP0_DEPC;
404
    int32_t CP0_Performance0;
405
    int32_t CP0_TagLo;
406
    int32_t CP0_DataLo;
407
    int32_t CP0_TagHi;
408
    int32_t CP0_DataHi;
409
    target_ulong CP0_ErrorEPC;
410
    int32_t CP0_DESAVE;
411
    /* We waste some space so we can handle shadow registers like TCs. */
412
    TCState tcs[MIPS_SHADOW_SET_MAX];
413
    /* Qemu */
414
    int interrupt_request;
415
    int error_code;
416
    int user_mode_only; /* user mode only simulation */
417
    uint32_t hflags;    /* CPU State */
418
    /* TMASK defines different execution modes */
419
#define MIPS_HFLAG_TMASK  0x01FF
420
#define MIPS_HFLAG_MODE   0x0007 /* execution modes                    */
421
    /* The KSU flags must be the lowest bits in hflags. The flag order
422
       must be the same as defined for CP0 Status. This allows to use
423
       the bits as the value of mmu_idx. */
424
#define MIPS_HFLAG_KSU    0x0003 /* kernel/supervisor/user mode mask   */
425
#define MIPS_HFLAG_UM       0x0002 /* user mode flag */
426
#define MIPS_HFLAG_SM       0x0001 /* supervisor mode flag */
427
#define MIPS_HFLAG_KM       0x0000 /* kernel mode flag */
428
#define MIPS_HFLAG_DM     0x0004 /* Debug mode                         */
429
#define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
430
#define MIPS_HFLAG_CP0    0x0010 /* CP0 enabled                        */
431
#define MIPS_HFLAG_FPU    0x0020 /* FPU enabled                        */
432
#define MIPS_HFLAG_F64    0x0040 /* 64-bit FPU enabled                 */
433
    /* True if the MIPS IV COP1X instructions can be used.  This also
434
       controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
435
       and RSQRT.D.  */
436
#define MIPS_HFLAG_COP1X  0x0080 /* COP1X instructions enabled         */
437
#define MIPS_HFLAG_RE     0x0100 /* Reversed endianness                */
438
    /* If translation is interrupted between the branch instruction and
439
     * the delay slot, record what type of branch it is so that we can
440
     * resume translation properly.  It might be possible to reduce
441
     * this from three bits to two.  */
442
#define MIPS_HFLAG_BMASK  0x0e00
443
#define MIPS_HFLAG_B      0x0200 /* Unconditional branch               */
444
#define MIPS_HFLAG_BC     0x0400 /* Conditional branch                 */
445
#define MIPS_HFLAG_BL     0x0600 /* Likely branch                      */
446
#define MIPS_HFLAG_BR     0x0800 /* branch to register (can't link TB) */
447
    target_ulong btarget;        /* Jump / branch target               */
448
    int bcond;                   /* Branch condition (if needed)       */
449

    
450
    int SYNCI_Step; /* Address step size for SYNCI */
451
    int CCRes; /* Cycle count resolution/divisor */
452
    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
453
    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
454
    int insn_flags; /* Supported instruction set */
455

    
456
#ifdef CONFIG_USER_ONLY
457
    target_ulong tls_value;
458
#endif
459

    
460
    CPU_COMMON
461

    
462
    const mips_def_t *cpu_model;
463
#ifndef CONFIG_USER_ONLY
464
    void *irq[8];
465
#endif
466

    
467
    struct QEMUTimer *timer; /* Internal timer */
468
};
469

    
470
int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
471
                        target_ulong address, int rw, int access_type);
472
int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
473
                           target_ulong address, int rw, int access_type);
474
int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
475
                     target_ulong address, int rw, int access_type);
476
void r4k_do_tlbwi (void);
477
void r4k_do_tlbwr (void);
478
void r4k_do_tlbp (void);
479
void r4k_do_tlbr (void);
480
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
481

    
482
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
483
                          int unused);
484

    
485
#define CPUState CPUMIPSState
486
#define cpu_init cpu_mips_init
487
#define cpu_exec cpu_mips_exec
488
#define cpu_gen_code cpu_mips_gen_code
489
#define cpu_signal_handler cpu_mips_signal_handler
490
#define cpu_list mips_cpu_list
491

    
492
#define CPU_SAVE_VERSION 3
493

    
494
/* MMU modes definitions. We carefully match the indices with our
495
   hflags layout. */
496
#define MMU_MODE0_SUFFIX _kernel
497
#define MMU_MODE1_SUFFIX _super
498
#define MMU_MODE2_SUFFIX _user
499
#define MMU_USER_IDX 2
500
static inline int cpu_mmu_index (CPUState *env)
501
{
502
    return env->hflags & MIPS_HFLAG_KSU;
503
}
504

    
505
#if defined(CONFIG_USER_ONLY)
506
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
507
{
508
    if (newsp)
509
        env->active_tc.gpr[29] = newsp;
510
    env->active_tc.gpr[7] = 0;
511
    env->active_tc.gpr[2] = 0;
512
}
513
#endif
514

    
515
#include "cpu-all.h"
516

    
517
/* Memory access type :
518
 * may be needed for precise access rights control and precise exceptions.
519
 */
520
enum {
521
    /* 1 bit to define user level / supervisor access */
522
    ACCESS_USER  = 0x00,
523
    ACCESS_SUPER = 0x01,
524
    /* 1 bit to indicate direction */
525
    ACCESS_STORE = 0x02,
526
    /* Type of instruction that generated the access */
527
    ACCESS_CODE  = 0x10, /* Code fetch access                */
528
    ACCESS_INT   = 0x20, /* Integer load/store access        */
529
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
530
};
531

    
532
/* Exceptions */
533
enum {
534
    EXCP_NONE          = -1,
535
    EXCP_RESET         = 0,
536
    EXCP_SRESET,
537
    EXCP_DSS,
538
    EXCP_DINT,
539
    EXCP_DDBL,
540
    EXCP_DDBS,
541
    EXCP_NMI,
542
    EXCP_MCHECK,
543
    EXCP_EXT_INTERRUPT, /* 8 */
544
    EXCP_DFWATCH,
545
    EXCP_DIB,
546
    EXCP_IWATCH,
547
    EXCP_AdEL,
548
    EXCP_AdES,
549
    EXCP_TLBF,
550
    EXCP_IBE,
551
    EXCP_DBp, /* 16 */
552
    EXCP_SYSCALL,
553
    EXCP_BREAK,
554
    EXCP_CpU,
555
    EXCP_RI,
556
    EXCP_OVERFLOW,
557
    EXCP_TRAP,
558
    EXCP_FPE,
559
    EXCP_DWATCH, /* 24 */
560
    EXCP_LTLBL,
561
    EXCP_TLBL,
562
    EXCP_TLBS,
563
    EXCP_DBE,
564
    EXCP_THREAD,
565
    EXCP_MDMX,
566
    EXCP_C2E,
567
    EXCP_CACHE, /* 32 */
568

    
569
    EXCP_LAST = EXCP_CACHE,
570
};
571

    
572
int cpu_mips_exec(CPUMIPSState *s);
573
CPUMIPSState *cpu_mips_init(const char *cpu_model);
574
uint32_t cpu_mips_get_clock (void);
575
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
576

    
577
#define CPU_PC_FROM_TB(env, tb) do { \
578
    env->active_tc.PC = tb->pc; \
579
    env->hflags &= ~MIPS_HFLAG_BMASK; \
580
    env->hflags |= tb->flags & MIPS_HFLAG_BMASK; \
581
    } while (0)
582

    
583
#endif /* !defined (__MIPS_CPU_H__) */