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/*
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 *  PowerPC emulation cpu definitions for qemu.
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 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include "config.h"
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#include <inttypes.h>
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//#define PPC_EMULATE_32BITS_HYPV
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#if defined (TARGET_PPC64)
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/* PowerPC 64 definitions */
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typedef uint64_t ppc_gpr_t;
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#define TARGET_LONG_BITS 64
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#define TARGET_PAGE_BITS 12
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#else /* defined (TARGET_PPC64) */
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/* PowerPC 32 definitions */
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#if (HOST_LONG_BITS >= 64)
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/* When using 64 bits temporary registers,
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 * we can use 64 bits GPR with no extra cost
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 * It's even an optimization as this will prevent
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 * the compiler to do unuseful masking in the micro-ops.
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 */
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typedef uint64_t ppc_gpr_t;
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#else /* (HOST_LONG_BITS >= 64) */
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typedef uint32_t ppc_gpr_t;
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#endif /* (HOST_LONG_BITS >= 64) */
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#define TARGET_LONG_BITS 32
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#if defined(TARGET_PPCEMB)
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/* Specific definitions for PowerPC embedded */
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/* BookE have 36 bits physical address space */
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#define TARGET_PHYS_ADDR_BITS 64
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#if defined(CONFIG_USER_ONLY)
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/* It looks like a lot of Linux programs assume page size
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 * is 4kB long. This is evil, but we have to deal with it...
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 */
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#define TARGET_PAGE_BITS 12
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#else /* defined(CONFIG_USER_ONLY) */
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/* Pages can be 1 kB small */
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#define TARGET_PAGE_BITS 10
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#endif /* defined(CONFIG_USER_ONLY) */
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#else /* defined(TARGET_PPCEMB) */
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/* "standard" PowerPC 32 definitions */
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#define TARGET_PAGE_BITS 12
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#endif /* defined(TARGET_PPCEMB) */
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#endif /* defined (TARGET_PPC64) */
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#include "cpu-defs.h"
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#define REGX "%016" PRIx64
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#define ADDRX TARGET_FMT_lx
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#define PADDRX TARGET_FMT_plx
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#include <setjmp.h>
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#if defined (TARGET_PPC64)
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#define ELF_MACHINE     EM_PPC64
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#else
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#define ELF_MACHINE     EM_PPC
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#endif
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/*****************************************************************************/
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/* MMU model                                                                 */
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typedef enum powerpc_mmu_t powerpc_mmu_t;
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enum powerpc_mmu_t {
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    POWERPC_MMU_UNKNOWN    = 0x00000000,
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    /* Standard 32 bits PowerPC MMU                            */
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    POWERPC_MMU_32B        = 0x00000001,
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    /* PowerPC 6xx MMU with software TLB                       */
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    POWERPC_MMU_SOFT_6xx   = 0x00000002,
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    /* PowerPC 74xx MMU with software TLB                      */
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    POWERPC_MMU_SOFT_74xx  = 0x00000003,
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    /* PowerPC 4xx MMU with software TLB                       */
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    POWERPC_MMU_SOFT_4xx   = 0x00000004,
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    /* PowerPC 4xx MMU with software TLB and zones protections */
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    POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
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    /* PowerPC MMU in real mode only                           */
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    POWERPC_MMU_REAL       = 0x00000006,
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    /* Freescale MPC8xx MMU model                              */
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    POWERPC_MMU_MPC8xx     = 0x00000007,
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    /* BookE MMU model                                         */
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    POWERPC_MMU_BOOKE      = 0x00000008,
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    /* BookE FSL MMU model                                     */
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    POWERPC_MMU_BOOKE_FSL  = 0x00000009,
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    /* PowerPC 601 MMU model (specific BATs format)            */
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    POWERPC_MMU_601        = 0x0000000A,
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#if defined(TARGET_PPC64)
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#define POWERPC_MMU_64       0x00010000
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    /* 64 bits PowerPC MMU                                     */
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    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
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    /* 620 variant (no segment exceptions)                     */
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    POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
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/* Exception model                                                           */
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typedef enum powerpc_excp_t powerpc_excp_t;
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enum powerpc_excp_t {
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    POWERPC_EXCP_UNKNOWN   = 0,
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    /* Standard PowerPC exception model */
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    POWERPC_EXCP_STD,
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    /* PowerPC 40x exception model      */
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    POWERPC_EXCP_40x,
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    /* PowerPC 601 exception model      */
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    POWERPC_EXCP_601,
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    /* PowerPC 602 exception model      */
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    POWERPC_EXCP_602,
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    /* PowerPC 603 exception model      */
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    POWERPC_EXCP_603,
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    /* PowerPC 603e exception model     */
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    POWERPC_EXCP_603E,
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    /* PowerPC G2 exception model       */
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    POWERPC_EXCP_G2,
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    /* PowerPC 604 exception model      */
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    POWERPC_EXCP_604,
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    /* PowerPC 7x0 exception model      */
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    POWERPC_EXCP_7x0,
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    /* PowerPC 7x5 exception model      */
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    POWERPC_EXCP_7x5,
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    /* PowerPC 74xx exception model     */
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    POWERPC_EXCP_74xx,
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    /* BookE exception model            */
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    POWERPC_EXCP_BOOKE,
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#if defined(TARGET_PPC64)
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    /* PowerPC 970 exception model      */
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    POWERPC_EXCP_970,
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#endif /* defined(TARGET_PPC64) */
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};
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/*****************************************************************************/
157
/* Exception vectors definitions                                             */
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enum {
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    POWERPC_EXCP_NONE    = -1,
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    /* The 64 first entries are used by the PowerPC embedded specification   */
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    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
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    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
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    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
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    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
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    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
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    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
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    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
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    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
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    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
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    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
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    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
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    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
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    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
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    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
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    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
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    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
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    /* Vectors 16 to 31 are reserved                                         */
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    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
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    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
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    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
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    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
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    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
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    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
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    /* Vectors 38 to 63 are reserved                                         */
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    /* Exceptions defined in the PowerPC server specification                */
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    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
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    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
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    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
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    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
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    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
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    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
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    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
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    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
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    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
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    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
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    /* 40x specific exceptions                                               */
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    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
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    /* 601 specific exceptions                                               */
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    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
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    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
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    /* 602 specific exceptions                                               */
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    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
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    /* 602/603 specific exceptions                                           */
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    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
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    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
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    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
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    /* Exceptions available on most PowerPC                                  */
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    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
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    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
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    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
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    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
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    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
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    /* 7xx/74xx specific exceptions                                          */
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    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
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    /* 74xx specific exceptions                                              */
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    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
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    /* 970FX specific exceptions                                             */
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    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
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    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
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    /* Freescale embeded cores specific exceptions                           */
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    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
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    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
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    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
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    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
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    /* EOL                                                                   */
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    POWERPC_EXCP_NB       = 96,
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    /* Qemu exceptions: used internally during code translation              */
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    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
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    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
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    /* Qemu exceptions: special cases we want to stop translation            */
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    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
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    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
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};
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/* Exceptions error codes                                                    */
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enum {
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    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
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    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
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    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
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    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
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    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
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    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
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    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
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    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
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    /* FP exceptions                                                         */
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    POWERPC_EXCP_FP            = 0x10,
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    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
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    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
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    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
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    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
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    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
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    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
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    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
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    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
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    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
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    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
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    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
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    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
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    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
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    /* Invalid instruction                                                   */
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    POWERPC_EXCP_INVAL         = 0x20,
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    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
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    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
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    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
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    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
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    /* Privileged instruction                                                */
267
    POWERPC_EXCP_PRIV          = 0x30,
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    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
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    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
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    /* Trap                                                                  */
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    POWERPC_EXCP_TRAP          = 0x40,
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};
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/*****************************************************************************/
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/* Input pins model                                                          */
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typedef enum powerpc_input_t powerpc_input_t;
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enum powerpc_input_t {
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    PPC_FLAGS_INPUT_UNKNOWN = 0,
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    /* PowerPC 6xx bus                  */
280
    PPC_FLAGS_INPUT_6xx,
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    /* BookE bus                        */
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    PPC_FLAGS_INPUT_BookE,
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    /* PowerPC 405 bus                  */
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    PPC_FLAGS_INPUT_405,
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    /* PowerPC 970 bus                  */
286
    PPC_FLAGS_INPUT_970,
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    /* PowerPC 401 bus                  */
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    PPC_FLAGS_INPUT_401,
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    /* Freescale RCPU bus               */
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    PPC_FLAGS_INPUT_RCPU,
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};
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293
#define PPC_INPUT(env) (env->bus_model)
294

    
295
/*****************************************************************************/
296
typedef struct ppc_def_t ppc_def_t;
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typedef struct opc_handler_t opc_handler_t;
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299
/*****************************************************************************/
300
/* Types used to describe some PowerPC registers */
301
typedef struct CPUPPCState CPUPPCState;
302
typedef struct ppc_tb_t ppc_tb_t;
303
typedef struct ppc_spr_t ppc_spr_t;
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typedef struct ppc_dcr_t ppc_dcr_t;
305
typedef union ppc_avr_t ppc_avr_t;
306
typedef union ppc_tlb_t ppc_tlb_t;
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/* SPR access micro-ops generations callbacks */
309
struct ppc_spr_t {
310
    void (*uea_read)(void *opaque, int spr_num);
311
    void (*uea_write)(void *opaque, int spr_num);
312
#if !defined(CONFIG_USER_ONLY)
313
    void (*oea_read)(void *opaque, int spr_num);
314
    void (*oea_write)(void *opaque, int spr_num);
315
    void (*hea_read)(void *opaque, int spr_num);
316
    void (*hea_write)(void *opaque, int spr_num);
317
#endif
318
    const unsigned char *name;
319
};
320

    
321
/* Altivec registers (128 bits) */
322
union ppc_avr_t {
323
    uint8_t u8[16];
324
    uint16_t u16[8];
325
    uint32_t u32[4];
326
    uint64_t u64[2];
327
};
328

    
329
/* Software TLB cache */
330
typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
331
struct ppc6xx_tlb_t {
332
    target_ulong pte0;
333
    target_ulong pte1;
334
    target_ulong EPN;
335
};
336

    
337
typedef struct ppcemb_tlb_t ppcemb_tlb_t;
338
struct ppcemb_tlb_t {
339
    target_phys_addr_t RPN;
340
    target_ulong EPN;
341
    target_ulong PID;
342
    target_ulong size;
343
    uint32_t prot;
344
    uint32_t attr; /* Storage attributes */
345
};
346

    
347
union ppc_tlb_t {
348
    ppc6xx_tlb_t tlb6;
349
    ppcemb_tlb_t tlbe;
350
};
351

    
352
/*****************************************************************************/
353
/* Machine state register bits definition                                    */
354
#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
355
#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
356
#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
357
#define MSR_SHV  60 /* hypervisor state                               hflags */
358
#define MSR_CM   31 /* Computation mode for BookE                     hflags */
359
#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
360
#define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
361
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
362
#define MSR_VR   25 /* altivec available                            x hflags */
363
#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
364
#define MSR_AP   23 /* Access privilege state on 602                  hflags */
365
#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
366
#define MSR_KEY  19 /* key bit on 603e                                       */
367
#define MSR_POW  18 /* Power management                                      */
368
#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
369
#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
370
#define MSR_ILE  16 /* Interrupt little-endian mode                          */
371
#define MSR_EE   15 /* External interrupt enable                             */
372
#define MSR_PR   14 /* Problem state                                  hflags */
373
#define MSR_FP   13 /* Floating point available                       hflags */
374
#define MSR_ME   12 /* Machine check interrupt enable                        */
375
#define MSR_FE0  11 /* Floating point exception mode 0                hflags */
376
#define MSR_SE   10 /* Single-step trace enable                     x hflags */
377
#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
378
#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
379
#define MSR_BE   9  /* Branch trace enable                          x hflags */
380
#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
381
#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
382
#define MSR_AL   7  /* AL bit on POWER                                       */
383
#define MSR_EP   6  /* Exception prefix on 601                               */
384
#define MSR_IR   5  /* Instruction relocate                                  */
385
#define MSR_DR   4  /* Data relocate                                         */
386
#define MSR_PE   3  /* Protection enable on 403                              */
387
#define MSR_PX   2  /* Protection exclusive on 403                  x        */
388
#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
389
#define MSR_RI   1  /* Recoverable interrupt                        1        */
390
#define MSR_LE   0  /* Little-endian mode                           1 hflags */
391

    
392
#define msr_sf   ((env->msr >> MSR_SF)   & 1)
393
#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
394
#define msr_shv  ((env->msr >> MSR_SHV)  & 1)
395
#define msr_cm   ((env->msr >> MSR_CM)   & 1)
396
#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
397
#define msr_thv  ((env->msr >> MSR_THV)  & 1)
398
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
399
#define msr_vr   ((env->msr >> MSR_VR)   & 1)
400
#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
401
#define msr_ap   ((env->msr >> MSR_AP)   & 1)
402
#define msr_sa   ((env->msr >> MSR_SA)   & 1)
403
#define msr_key  ((env->msr >> MSR_KEY)  & 1)
404
#define msr_pow  ((env->msr >> MSR_POW)  & 1)
405
#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
406
#define msr_ce   ((env->msr >> MSR_CE)   & 1)
407
#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
408
#define msr_ee   ((env->msr >> MSR_EE)   & 1)
409
#define msr_pr   ((env->msr >> MSR_PR)   & 1)
410
#define msr_fp   ((env->msr >> MSR_FP)   & 1)
411
#define msr_me   ((env->msr >> MSR_ME)   & 1)
412
#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
413
#define msr_se   ((env->msr >> MSR_SE)   & 1)
414
#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
415
#define msr_uble ((env->msr >> MSR_UBLE) & 1)
416
#define msr_be   ((env->msr >> MSR_BE)   & 1)
417
#define msr_de   ((env->msr >> MSR_DE)   & 1)
418
#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
419
#define msr_al   ((env->msr >> MSR_AL)   & 1)
420
#define msr_ep   ((env->msr >> MSR_EP)   & 1)
421
#define msr_ir   ((env->msr >> MSR_IR)   & 1)
422
#define msr_dr   ((env->msr >> MSR_DR)   & 1)
423
#define msr_pe   ((env->msr >> MSR_PE)   & 1)
424
#define msr_px   ((env->msr >> MSR_PX)   & 1)
425
#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
426
#define msr_ri   ((env->msr >> MSR_RI)   & 1)
427
#define msr_le   ((env->msr >> MSR_LE)   & 1)
428
/* Hypervisor bit is more specific */
429
#if defined(TARGET_PPC64)
430
#define MSR_HVB (1ULL << MSR_SHV)
431
#define msr_hv  msr_shv
432
#else
433
#if defined(PPC_EMULATE_32BITS_HYPV)
434
#define MSR_HVB (1ULL << MSR_THV)
435
#define msr_hv  msr_thv
436
#else
437
#define MSR_HVB (0ULL)
438
#define msr_hv  (0)
439
#endif
440
#endif
441

    
442
enum {
443
    POWERPC_FLAG_NONE     = 0x00000000,
444
    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
445
    POWERPC_FLAG_SPE      = 0x00000001,
446
    POWERPC_FLAG_VRE      = 0x00000002,
447
    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
448
    POWERPC_FLAG_TGPR     = 0x00000004,
449
    POWERPC_FLAG_CE       = 0x00000008,
450
    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
451
    POWERPC_FLAG_SE       = 0x00000010,
452
    POWERPC_FLAG_DWE      = 0x00000020,
453
    POWERPC_FLAG_UBLE     = 0x00000040,
454
    /* Flag for MSR bit 9 signification (BE/DE)                              */
455
    POWERPC_FLAG_BE       = 0x00000080,
456
    POWERPC_FLAG_DE       = 0x00000100,
457
    /* Flag for MSR bit 2 signification (PX/PMM)                             */
458
    POWERPC_FLAG_PX       = 0x00000200,
459
    POWERPC_FLAG_PMM      = 0x00000400,
460
    /* Flag for special features                                             */
461
    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
462
    POWERPC_FLAG_RTC_CLK  = 0x00010000,
463
    POWERPC_FLAG_BUS_CLK  = 0x00020000,
464
};
465

    
466
/*****************************************************************************/
467
/* Floating point status and control register                                */
468
#define FPSCR_FX     31 /* Floating-point exception summary                  */
469
#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
470
#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
471
#define FPSCR_OX     28 /* Floating-point overflow exception                 */
472
#define FPSCR_UX     27 /* Floating-point underflow exception                */
473
#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
474
#define FPSCR_XX     25 /* Floating-point inexact exception                  */
475
#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
476
#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
477
#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
478
#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
479
#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
480
#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
481
#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
482
#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
483
#define FPSCR_C      16 /* Floating-point result class descriptor            */
484
#define FPSCR_FL     15 /* Floating-point less than or negative              */
485
#define FPSCR_FG     14 /* Floating-point greater than or negative           */
486
#define FPSCR_FE     13 /* Floating-point equal or zero                      */
487
#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
488
#define FPSCR_FPCC   12 /* Floating-point condition code                     */
489
#define FPSCR_FPRF   12 /* Floating-point result flags                       */
490
#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
491
#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
492
#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
493
#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
494
#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
495
#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
496
#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
497
#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
498
#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
499
#define FPSCR_RN1    1
500
#define FPSCR_RN     0  /* Floating-point rounding control                   */
501
#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
502
#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
503
#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
504
#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
505
#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
506
#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
507
#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
508
#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
509
#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
510
#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
511
#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
512
#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
513
#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
514
#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
515
#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
516
#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
517
#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
518
#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
519
#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
520
#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
521
#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
522
#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
523
#define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
524
/* Invalid operation exception summary */
525
#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
526
                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
527
                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
528
                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
529
                                  (1 << FPSCR_VXCVI)))
530
/* exception summary */
531
#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
532
/* enabled exception summary */
533
#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
534
                   0x1F)
535

    
536
/*****************************************************************************/
537
/* The whole PowerPC CPU context */
538
#define NB_MMU_MODES 3
539

    
540
struct CPUPPCState {
541
    /* First are the most commonly used resources
542
     * during translated code execution
543
     */
544
#if (HOST_LONG_BITS == 32)
545
    /* temporary fixed-point registers
546
     * used to emulate 64 bits registers on 32 bits hosts
547
     */
548
    uint64_t t0, t1, t2;
549
#endif
550
    ppc_avr_t avr0, avr1, avr2;
551

    
552
    /* general purpose registers */
553
    ppc_gpr_t gpr[32];
554
#if !defined(TARGET_PPC64)
555
    /* Storage for GPR MSB, used by the SPE extension */
556
    ppc_gpr_t gprh[32];
557
#endif
558
    /* LR */
559
    target_ulong lr;
560
    /* CTR */
561
    target_ulong ctr;
562
    /* condition register */
563
    uint8_t crf[8];
564
    /* XER */
565
    /* XXX: We use only 5 fields, but we want to keep the structure aligned */
566
    uint8_t xer[8];
567
    /* Reservation address */
568
    target_ulong reserve;
569

    
570
    /* Those ones are used in supervisor mode only */
571
    /* machine state register */
572
    target_ulong msr;
573
    /* temporary general purpose registers */
574
    ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
575

    
576
    /* Floating point execution context */
577
    /* temporary float registers */
578
    float64 ft0;
579
    float64 ft1;
580
    float64 ft2;
581
    float_status fp_status;
582
    /* floating point registers */
583
    float64 fpr[32];
584
    /* floating point status and control register */
585
    uint32_t fpscr;
586

    
587
    CPU_COMMON
588

    
589
    int access_type; /* when a memory exception occurs, the access
590
                        type is stored here */
591

    
592
    /* MMU context - only relevant for full system emulation */
593
#if !defined(CONFIG_USER_ONLY)
594
#if defined(TARGET_PPC64)
595
    /* Address space register */
596
    target_ulong asr;
597
    /* PowerPC 64 SLB area */
598
    int slb_nr;
599
#endif
600
    /* segment registers */
601
    target_ulong sdr1;
602
    target_ulong sr[16];
603
    /* BATs */
604
    int nb_BATs;
605
    target_ulong DBAT[2][8];
606
    target_ulong IBAT[2][8];
607
    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
608
    int nb_tlb;      /* Total number of TLB                                  */
609
    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
610
    int nb_ways;     /* Number of ways in the TLB set                        */
611
    int last_way;    /* Last used way used to allocate TLB in a LRU way      */
612
    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
613
    int nb_pids;     /* Number of available PID registers                    */
614
    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
615
    /* 403 dedicated access protection registers */
616
    target_ulong pb[4];
617
#endif
618

    
619
    /* Other registers */
620
    /* Special purpose registers */
621
    target_ulong spr[1024];
622
    ppc_spr_t spr_cb[1024];
623
    /* Altivec registers */
624
    ppc_avr_t avr[32];
625
    uint32_t vscr;
626
    /* SPE registers */
627
    ppc_gpr_t spe_acc;
628
    float_status spe_status;
629
    uint32_t spe_fscr;
630

    
631
    /* Internal devices resources */
632
    /* Time base and decrementer */
633
    ppc_tb_t *tb_env;
634
    /* Device control registers */
635
    ppc_dcr_t *dcr_env;
636

    
637
    int dcache_line_size;
638
    int icache_line_size;
639

    
640
    /* Those resources are used during exception processing */
641
    /* CPU model definition */
642
    target_ulong msr_mask;
643
    powerpc_mmu_t mmu_model;
644
    powerpc_excp_t excp_model;
645
    powerpc_input_t bus_model;
646
    int bfd_mach;
647
    uint32_t flags;
648

    
649
    int error_code;
650
    int interrupt_request;
651
    uint32_t pending_interrupts;
652
#if !defined(CONFIG_USER_ONLY)
653
    /* This is the IRQ controller, which is implementation dependant
654
     * and only relevant when emulating a complete machine.
655
     */
656
    uint32_t irq_input_state;
657
    void **irq_inputs;
658
    /* Exception vectors */
659
    target_ulong excp_vectors[POWERPC_EXCP_NB];
660
    target_ulong excp_prefix;
661
    target_ulong ivor_mask;
662
    target_ulong ivpr_mask;
663
    target_ulong hreset_vector;
664
#endif
665

    
666
    /* Those resources are used only during code translation */
667
    /* Next instruction pointer */
668
    target_ulong nip;
669

    
670
    /* opcode handlers */
671
    opc_handler_t *opcodes[0x40];
672

    
673
    /* Those resources are used only in Qemu core */
674
    int user_mode_only; /* user mode only simulation */
675
    target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
676
    target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
677
    int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
678

    
679
    /* Power management */
680
    int power_mode;
681
    int (*check_pow)(CPUPPCState *env);
682

    
683
    /* temporary hack to handle OSI calls (only used if non NULL) */
684
    int (*osi_call)(struct CPUPPCState *env);
685
};
686

    
687
/* Context used internally during MMU translations */
688
typedef struct mmu_ctx_t mmu_ctx_t;
689
struct mmu_ctx_t {
690
    target_phys_addr_t raddr;      /* Real address              */
691
    int prot;                      /* Protection bits           */
692
    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
693
    target_ulong ptem;             /* Virtual segment ID | API  */
694
    int key;                       /* Access key                */
695
    int nx;                        /* Non-execute area          */
696
};
697

    
698
/*****************************************************************************/
699
CPUPPCState *cpu_ppc_init (const char *cpu_model);
700
void ppc_translate_init(void);
701
int cpu_ppc_exec (CPUPPCState *s);
702
void cpu_ppc_close (CPUPPCState *s);
703
/* you can call this signal handler from your SIGBUS and SIGSEGV
704
   signal handlers to inform the virtual CPU of exceptions. non zero
705
   is returned if the signal was handled by the virtual CPU.  */
706
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
707
                            void *puc);
708

    
709
void do_interrupt (CPUPPCState *env);
710
void ppc_hw_interrupt (CPUPPCState *env);
711
void cpu_loop_exit (void);
712

    
713
void dump_stack (CPUPPCState *env);
714

    
715
#if !defined(CONFIG_USER_ONLY)
716
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
717
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
718
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
719
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
720
target_ulong do_load_dbatu (CPUPPCState *env, int nr);
721
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
722
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
723
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
724
void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
725
void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
726
target_ulong do_load_sdr1 (CPUPPCState *env);
727
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
728
#if defined(TARGET_PPC64)
729
target_ulong ppc_load_asr (CPUPPCState *env);
730
void ppc_store_asr (CPUPPCState *env, target_ulong value);
731
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
732
void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
733
#endif /* defined(TARGET_PPC64) */
734
#if 0 // Unused
735
target_ulong do_load_sr (CPUPPCState *env, int srnum);
736
#endif
737
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
738
#endif /* !defined(CONFIG_USER_ONLY) */
739
target_ulong ppc_load_xer (CPUPPCState *env);
740
void ppc_store_xer (CPUPPCState *env, target_ulong value);
741
void ppc_store_msr (CPUPPCState *env, target_ulong value);
742

    
743
void cpu_ppc_reset (void *opaque);
744

    
745
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
746

    
747
const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
748
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
749

    
750
/* Time-base and decrementer management */
751
#ifndef NO_CPU_IO_DEFS
752
uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
753
uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
754
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
755
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
756
uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
757
uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
758
void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
759
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
760
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
761
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
762
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
763
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
764
uint64_t cpu_ppc_load_purr (CPUPPCState *env);
765
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
766
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
767
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
768
#if !defined(CONFIG_USER_ONLY)
769
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
770
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
771
target_ulong load_40x_pit (CPUPPCState *env);
772
void store_40x_pit (CPUPPCState *env, target_ulong val);
773
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
774
void store_40x_sler (CPUPPCState *env, uint32_t val);
775
void store_booke_tcr (CPUPPCState *env, target_ulong val);
776
void store_booke_tsr (CPUPPCState *env, target_ulong val);
777
void ppc_tlb_invalidate_all (CPUPPCState *env);
778
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
779
#if defined(TARGET_PPC64)
780
void ppc_slb_invalidate_all (CPUPPCState *env);
781
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
782
#endif
783
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
784
#endif
785
#endif
786

    
787
static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
788
{
789
    uint64_t gprv;
790

    
791
    gprv = env->gpr[gprn];
792
#if !defined(TARGET_PPC64)
793
    if (env->flags & POWERPC_FLAG_SPE) {
794
        /* If the CPU implements the SPE extension, we have to get the
795
         * high bits of the GPR from the gprh storage area
796
         */
797
        gprv &= 0xFFFFFFFFULL;
798
        gprv |= (uint64_t)env->gprh[gprn] << 32;
799
    }
800
#endif
801

    
802
    return gprv;
803
}
804

    
805
/* Device control registers */
806
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
807
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
808

    
809
#define CPUState CPUPPCState
810
#define cpu_init cpu_ppc_init
811
#define cpu_exec cpu_ppc_exec
812
#define cpu_gen_code cpu_ppc_gen_code
813
#define cpu_signal_handler cpu_ppc_signal_handler
814
#define cpu_list ppc_cpu_list
815

    
816
#define CPU_SAVE_VERSION 3
817

    
818
/* MMU modes definitions */
819
#define MMU_MODE0_SUFFIX _user
820
#define MMU_MODE1_SUFFIX _kernel
821
#define MMU_MODE2_SUFFIX _hypv
822
#define MMU_USER_IDX 0
823
static inline int cpu_mmu_index (CPUState *env)
824
{
825
    return env->mmu_idx;
826
}
827

    
828
#if defined(CONFIG_USER_ONLY)
829
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
830
{
831
    int i;
832
    if (newsp)
833
        env->gpr[1] = newsp;
834
    for (i = 7; i < 32; i++)
835
        env->gpr[i] = 0;
836
}
837
#endif
838

    
839
#define CPU_PC_FROM_TB(env, tb) env->nip = tb->pc
840

    
841
#include "cpu-all.h"
842

    
843
/*****************************************************************************/
844
/* Registers definitions */
845
#define XER_SO 31
846
#define XER_OV 30
847
#define XER_CA 29
848
#define XER_CMP 8
849
#define XER_BC  0
850
#define xer_so  env->xer[4]
851
#define xer_ov  env->xer[6]
852
#define xer_ca  env->xer[2]
853
#define xer_cmp env->xer[1]
854
#define xer_bc  env->xer[0]
855

    
856
/* SPR definitions */
857
#define SPR_MQ                (0x000)
858
#define SPR_XER               (0x001)
859
#define SPR_601_VRTCU         (0x004)
860
#define SPR_601_VRTCL         (0x005)
861
#define SPR_601_UDECR         (0x006)
862
#define SPR_LR                (0x008)
863
#define SPR_CTR               (0x009)
864
#define SPR_DSISR             (0x012)
865
#define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
866
#define SPR_601_RTCU          (0x014)
867
#define SPR_601_RTCL          (0x015)
868
#define SPR_DECR              (0x016)
869
#define SPR_SDR1              (0x019)
870
#define SPR_SRR0              (0x01A)
871
#define SPR_SRR1              (0x01B)
872
#define SPR_AMR               (0x01D)
873
#define SPR_BOOKE_PID         (0x030)
874
#define SPR_BOOKE_DECAR       (0x036)
875
#define SPR_BOOKE_CSRR0       (0x03A)
876
#define SPR_BOOKE_CSRR1       (0x03B)
877
#define SPR_BOOKE_DEAR        (0x03D)
878
#define SPR_BOOKE_ESR         (0x03E)
879
#define SPR_BOOKE_IVPR        (0x03F)
880
#define SPR_MPC_EIE           (0x050)
881
#define SPR_MPC_EID           (0x051)
882
#define SPR_MPC_NRI           (0x052)
883
#define SPR_CTRL              (0x088)
884
#define SPR_MPC_CMPA          (0x090)
885
#define SPR_MPC_CMPB          (0x091)
886
#define SPR_MPC_CMPC          (0x092)
887
#define SPR_MPC_CMPD          (0x093)
888
#define SPR_MPC_ECR           (0x094)
889
#define SPR_MPC_DER           (0x095)
890
#define SPR_MPC_COUNTA        (0x096)
891
#define SPR_MPC_COUNTB        (0x097)
892
#define SPR_UCTRL             (0x098)
893
#define SPR_MPC_CMPE          (0x098)
894
#define SPR_MPC_CMPF          (0x099)
895
#define SPR_MPC_CMPG          (0x09A)
896
#define SPR_MPC_CMPH          (0x09B)
897
#define SPR_MPC_LCTRL1        (0x09C)
898
#define SPR_MPC_LCTRL2        (0x09D)
899
#define SPR_MPC_ICTRL         (0x09E)
900
#define SPR_MPC_BAR           (0x09F)
901
#define SPR_VRSAVE            (0x100)
902
#define SPR_USPRG0            (0x100)
903
#define SPR_USPRG1            (0x101)
904
#define SPR_USPRG2            (0x102)
905
#define SPR_USPRG3            (0x103)
906
#define SPR_USPRG4            (0x104)
907
#define SPR_USPRG5            (0x105)
908
#define SPR_USPRG6            (0x106)
909
#define SPR_USPRG7            (0x107)
910
#define SPR_VTBL              (0x10C)
911
#define SPR_VTBU              (0x10D)
912
#define SPR_SPRG0             (0x110)
913
#define SPR_SPRG1             (0x111)
914
#define SPR_SPRG2             (0x112)
915
#define SPR_SPRG3             (0x113)
916
#define SPR_SPRG4             (0x114)
917
#define SPR_SCOMC             (0x114)
918
#define SPR_SPRG5             (0x115)
919
#define SPR_SCOMD             (0x115)
920
#define SPR_SPRG6             (0x116)
921
#define SPR_SPRG7             (0x117)
922
#define SPR_ASR               (0x118)
923
#define SPR_EAR               (0x11A)
924
#define SPR_TBL               (0x11C)
925
#define SPR_TBU               (0x11D)
926
#define SPR_TBU40             (0x11E)
927
#define SPR_SVR               (0x11E)
928
#define SPR_BOOKE_PIR         (0x11E)
929
#define SPR_PVR               (0x11F)
930
#define SPR_HSPRG0            (0x130)
931
#define SPR_BOOKE_DBSR        (0x130)
932
#define SPR_HSPRG1            (0x131)
933
#define SPR_HDSISR            (0x132)
934
#define SPR_HDAR              (0x133)
935
#define SPR_BOOKE_DBCR0       (0x134)
936
#define SPR_IBCR              (0x135)
937
#define SPR_PURR              (0x135)
938
#define SPR_BOOKE_DBCR1       (0x135)
939
#define SPR_DBCR              (0x136)
940
#define SPR_HDEC              (0x136)
941
#define SPR_BOOKE_DBCR2       (0x136)
942
#define SPR_HIOR              (0x137)
943
#define SPR_MBAR              (0x137)
944
#define SPR_RMOR              (0x138)
945
#define SPR_BOOKE_IAC1        (0x138)
946
#define SPR_HRMOR             (0x139)
947
#define SPR_BOOKE_IAC2        (0x139)
948
#define SPR_HSRR0             (0x13A)
949
#define SPR_BOOKE_IAC3        (0x13A)
950
#define SPR_HSRR1             (0x13B)
951
#define SPR_BOOKE_IAC4        (0x13B)
952
#define SPR_LPCR              (0x13C)
953
#define SPR_BOOKE_DAC1        (0x13C)
954
#define SPR_LPIDR             (0x13D)
955
#define SPR_DABR2             (0x13D)
956
#define SPR_BOOKE_DAC2        (0x13D)
957
#define SPR_BOOKE_DVC1        (0x13E)
958
#define SPR_BOOKE_DVC2        (0x13F)
959
#define SPR_BOOKE_TSR         (0x150)
960
#define SPR_BOOKE_TCR         (0x154)
961
#define SPR_BOOKE_IVOR0       (0x190)
962
#define SPR_BOOKE_IVOR1       (0x191)
963
#define SPR_BOOKE_IVOR2       (0x192)
964
#define SPR_BOOKE_IVOR3       (0x193)
965
#define SPR_BOOKE_IVOR4       (0x194)
966
#define SPR_BOOKE_IVOR5       (0x195)
967
#define SPR_BOOKE_IVOR6       (0x196)
968
#define SPR_BOOKE_IVOR7       (0x197)
969
#define SPR_BOOKE_IVOR8       (0x198)
970
#define SPR_BOOKE_IVOR9       (0x199)
971
#define SPR_BOOKE_IVOR10      (0x19A)
972
#define SPR_BOOKE_IVOR11      (0x19B)
973
#define SPR_BOOKE_IVOR12      (0x19C)
974
#define SPR_BOOKE_IVOR13      (0x19D)
975
#define SPR_BOOKE_IVOR14      (0x19E)
976
#define SPR_BOOKE_IVOR15      (0x19F)
977
#define SPR_BOOKE_SPEFSCR     (0x200)
978
#define SPR_Exxx_BBEAR        (0x201)
979
#define SPR_Exxx_BBTAR        (0x202)
980
#define SPR_Exxx_L1CFG0       (0x203)
981
#define SPR_Exxx_NPIDR        (0x205)
982
#define SPR_ATBL              (0x20E)
983
#define SPR_ATBU              (0x20F)
984
#define SPR_IBAT0U            (0x210)
985
#define SPR_BOOKE_IVOR32      (0x210)
986
#define SPR_RCPU_MI_GRA       (0x210)
987
#define SPR_IBAT0L            (0x211)
988
#define SPR_BOOKE_IVOR33      (0x211)
989
#define SPR_IBAT1U            (0x212)
990
#define SPR_BOOKE_IVOR34      (0x212)
991
#define SPR_IBAT1L            (0x213)
992
#define SPR_BOOKE_IVOR35      (0x213)
993
#define SPR_IBAT2U            (0x214)
994
#define SPR_BOOKE_IVOR36      (0x214)
995
#define SPR_IBAT2L            (0x215)
996
#define SPR_BOOKE_IVOR37      (0x215)
997
#define SPR_IBAT3U            (0x216)
998
#define SPR_IBAT3L            (0x217)
999
#define SPR_DBAT0U            (0x218)
1000
#define SPR_RCPU_L2U_GRA      (0x218)
1001
#define SPR_DBAT0L            (0x219)
1002
#define SPR_DBAT1U            (0x21A)
1003
#define SPR_DBAT1L            (0x21B)
1004
#define SPR_DBAT2U            (0x21C)
1005
#define SPR_DBAT2L            (0x21D)
1006
#define SPR_DBAT3U            (0x21E)
1007
#define SPR_DBAT3L            (0x21F)
1008
#define SPR_IBAT4U            (0x230)
1009
#define SPR_RPCU_BBCMCR       (0x230)
1010
#define SPR_MPC_IC_CST        (0x230)
1011
#define SPR_Exxx_CTXCR        (0x230)
1012
#define SPR_IBAT4L            (0x231)
1013
#define SPR_MPC_IC_ADR        (0x231)
1014
#define SPR_Exxx_DBCR3        (0x231)
1015
#define SPR_IBAT5U            (0x232)
1016
#define SPR_MPC_IC_DAT        (0x232)
1017
#define SPR_Exxx_DBCNT        (0x232)
1018
#define SPR_IBAT5L            (0x233)
1019
#define SPR_IBAT6U            (0x234)
1020
#define SPR_IBAT6L            (0x235)
1021
#define SPR_IBAT7U            (0x236)
1022
#define SPR_IBAT7L            (0x237)
1023
#define SPR_DBAT4U            (0x238)
1024
#define SPR_RCPU_L2U_MCR      (0x238)
1025
#define SPR_MPC_DC_CST        (0x238)
1026
#define SPR_Exxx_ALTCTXCR     (0x238)
1027
#define SPR_DBAT4L            (0x239)
1028
#define SPR_MPC_DC_ADR        (0x239)
1029
#define SPR_DBAT5U            (0x23A)
1030
#define SPR_BOOKE_MCSRR0      (0x23A)
1031
#define SPR_MPC_DC_DAT        (0x23A)
1032
#define SPR_DBAT5L            (0x23B)
1033
#define SPR_BOOKE_MCSRR1      (0x23B)
1034
#define SPR_DBAT6U            (0x23C)
1035
#define SPR_BOOKE_MCSR        (0x23C)
1036
#define SPR_DBAT6L            (0x23D)
1037
#define SPR_Exxx_MCAR         (0x23D)
1038
#define SPR_DBAT7U            (0x23E)
1039
#define SPR_BOOKE_DSRR0       (0x23E)
1040
#define SPR_DBAT7L            (0x23F)
1041
#define SPR_BOOKE_DSRR1       (0x23F)
1042
#define SPR_BOOKE_SPRG8       (0x25C)
1043
#define SPR_BOOKE_SPRG9       (0x25D)
1044
#define SPR_BOOKE_MAS0        (0x270)
1045
#define SPR_BOOKE_MAS1        (0x271)
1046
#define SPR_BOOKE_MAS2        (0x272)
1047
#define SPR_BOOKE_MAS3        (0x273)
1048
#define SPR_BOOKE_MAS4        (0x274)
1049
#define SPR_BOOKE_MAS5        (0x275)
1050
#define SPR_BOOKE_MAS6        (0x276)
1051
#define SPR_BOOKE_PID1        (0x279)
1052
#define SPR_BOOKE_PID2        (0x27A)
1053
#define SPR_MPC_DPDR          (0x280)
1054
#define SPR_MPC_IMMR          (0x288)
1055
#define SPR_BOOKE_TLB0CFG     (0x2B0)
1056
#define SPR_BOOKE_TLB1CFG     (0x2B1)
1057
#define SPR_BOOKE_TLB2CFG     (0x2B2)
1058
#define SPR_BOOKE_TLB3CFG     (0x2B3)
1059
#define SPR_BOOKE_EPR         (0x2BE)
1060
#define SPR_PERF0             (0x300)
1061
#define SPR_RCPU_MI_RBA0      (0x300)
1062
#define SPR_MPC_MI_CTR        (0x300)
1063
#define SPR_PERF1             (0x301)
1064
#define SPR_RCPU_MI_RBA1      (0x301)
1065
#define SPR_PERF2             (0x302)
1066
#define SPR_RCPU_MI_RBA2      (0x302)
1067
#define SPR_MPC_MI_AP         (0x302)
1068
#define SPR_PERF3             (0x303)
1069
#define SPR_620_PMC1R         (0x303)
1070
#define SPR_RCPU_MI_RBA3      (0x303)
1071
#define SPR_MPC_MI_EPN        (0x303)
1072
#define SPR_PERF4             (0x304)
1073
#define SPR_620_PMC2R         (0x304)
1074
#define SPR_PERF5             (0x305)
1075
#define SPR_MPC_MI_TWC        (0x305)
1076
#define SPR_PERF6             (0x306)
1077
#define SPR_MPC_MI_RPN        (0x306)
1078
#define SPR_PERF7             (0x307)
1079
#define SPR_PERF8             (0x308)
1080
#define SPR_RCPU_L2U_RBA0     (0x308)
1081
#define SPR_MPC_MD_CTR        (0x308)
1082
#define SPR_PERF9             (0x309)
1083
#define SPR_RCPU_L2U_RBA1     (0x309)
1084
#define SPR_MPC_MD_CASID      (0x309)
1085
#define SPR_PERFA             (0x30A)
1086
#define SPR_RCPU_L2U_RBA2     (0x30A)
1087
#define SPR_MPC_MD_AP         (0x30A)
1088
#define SPR_PERFB             (0x30B)
1089
#define SPR_620_MMCR0R        (0x30B)
1090
#define SPR_RCPU_L2U_RBA3     (0x30B)
1091
#define SPR_MPC_MD_EPN        (0x30B)
1092
#define SPR_PERFC             (0x30C)
1093
#define SPR_MPC_MD_TWB        (0x30C)
1094
#define SPR_PERFD             (0x30D)
1095
#define SPR_MPC_MD_TWC        (0x30D)
1096
#define SPR_PERFE             (0x30E)
1097
#define SPR_MPC_MD_RPN        (0x30E)
1098
#define SPR_PERFF             (0x30F)
1099
#define SPR_MPC_MD_TW         (0x30F)
1100
#define SPR_UPERF0            (0x310)
1101
#define SPR_UPERF1            (0x311)
1102
#define SPR_UPERF2            (0x312)
1103
#define SPR_UPERF3            (0x313)
1104
#define SPR_620_PMC1W         (0x313)
1105
#define SPR_UPERF4            (0x314)
1106
#define SPR_620_PMC2W         (0x314)
1107
#define SPR_UPERF5            (0x315)
1108
#define SPR_UPERF6            (0x316)
1109
#define SPR_UPERF7            (0x317)
1110
#define SPR_UPERF8            (0x318)
1111
#define SPR_UPERF9            (0x319)
1112
#define SPR_UPERFA            (0x31A)
1113
#define SPR_UPERFB            (0x31B)
1114
#define SPR_620_MMCR0W        (0x31B)
1115
#define SPR_UPERFC            (0x31C)
1116
#define SPR_UPERFD            (0x31D)
1117
#define SPR_UPERFE            (0x31E)
1118
#define SPR_UPERFF            (0x31F)
1119
#define SPR_RCPU_MI_RA0       (0x320)
1120
#define SPR_MPC_MI_DBCAM      (0x320)
1121
#define SPR_RCPU_MI_RA1       (0x321)
1122
#define SPR_MPC_MI_DBRAM0     (0x321)
1123
#define SPR_RCPU_MI_RA2       (0x322)
1124
#define SPR_MPC_MI_DBRAM1     (0x322)
1125
#define SPR_RCPU_MI_RA3       (0x323)
1126
#define SPR_RCPU_L2U_RA0      (0x328)
1127
#define SPR_MPC_MD_DBCAM      (0x328)
1128
#define SPR_RCPU_L2U_RA1      (0x329)
1129
#define SPR_MPC_MD_DBRAM0     (0x329)
1130
#define SPR_RCPU_L2U_RA2      (0x32A)
1131
#define SPR_MPC_MD_DBRAM1     (0x32A)
1132
#define SPR_RCPU_L2U_RA3      (0x32B)
1133
#define SPR_440_INV0          (0x370)
1134
#define SPR_440_INV1          (0x371)
1135
#define SPR_440_INV2          (0x372)
1136
#define SPR_440_INV3          (0x373)
1137
#define SPR_440_ITV0          (0x374)
1138
#define SPR_440_ITV1          (0x375)
1139
#define SPR_440_ITV2          (0x376)
1140
#define SPR_440_ITV3          (0x377)
1141
#define SPR_440_CCR1          (0x378)
1142
#define SPR_DCRIPR            (0x37B)
1143
#define SPR_PPR               (0x380)
1144
#define SPR_750_GQR0          (0x390)
1145
#define SPR_440_DNV0          (0x390)
1146
#define SPR_750_GQR1          (0x391)
1147
#define SPR_440_DNV1          (0x391)
1148
#define SPR_750_GQR2          (0x392)
1149
#define SPR_440_DNV2          (0x392)
1150
#define SPR_750_GQR3          (0x393)
1151
#define SPR_440_DNV3          (0x393)
1152
#define SPR_750_GQR4          (0x394)
1153
#define SPR_440_DTV0          (0x394)
1154
#define SPR_750_GQR5          (0x395)
1155
#define SPR_440_DTV1          (0x395)
1156
#define SPR_750_GQR6          (0x396)
1157
#define SPR_440_DTV2          (0x396)
1158
#define SPR_750_GQR7          (0x397)
1159
#define SPR_440_DTV3          (0x397)
1160
#define SPR_750_THRM4         (0x398)
1161
#define SPR_750CL_HID2        (0x398)
1162
#define SPR_440_DVLIM         (0x398)
1163
#define SPR_750_WPAR          (0x399)
1164
#define SPR_440_IVLIM         (0x399)
1165
#define SPR_750_DMAU          (0x39A)
1166
#define SPR_750_DMAL          (0x39B)
1167
#define SPR_440_RSTCFG        (0x39B)
1168
#define SPR_BOOKE_DCDBTRL     (0x39C)
1169
#define SPR_BOOKE_DCDBTRH     (0x39D)
1170
#define SPR_BOOKE_ICDBTRL     (0x39E)
1171
#define SPR_BOOKE_ICDBTRH     (0x39F)
1172
#define SPR_UMMCR2            (0x3A0)
1173
#define SPR_UPMC5             (0x3A1)
1174
#define SPR_UPMC6             (0x3A2)
1175
#define SPR_UBAMR             (0x3A7)
1176
#define SPR_UMMCR0            (0x3A8)
1177
#define SPR_UPMC1             (0x3A9)
1178
#define SPR_UPMC2             (0x3AA)
1179
#define SPR_USIAR             (0x3AB)
1180
#define SPR_UMMCR1            (0x3AC)
1181
#define SPR_UPMC3             (0x3AD)
1182
#define SPR_UPMC4             (0x3AE)
1183
#define SPR_USDA              (0x3AF)
1184
#define SPR_40x_ZPR           (0x3B0)
1185
#define SPR_BOOKE_MAS7        (0x3B0)
1186
#define SPR_620_PMR0          (0x3B0)
1187
#define SPR_MMCR2             (0x3B0)
1188
#define SPR_PMC5              (0x3B1)
1189
#define SPR_40x_PID           (0x3B1)
1190
#define SPR_620_PMR1          (0x3B1)
1191
#define SPR_PMC6              (0x3B2)
1192
#define SPR_440_MMUCR         (0x3B2)
1193
#define SPR_620_PMR2          (0x3B2)
1194
#define SPR_4xx_CCR0          (0x3B3)
1195
#define SPR_BOOKE_EPLC        (0x3B3)
1196
#define SPR_620_PMR3          (0x3B3)
1197
#define SPR_405_IAC3          (0x3B4)
1198
#define SPR_BOOKE_EPSC        (0x3B4)
1199
#define SPR_620_PMR4          (0x3B4)
1200
#define SPR_405_IAC4          (0x3B5)
1201
#define SPR_620_PMR5          (0x3B5)
1202
#define SPR_405_DVC1          (0x3B6)
1203
#define SPR_620_PMR6          (0x3B6)
1204
#define SPR_405_DVC2          (0x3B7)
1205
#define SPR_620_PMR7          (0x3B7)
1206
#define SPR_BAMR              (0x3B7)
1207
#define SPR_MMCR0             (0x3B8)
1208
#define SPR_620_PMR8          (0x3B8)
1209
#define SPR_PMC1              (0x3B9)
1210
#define SPR_40x_SGR           (0x3B9)
1211
#define SPR_620_PMR9          (0x3B9)
1212
#define SPR_PMC2              (0x3BA)
1213
#define SPR_40x_DCWR          (0x3BA)
1214
#define SPR_620_PMRA          (0x3BA)
1215
#define SPR_SIAR              (0x3BB)
1216
#define SPR_405_SLER          (0x3BB)
1217
#define SPR_620_PMRB          (0x3BB)
1218
#define SPR_MMCR1             (0x3BC)
1219
#define SPR_405_SU0R          (0x3BC)
1220
#define SPR_620_PMRC          (0x3BC)
1221
#define SPR_401_SKR           (0x3BC)
1222
#define SPR_PMC3              (0x3BD)
1223
#define SPR_405_DBCR1         (0x3BD)
1224
#define SPR_620_PMRD          (0x3BD)
1225
#define SPR_PMC4              (0x3BE)
1226
#define SPR_620_PMRE          (0x3BE)
1227
#define SPR_SDA               (0x3BF)
1228
#define SPR_620_PMRF          (0x3BF)
1229
#define SPR_403_VTBL          (0x3CC)
1230
#define SPR_403_VTBU          (0x3CD)
1231
#define SPR_DMISS             (0x3D0)
1232
#define SPR_DCMP              (0x3D1)
1233
#define SPR_HASH1             (0x3D2)
1234
#define SPR_HASH2             (0x3D3)
1235
#define SPR_BOOKE_ICDBDR      (0x3D3)
1236
#define SPR_TLBMISS           (0x3D4)
1237
#define SPR_IMISS             (0x3D4)
1238
#define SPR_40x_ESR           (0x3D4)
1239
#define SPR_PTEHI             (0x3D5)
1240
#define SPR_ICMP              (0x3D5)
1241
#define SPR_40x_DEAR          (0x3D5)
1242
#define SPR_PTELO             (0x3D6)
1243
#define SPR_RPA               (0x3D6)
1244
#define SPR_40x_EVPR          (0x3D6)
1245
#define SPR_L3PM              (0x3D7)
1246
#define SPR_403_CDBCR         (0x3D7)
1247
#define SPR_L3ITCR0           (0x3D8)
1248
#define SPR_TCR               (0x3D8)
1249
#define SPR_40x_TSR           (0x3D8)
1250
#define SPR_IBR               (0x3DA)
1251
#define SPR_40x_TCR           (0x3DA)
1252
#define SPR_ESASRR            (0x3DB)
1253
#define SPR_40x_PIT           (0x3DB)
1254
#define SPR_403_TBL           (0x3DC)
1255
#define SPR_403_TBU           (0x3DD)
1256
#define SPR_SEBR              (0x3DE)
1257
#define SPR_40x_SRR2          (0x3DE)
1258
#define SPR_SER               (0x3DF)
1259
#define SPR_40x_SRR3          (0x3DF)
1260
#define SPR_L3OHCR            (0x3E8)
1261
#define SPR_L3ITCR1           (0x3E9)
1262
#define SPR_L3ITCR2           (0x3EA)
1263
#define SPR_L3ITCR3           (0x3EB)
1264
#define SPR_HID0              (0x3F0)
1265
#define SPR_40x_DBSR          (0x3F0)
1266
#define SPR_HID1              (0x3F1)
1267
#define SPR_IABR              (0x3F2)
1268
#define SPR_40x_DBCR0         (0x3F2)
1269
#define SPR_601_HID2          (0x3F2)
1270
#define SPR_Exxx_L1CSR0       (0x3F2)
1271
#define SPR_ICTRL             (0x3F3)
1272
#define SPR_HID2              (0x3F3)
1273
#define SPR_750CL_HID4        (0x3F3)
1274
#define SPR_Exxx_L1CSR1       (0x3F3)
1275
#define SPR_440_DBDR          (0x3F3)
1276
#define SPR_LDSTDB            (0x3F4)
1277
#define SPR_750_TDCL          (0x3F4)
1278
#define SPR_40x_IAC1          (0x3F4)
1279
#define SPR_MMUCSR0           (0x3F4)
1280
#define SPR_DABR              (0x3F5)
1281
#define DABR_MASK (~(target_ulong)0x7)
1282
#define SPR_Exxx_BUCSR        (0x3F5)
1283
#define SPR_40x_IAC2          (0x3F5)
1284
#define SPR_601_HID5          (0x3F5)
1285
#define SPR_40x_DAC1          (0x3F6)
1286
#define SPR_MSSCR0            (0x3F6)
1287
#define SPR_970_HID5          (0x3F6)
1288
#define SPR_MSSSR0            (0x3F7)
1289
#define SPR_MSSCR1            (0x3F7)
1290
#define SPR_DABRX             (0x3F7)
1291
#define SPR_40x_DAC2          (0x3F7)
1292
#define SPR_MMUCFG            (0x3F7)
1293
#define SPR_LDSTCR            (0x3F8)
1294
#define SPR_L2PMCR            (0x3F8)
1295
#define SPR_750FX_HID2        (0x3F8)
1296
#define SPR_620_BUSCSR        (0x3F8)
1297
#define SPR_Exxx_L1FINV0      (0x3F8)
1298
#define SPR_L2CR              (0x3F9)
1299
#define SPR_620_L2CR          (0x3F9)
1300
#define SPR_L3CR              (0x3FA)
1301
#define SPR_750_TDCH          (0x3FA)
1302
#define SPR_IABR2             (0x3FA)
1303
#define SPR_40x_DCCR          (0x3FA)
1304
#define SPR_620_L2SR          (0x3FA)
1305
#define SPR_ICTC              (0x3FB)
1306
#define SPR_40x_ICCR          (0x3FB)
1307
#define SPR_THRM1             (0x3FC)
1308
#define SPR_403_PBL1          (0x3FC)
1309
#define SPR_SP                (0x3FD)
1310
#define SPR_THRM2             (0x3FD)
1311
#define SPR_403_PBU1          (0x3FD)
1312
#define SPR_604_HID13         (0x3FD)
1313
#define SPR_LT                (0x3FE)
1314
#define SPR_THRM3             (0x3FE)
1315
#define SPR_RCPU_FPECR        (0x3FE)
1316
#define SPR_403_PBL2          (0x3FE)
1317
#define SPR_PIR               (0x3FF)
1318
#define SPR_403_PBU2          (0x3FF)
1319
#define SPR_601_HID15         (0x3FF)
1320
#define SPR_604_HID15         (0x3FF)
1321
#define SPR_E500_SVR          (0x3FF)
1322

    
1323
/*****************************************************************************/
1324
/* Memory access type :
1325
 * may be needed for precise access rights control and precise exceptions.
1326
 */
1327
enum {
1328
    /* 1 bit to define user level / supervisor access */
1329
    ACCESS_USER  = 0x00,
1330
    ACCESS_SUPER = 0x01,
1331
    /* Type of instruction that generated the access */
1332
    ACCESS_CODE  = 0x10, /* Code fetch access                */
1333
    ACCESS_INT   = 0x20, /* Integer load/store access        */
1334
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
1335
    ACCESS_RES   = 0x40, /* load/store with reservation      */
1336
    ACCESS_EXT   = 0x50, /* external access                  */
1337
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
1338
};
1339

    
1340
/* Hardware interruption sources:
1341
 * all those exception can be raised simulteaneously
1342
 */
1343
/* Input pins definitions */
1344
enum {
1345
    /* 6xx bus input pins */
1346
    PPC6xx_INPUT_HRESET     = 0,
1347
    PPC6xx_INPUT_SRESET     = 1,
1348
    PPC6xx_INPUT_CKSTP_IN   = 2,
1349
    PPC6xx_INPUT_MCP        = 3,
1350
    PPC6xx_INPUT_SMI        = 4,
1351
    PPC6xx_INPUT_INT        = 5,
1352
    PPC6xx_INPUT_TBEN       = 6,
1353
    PPC6xx_INPUT_WAKEUP     = 7,
1354
    PPC6xx_INPUT_NB,
1355
};
1356

    
1357
enum {
1358
    /* Embedded PowerPC input pins */
1359
    PPCBookE_INPUT_HRESET     = 0,
1360
    PPCBookE_INPUT_SRESET     = 1,
1361
    PPCBookE_INPUT_CKSTP_IN   = 2,
1362
    PPCBookE_INPUT_MCP        = 3,
1363
    PPCBookE_INPUT_SMI        = 4,
1364
    PPCBookE_INPUT_INT        = 5,
1365
    PPCBookE_INPUT_CINT       = 6,
1366
    PPCBookE_INPUT_NB,
1367
};
1368

    
1369
enum {
1370
    /* PowerPC 40x input pins */
1371
    PPC40x_INPUT_RESET_CORE = 0,
1372
    PPC40x_INPUT_RESET_CHIP = 1,
1373
    PPC40x_INPUT_RESET_SYS  = 2,
1374
    PPC40x_INPUT_CINT       = 3,
1375
    PPC40x_INPUT_INT        = 4,
1376
    PPC40x_INPUT_HALT       = 5,
1377
    PPC40x_INPUT_DEBUG      = 6,
1378
    PPC40x_INPUT_NB,
1379
};
1380

    
1381
enum {
1382
    /* RCPU input pins */
1383
    PPCRCPU_INPUT_PORESET   = 0,
1384
    PPCRCPU_INPUT_HRESET    = 1,
1385
    PPCRCPU_INPUT_SRESET    = 2,
1386
    PPCRCPU_INPUT_IRQ0      = 3,
1387
    PPCRCPU_INPUT_IRQ1      = 4,
1388
    PPCRCPU_INPUT_IRQ2      = 5,
1389
    PPCRCPU_INPUT_IRQ3      = 6,
1390
    PPCRCPU_INPUT_IRQ4      = 7,
1391
    PPCRCPU_INPUT_IRQ5      = 8,
1392
    PPCRCPU_INPUT_IRQ6      = 9,
1393
    PPCRCPU_INPUT_IRQ7      = 10,
1394
    PPCRCPU_INPUT_NB,
1395
};
1396

    
1397
#if defined(TARGET_PPC64)
1398
enum {
1399
    /* PowerPC 970 input pins */
1400
    PPC970_INPUT_HRESET     = 0,
1401
    PPC970_INPUT_SRESET     = 1,
1402
    PPC970_INPUT_CKSTP      = 2,
1403
    PPC970_INPUT_TBEN       = 3,
1404
    PPC970_INPUT_MCP        = 4,
1405
    PPC970_INPUT_INT        = 5,
1406
    PPC970_INPUT_THINT      = 6,
1407
    PPC970_INPUT_NB,
1408
};
1409
#endif
1410

    
1411
/* Hardware exceptions definitions */
1412
enum {
1413
    /* External hardware exception sources */
1414
    PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
1415
    PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
1416
    PPC_INTERRUPT_MCK,            /* Machine check exception              */
1417
    PPC_INTERRUPT_EXT,            /* External interrupt                   */
1418
    PPC_INTERRUPT_SMI,            /* System management interrupt          */
1419
    PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
1420
    PPC_INTERRUPT_DEBUG,          /* External debug exception             */
1421
    PPC_INTERRUPT_THERM,          /* Thermal exception                    */
1422
    /* Internal hardware exception sources */
1423
    PPC_INTERRUPT_DECR,           /* Decrementer exception                */
1424
    PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
1425
    PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
1426
    PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
1427
    PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
1428
    PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
1429
    PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
1430
    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
1431
};
1432

    
1433
/*****************************************************************************/
1434

    
1435
#endif /* !defined (__CPU_PPC_H__) */