Archipelago » qemu

static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)

{

    ChannelState *s;

    uint32_t saddr;

    int newreg, channel;

    val &= 0xff;

    saddr = (addr & 3) >> 1;

    channel = (addr & SERIAL_MAXADDR) >> 2;

    switch (saddr) {

    case 0:

	SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff);

	    default:

		break;

	    case 0x40:

		return;

	    case 0x80:

		return;

	    case 0xc0:

		return;

	    }

	    break;

static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)

{

    ChannelState *s;

    uint32_t saddr;

    uint32_t ret;

    saddr = (addr & 3) >> 1;

    channel = (addr & SERIAL_MAXADDR) >> 2;

    switch (saddr) {

    case 0:

	SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]);

    m48t59_write(nvram, start + 1, sum & 0xff);

}

extern int nographic;

static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,

    env->halted = 1;

}

{

    CPUState *env, *envs[MAX_CPUS];

    unsigned int i;

    const sparc_def_t *def;

    qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,

        *espdma_irq, *ledma_irq;

        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);

    /* allocate RAM */

    iommu = iommu_init(hwdef->iommu_base);

    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,

        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);

        exit (1);

    }

             hwdef->vram_size, graphic_width, graphic_height, graphic_depth);

    if (nd_table[0].model == NULL

                                   slavio_irq[hwdef->me_irq]);

    if (hwdef->cs_base != (target_phys_addr_t)-1)

        cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);

}

                              const char *kernel_filename,

                              const char *kernel_cmdline,

                              const char *initrd_filename,

{

    int ret, linux_boot;

    char buf[1024];

    linux_boot = (kernel_filename != NULL);

    cpu_register_physical_memory(PROM_ADDR, 

                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK, 

                                 prom_offset | IO_MEM_ROM);

        }

    }

    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,

               graphic_height, graphic_depth, machine_id);

}

    },

};

                              const char *kernel_filename, const char *kernel_cmdline,

                              const char *initrd_filename, const char *cpu_model,

                              unsigned int machine, int max_ram)

{

        fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",

                (unsigned int)max_ram / (1024 * 1024));

        exit(1);

    }

                      kernel_filename, kernel_cmdline, initrd_filename,

}

/* SPARCstation 5 hardware initialisation */

                       DisplayState *ds, const char **fd_filename, int snapshot,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

{

    if (cpu_model == NULL)

        cpu_model = "Fujitsu MB86904";

                      kernel_cmdline, initrd_filename, cpu_model,

                      0, 0x10000000);

}

/* SPARCstation 10 hardware initialisation */

                            DisplayState *ds, const char **fd_filename, int snapshot,

                            const char *kernel_filename, const char *kernel_cmdline,

                            const char *initrd_filename, const char *cpu_model)

{

    if (cpu_model == NULL)

        cpu_model = "TI SuperSparc II";

                      kernel_cmdline, initrd_filename, cpu_model,

                      1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok

}

    ram_addr_t page, page_min, page_max;

    int y, y_start, dd, ds;

    uint8_t *d, *s;

    if (ts->ds->depth == 0)

	return;