Revision b41a2cd1 hw/serial.c
| b/hw/serial.c | ||
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| 90 | 90 |
#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
| 91 | 91 |
#define UART_LSR_DR 0x01 /* Receiver data ready */ |
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typedef struct SerialState {
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struct SerialState {
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uint8_t divider; |
| 95 | 95 |
uint8_t rbr; /* receive register */ |
| 96 | 96 |
uint8_t ier; |
| ... | ... | |
| 104 | 104 |
it can be reset while reading iir */ |
| 105 | 105 |
int thr_ipending; |
| 106 | 106 |
int irq; |
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} SerialState; |
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int out_fd; |
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}; |
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SerialState serial_ports[1]; |
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void serial_update_irq(void) |
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static void serial_update_irq(SerialState *s) |
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{
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SerialState *s = &serial_ports[0]; |
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if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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s->iir = UART_IIR_RDI; |
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} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
|
| ... | ... | |
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} |
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} |
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void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
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static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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SerialState *s = &serial_ports[0];
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SerialState *s = opaque;
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unsigned char ch; |
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int ret; |
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|
| ... | ... | |
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} else {
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s->thr_ipending = 0; |
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s->lsr &= ~UART_LSR_THRE; |
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serial_update_irq(); |
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serial_update_irq(s);
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ch = val; |
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do {
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ret = write(1, &ch, 1);
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ret = write(s->out_fd, &ch, 1);
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} while (ret != 1); |
| 153 | 150 |
s->thr_ipending = 1; |
| 154 | 151 |
s->lsr |= UART_LSR_THRE; |
| 155 | 152 |
s->lsr |= UART_LSR_TEMT; |
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serial_update_irq(); |
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serial_update_irq(s);
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} |
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break; |
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case 1: |
| ... | ... | |
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s->divider = (s->divider & 0x00ff) | (val << 8); |
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} else {
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s->ier = val; |
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serial_update_irq(); |
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serial_update_irq(s);
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} |
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break; |
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case 2: |
| ... | ... | |
| 183 | 180 |
} |
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} |
| 185 | 182 |
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uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
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static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
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{
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SerialState *s = &serial_ports[0];
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SerialState *s = opaque;
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uint32_t ret; |
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addr &= 7; |
| ... | ... | |
| 197 | 194 |
} else {
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ret = s->rbr; |
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s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
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serial_update_irq(); |
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serial_update_irq(s);
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} |
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break; |
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case 1: |
| ... | ... | |
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/* reset THR pending bit */ |
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if ((ret & 0x7) == UART_IIR_THRI) |
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s->thr_ipending = 0; |
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serial_update_irq(); |
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serial_update_irq(s);
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break; |
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case 3: |
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ret = s->lcr; |
| ... | ... | |
| 244 | 241 |
return ret; |
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} |
| 246 | 243 |
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int serial_can_receive(void)
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int serial_can_receive(SerialState *s)
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{
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SerialState *s = &serial_ports[0]; |
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return !(s->lsr & UART_LSR_DR); |
| 251 | 247 |
} |
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void serial_receive_byte(int ch) |
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void serial_receive_byte(SerialState *s, int ch)
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{
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SerialState *s = &serial_ports[0]; |
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s->rbr = ch; |
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s->lsr |= UART_LSR_DR; |
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serial_update_irq(); |
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serial_update_irq(s);
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} |
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void serial_receive_break(void)
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void serial_receive_break(SerialState *s)
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{
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SerialState *s = &serial_ports[0]; |
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s->rbr = 0; |
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s->lsr |= UART_LSR_BI | UART_LSR_DR; |
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serial_update_irq(); |
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serial_update_irq(s);
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} |
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void serial_init(int base, int irq)
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static int serial_can_receive1(void *opaque)
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{
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SerialState *s = &serial_ports[0]; |
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SerialState *s = opaque; |
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return serial_can_receive(s); |
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} |
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static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
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{
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SerialState *s = opaque; |
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serial_receive_byte(s, buf[0]); |
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} |
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/* If fd is zero, it means that the serial device uses the console */ |
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SerialState *serial_init(int base, int irq, int fd) |
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{
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SerialState *s; |
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s = qemu_mallocz(sizeof(SerialState)); |
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if (!s) |
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return NULL; |
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s->irq = irq; |
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s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
| 277 | 285 |
s->iir = UART_IIR_NO_INT; |
| 278 |
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register_ioport_write(base, 8, serial_ioport_write, 1); |
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register_ioport_read(base, 8, serial_ioport_read, 1); |
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register_ioport_write(base, 8, 1, serial_ioport_write, s); |
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register_ioport_read(base, 8, 1, serial_ioport_read, s); |
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if (fd != 0) {
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add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s); |
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s->out_fd = fd; |
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} else {
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serial_console = s; |
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s->out_fd = 1; |
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} |
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return s; |
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| 281 | 298 |
} |
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