root / hw / serial.c @ b41a2cd1
History | View | Annotate | Download (8 kB)
1 |
/*
|
---|---|
2 |
* QEMU 16450 UART emulation
|
3 |
*
|
4 |
* Copyright (c) 2003-2004 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include <stdlib.h> |
25 |
#include <stdio.h> |
26 |
#include <stdarg.h> |
27 |
#include <string.h> |
28 |
#include <getopt.h> |
29 |
#include <inttypes.h> |
30 |
#include <unistd.h> |
31 |
#include <sys/mman.h> |
32 |
#include <fcntl.h> |
33 |
#include <signal.h> |
34 |
#include <time.h> |
35 |
#include <sys/time.h> |
36 |
#include <malloc.h> |
37 |
#include <termios.h> |
38 |
#include <sys/poll.h> |
39 |
#include <errno.h> |
40 |
#include <sys/wait.h> |
41 |
#include <netinet/in.h> |
42 |
|
43 |
#include "cpu.h" |
44 |
#include "vl.h" |
45 |
|
46 |
//#define DEBUG_SERIAL
|
47 |
|
48 |
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
49 |
|
50 |
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
51 |
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
52 |
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
53 |
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
54 |
|
55 |
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
56 |
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
57 |
|
58 |
#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
59 |
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
60 |
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
61 |
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
62 |
|
63 |
/*
|
64 |
* These are the definitions for the Modem Control Register
|
65 |
*/
|
66 |
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
67 |
#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
68 |
#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
69 |
#define UART_MCR_RTS 0x02 /* RTS complement */ |
70 |
#define UART_MCR_DTR 0x01 /* DTR complement */ |
71 |
|
72 |
/*
|
73 |
* These are the definitions for the Modem Status Register
|
74 |
*/
|
75 |
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
76 |
#define UART_MSR_RI 0x40 /* Ring Indicator */ |
77 |
#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
78 |
#define UART_MSR_CTS 0x10 /* Clear to Send */ |
79 |
#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
80 |
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
81 |
#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
82 |
#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
83 |
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
84 |
|
85 |
#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
86 |
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
87 |
#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
88 |
#define UART_LSR_FE 0x08 /* Frame error indicator */ |
89 |
#define UART_LSR_PE 0x04 /* Parity error indicator */ |
90 |
#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
91 |
#define UART_LSR_DR 0x01 /* Receiver data ready */ |
92 |
|
93 |
struct SerialState {
|
94 |
uint8_t divider; |
95 |
uint8_t rbr; /* receive register */
|
96 |
uint8_t ier; |
97 |
uint8_t iir; /* read only */
|
98 |
uint8_t lcr; |
99 |
uint8_t mcr; |
100 |
uint8_t lsr; /* read only */
|
101 |
uint8_t msr; |
102 |
uint8_t scr; |
103 |
/* NOTE: this hidden state is necessary for tx irq generation as
|
104 |
it can be reset while reading iir */
|
105 |
int thr_ipending;
|
106 |
int irq;
|
107 |
int out_fd;
|
108 |
}; |
109 |
|
110 |
static void serial_update_irq(SerialState *s) |
111 |
{ |
112 |
if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
|
113 |
s->iir = UART_IIR_RDI; |
114 |
} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
115 |
s->iir = UART_IIR_THRI; |
116 |
} else {
|
117 |
s->iir = UART_IIR_NO_INT; |
118 |
} |
119 |
if (s->iir != UART_IIR_NO_INT) {
|
120 |
pic_set_irq(s->irq, 1);
|
121 |
} else {
|
122 |
pic_set_irq(s->irq, 0);
|
123 |
} |
124 |
} |
125 |
|
126 |
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
127 |
{ |
128 |
SerialState *s = opaque; |
129 |
unsigned char ch; |
130 |
int ret;
|
131 |
|
132 |
addr &= 7;
|
133 |
#ifdef DEBUG_SERIAL
|
134 |
printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
|
135 |
#endif
|
136 |
switch(addr) {
|
137 |
default:
|
138 |
case 0: |
139 |
if (s->lcr & UART_LCR_DLAB) {
|
140 |
s->divider = (s->divider & 0xff00) | val;
|
141 |
} else {
|
142 |
s->thr_ipending = 0;
|
143 |
s->lsr &= ~UART_LSR_THRE; |
144 |
serial_update_irq(s); |
145 |
|
146 |
ch = val; |
147 |
do {
|
148 |
ret = write(s->out_fd, &ch, 1);
|
149 |
} while (ret != 1); |
150 |
s->thr_ipending = 1;
|
151 |
s->lsr |= UART_LSR_THRE; |
152 |
s->lsr |= UART_LSR_TEMT; |
153 |
serial_update_irq(s); |
154 |
} |
155 |
break;
|
156 |
case 1: |
157 |
if (s->lcr & UART_LCR_DLAB) {
|
158 |
s->divider = (s->divider & 0x00ff) | (val << 8); |
159 |
} else {
|
160 |
s->ier = val; |
161 |
serial_update_irq(s); |
162 |
} |
163 |
break;
|
164 |
case 2: |
165 |
break;
|
166 |
case 3: |
167 |
s->lcr = val; |
168 |
break;
|
169 |
case 4: |
170 |
s->mcr = val; |
171 |
break;
|
172 |
case 5: |
173 |
break;
|
174 |
case 6: |
175 |
s->msr = val; |
176 |
break;
|
177 |
case 7: |
178 |
s->scr = val; |
179 |
break;
|
180 |
} |
181 |
} |
182 |
|
183 |
static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
184 |
{ |
185 |
SerialState *s = opaque; |
186 |
uint32_t ret; |
187 |
|
188 |
addr &= 7;
|
189 |
switch(addr) {
|
190 |
default:
|
191 |
case 0: |
192 |
if (s->lcr & UART_LCR_DLAB) {
|
193 |
ret = s->divider & 0xff;
|
194 |
} else {
|
195 |
ret = s->rbr; |
196 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
197 |
serial_update_irq(s); |
198 |
} |
199 |
break;
|
200 |
case 1: |
201 |
if (s->lcr & UART_LCR_DLAB) {
|
202 |
ret = (s->divider >> 8) & 0xff; |
203 |
} else {
|
204 |
ret = s->ier; |
205 |
} |
206 |
break;
|
207 |
case 2: |
208 |
ret = s->iir; |
209 |
/* reset THR pending bit */
|
210 |
if ((ret & 0x7) == UART_IIR_THRI) |
211 |
s->thr_ipending = 0;
|
212 |
serial_update_irq(s); |
213 |
break;
|
214 |
case 3: |
215 |
ret = s->lcr; |
216 |
break;
|
217 |
case 4: |
218 |
ret = s->mcr; |
219 |
break;
|
220 |
case 5: |
221 |
ret = s->lsr; |
222 |
break;
|
223 |
case 6: |
224 |
if (s->mcr & UART_MCR_LOOP) {
|
225 |
/* in loopback, the modem output pins are connected to the
|
226 |
inputs */
|
227 |
ret = (s->mcr & 0x0c) << 4; |
228 |
ret |= (s->mcr & 0x02) << 3; |
229 |
ret |= (s->mcr & 0x01) << 5; |
230 |
} else {
|
231 |
ret = s->msr; |
232 |
} |
233 |
break;
|
234 |
case 7: |
235 |
ret = s->scr; |
236 |
break;
|
237 |
} |
238 |
#ifdef DEBUG_SERIAL
|
239 |
printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
240 |
#endif
|
241 |
return ret;
|
242 |
} |
243 |
|
244 |
int serial_can_receive(SerialState *s)
|
245 |
{ |
246 |
return !(s->lsr & UART_LSR_DR);
|
247 |
} |
248 |
|
249 |
void serial_receive_byte(SerialState *s, int ch) |
250 |
{ |
251 |
s->rbr = ch; |
252 |
s->lsr |= UART_LSR_DR; |
253 |
serial_update_irq(s); |
254 |
} |
255 |
|
256 |
void serial_receive_break(SerialState *s)
|
257 |
{ |
258 |
s->rbr = 0;
|
259 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
260 |
serial_update_irq(s); |
261 |
} |
262 |
|
263 |
static int serial_can_receive1(void *opaque) |
264 |
{ |
265 |
SerialState *s = opaque; |
266 |
return serial_can_receive(s);
|
267 |
} |
268 |
|
269 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
270 |
{ |
271 |
SerialState *s = opaque; |
272 |
serial_receive_byte(s, buf[0]);
|
273 |
} |
274 |
|
275 |
/* If fd is zero, it means that the serial device uses the console */
|
276 |
SerialState *serial_init(int base, int irq, int fd) |
277 |
{ |
278 |
SerialState *s; |
279 |
|
280 |
s = qemu_mallocz(sizeof(SerialState));
|
281 |
if (!s)
|
282 |
return NULL; |
283 |
s->irq = irq; |
284 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
285 |
s->iir = UART_IIR_NO_INT; |
286 |
|
287 |
register_ioport_write(base, 8, 1, serial_ioport_write, s); |
288 |
register_ioport_read(base, 8, 1, serial_ioport_read, s); |
289 |
|
290 |
if (fd != 0) { |
291 |
add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s); |
292 |
s->out_fd = fd; |
293 |
} else {
|
294 |
serial_console = s; |
295 |
s->out_fd = 1;
|
296 |
} |
297 |
return s;
|
298 |
} |