root / target-mips / mips-defs.h @ b48cfdff
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| 1 | 6af0bf9c | bellard | #if !defined (__QEMU_MIPS_DEFS_H__)
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| 2 | 6af0bf9c | bellard | #define __QEMU_MIPS_DEFS_H__
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| 3 | 6af0bf9c | bellard | |
| 4 | 6af0bf9c | bellard | /* If we want to use 64 bits host regs... */
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| 5 | 6af0bf9c | bellard | //#define USE_64BITS_REGS
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| 6 | 6af0bf9c | bellard | /* If we want to use host float regs... */
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| 7 | 6af0bf9c | bellard | //#define USE_HOST_FLOAT_REGS
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| 8 | 6af0bf9c | bellard | |
| 9 | 6af0bf9c | bellard | /* real pages are variable size... */
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| 10 | 6af0bf9c | bellard | #define TARGET_PAGE_BITS 12 |
| 11 | 6af0bf9c | bellard | /* Uses MIPS R4Kc TLB model */
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| 12 | 6af0bf9c | bellard | #define MIPS_USES_R4K_TLB
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| 13 | 6af0bf9c | bellard | #define MIPS_TLB_NB 16 |
| 14 | 814b9a47 | ths | #define MIPS_TLB_MAX 128 |
| 15 | 6af0bf9c | bellard | |
| 16 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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| 17 | c570fd16 | ths | #define TARGET_LONG_BITS 64 |
| 18 | c570fd16 | ths | #else
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| 19 | c570fd16 | ths | #define TARGET_LONG_BITS 32 |
| 20 | c570fd16 | ths | #endif
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| 21 | c570fd16 | ths | |
| 22 | b48cfdff | ths | /* Strictly follow the architecture standard: Disallow "special"
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| 23 | b48cfdff | ths | instruction handling for PMON/SPIM, force cycle-dependent
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| 24 | b48cfdff | ths | Count/Compare maintenance. */
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| 25 | b48cfdff | ths | //#define MIPS_STRICT_STANDARD 1
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| 26 | b48cfdff | ths | |
| 27 | 6af0bf9c | bellard | #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |