Revision b48cfdff
| b/target-mips/mips-defs.h | ||
|---|---|---|
| 19 | 19 |
#define TARGET_LONG_BITS 32 |
| 20 | 20 |
#endif |
| 21 | 21 |
|
| 22 |
/* Strictly follow the architecture standard: Disallow "special" |
|
| 23 |
instruction handling for PMON/SPIM, force cycle-dependent |
|
| 24 |
Count/Compare maintenance. */ |
|
| 25 |
//#define MIPS_STRICT_STANDARD 1 |
|
| 26 |
|
|
| 22 | 27 |
#endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |
| b/target-mips/translate.c | ||
|---|---|---|
| 305 | 305 |
}; |
| 306 | 306 |
|
| 307 | 307 |
/* MFMC0 opcodes */ |
| 308 |
#define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5)))
|
|
| 308 |
#define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
|
|
| 309 | 309 |
|
| 310 | 310 |
enum {
|
| 311 | 311 |
OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, |
| ... | ... | |
| 4715 | 4715 |
case OPC_MTLO: /* Move to HI/LO */ |
| 4716 | 4716 |
gen_HILO(ctx, op1, rs); |
| 4717 | 4717 |
break; |
| 4718 |
case OPC_PMON: /* Pmon entry point */ |
|
| 4718 |
case OPC_PMON: /* Pmon entry point, also R4010 selsl */ |
|
| 4719 |
#ifdef MIPS_STRICT_STANDARD |
|
| 4720 |
MIPS_INVAL("PMON / selsl");
|
|
| 4721 |
generate_exception(ctx, EXCP_RI); |
|
| 4722 |
#else |
|
| 4719 | 4723 |
gen_op_pmon(sa); |
| 4724 |
#endif |
|
| 4720 | 4725 |
break; |
| 4721 | 4726 |
case OPC_SYSCALL: |
| 4722 | 4727 |
generate_exception(ctx, EXCP_SYSCALL); |
| ... | ... | |
| 4724 | 4729 |
case OPC_BREAK: |
| 4725 | 4730 |
generate_exception(ctx, EXCP_BREAK); |
| 4726 | 4731 |
break; |
| 4727 |
case OPC_SPIM: /* SPIM ? */ |
|
| 4732 |
case OPC_SPIM: |
|
| 4733 |
#ifdef MIPS_STRICT_STANDARD |
|
| 4734 |
MIPS_INVAL("SPIM");
|
|
| 4735 |
generate_exception(ctx, EXCP_RI); |
|
| 4736 |
#else |
|
| 4728 | 4737 |
/* Implemented as RI exception for now. */ |
| 4729 | 4738 |
MIPS_INVAL("spim (unofficial)");
|
| 4730 | 4739 |
generate_exception(ctx, EXCP_RI); |
| 4740 |
#endif |
|
| 4731 | 4741 |
break; |
| 4732 | 4742 |
case OPC_SYNC: |
| 4733 | 4743 |
/* Treat as a noop. */ |
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