Revision b48d7d69 hw/ppc405_uc.c
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 3051 | 3051 |
/* Universal interrupt controller */ |
| 3052 | 3052 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); |
| 3053 | 3053 |
irqs[PPCUIC_OUTPUT_INT] = |
| 3054 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
|
|
| 3054 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
|
|
| 3055 | 3055 |
irqs[PPCUIC_OUTPUT_CINT] = |
| 3056 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
|
|
| 3056 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
|
|
| 3057 | 3057 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
| 3058 | 3058 |
*picp = pic; |
| 3059 | 3059 |
/* SDRAM controller */ |
| ... | ... | |
| 3404 | 3404 |
/* Universal interrupt controller */ |
| 3405 | 3405 |
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); |
| 3406 | 3406 |
irqs[PPCUIC_OUTPUT_INT] = |
| 3407 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
|
|
| 3407 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
|
|
| 3408 | 3408 |
irqs[PPCUIC_OUTPUT_CINT] = |
| 3409 |
((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
|
|
| 3409 |
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
|
|
| 3410 | 3410 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
| 3411 | 3411 |
*picp = pic; |
| 3412 | 3412 |
/* SDRAM controller */ |
Also available in: Unified diff