Revision b4ab4b4e target-mips/helper.c
| b/target-mips/helper.c | ||
|---|---|---|
| 77 | 77 |
int *prot, target_ulong address, |
| 78 | 78 |
int rw, int access_type) |
| 79 | 79 |
{
|
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/* User mode can only access useg */ |
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/* User mode can only access useg/xuseg */
|
|
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
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#ifdef TARGET_MIPS64 |
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
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#endif |
|
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int ret = TLBRET_MATCH; |
| 83 | 88 |
|
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#if 0 |
| ... | ... | |
| 87 | 92 |
user_mode, env->hflags); |
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} |
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#endif |
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|
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#ifdef TARGET_MIPS64 |
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if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL) |
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return TLBRET_BADADDR; |
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#else |
|
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if (user_mode && address > 0x7FFFFFFFUL) |
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return TLBRET_BADADDR; |
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if (address < (int32_t)0x80000000UL) {
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if (!(env->CP0_Status & (1 << CP0St_ERL))) {
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#endif |
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|
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if (address <= (int32_t)0x7FFFFFFFUL) {
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/* useg */ |
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if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) {
|
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#ifdef MIPS_USES_R4K_TLB |
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ret = map_address(env, physical, prot, address, rw, access_type); |
| 96 | 109 |
#else |
| ... | ... | |
| 101 | 114 |
*physical = address; |
| 102 | 115 |
*prot = PAGE_READ | PAGE_WRITE; |
| 103 | 116 |
} |
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#ifdef TARGET_MIPS64 |
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/* |
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XXX: Assuming : |
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- PABITS = 36 (correct for MIPS64R1) |
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- SEGBITS = 40 |
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*/ |
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} else if (address < 0x3FFFFFFFFFFFFFFFULL) {
|
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/* xuseg */ |
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if (UX && address < 0x000000FFFFFFFFFFULL) {
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ret = map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < 0x7FFFFFFFFFFFFFFFULL) {
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/* xsseg */ |
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if (SX && address < 0x400000FFFFFFFFFFULL) {
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ret = map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < 0xBFFFFFFFFFFFFFFFULL) {
|
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/* xkphys */ |
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/* XXX: check supervisor mode */ |
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if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) |
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{
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*physical = address & 0X000000FFFFFFFFFFULL; |
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*prot = PAGE_READ | PAGE_WRITE; |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < 0xFFFFFFFF7FFFFFFFULL) {
|
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/* xkseg */ |
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/* XXX: check supervisor mode */ |
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if (KX && address < 0xC00000FF7FFFFFFFULL) {
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ret = map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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#endif |
|
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} else if (address < (int32_t)0xA0000000UL) {
|
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/* kseg0 */ |
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/* XXX: check supervisor mode */ |
| ... | ... | |
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#ifdef MIPS_USES_R4K_TLB |
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ret = map_address(env, physical, prot, address, rw, access_type); |
| 118 | 170 |
#else |
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*physical = address; |
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*physical = address & 0xFFFFFFFF;
|
|
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*prot = PAGE_READ | PAGE_WRITE; |
| 121 | 173 |
#endif |
| 122 | 174 |
} else {
|
| ... | ... | |
| 126 | 178 |
#ifdef MIPS_USES_R4K_TLB |
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ret = map_address(env, physical, prot, address, rw, access_type); |
| 128 | 180 |
#else |
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*physical = address; |
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*physical = address & 0xFFFFFFFF;
|
|
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*prot = PAGE_READ | PAGE_WRITE; |
| 131 | 183 |
#endif |
| 132 | 184 |
} |
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