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/*
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| 2 |
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* TI OMAP processors emulation.
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*
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "hw.h"
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#include "arm-misc.h"
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#include "omap.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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/* We use pc-style serial ports. */
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| 27 |
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#include "pc.h"
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| 28 |
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| 29 |
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/* Should signal the TCMI */
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| 30 |
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uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
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| 31 |
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{
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uint8_t ret;
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OMAP_8B_REG(addr);
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cpu_physical_memory_read(addr, (void *) &ret, 1);
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| 36 |
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return ret;
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| 37 |
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}
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| 39 |
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void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
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| 40 |
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uint32_t value)
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| 41 |
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{
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| 42 |
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uint8_t val8 = value;
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| 44 |
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OMAP_8B_REG(addr);
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cpu_physical_memory_write(addr, (void *) &val8, 1);
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| 46 |
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}
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| 47 |
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| 48 |
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uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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| 49 |
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{
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uint16_t ret;
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OMAP_16B_REG(addr);
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cpu_physical_memory_read(addr, (void *) &ret, 2);
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return ret;
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| 55 |
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}
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| 56 |
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| 57 |
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void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
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| 58 |
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uint32_t value)
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| 59 |
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{
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| 60 |
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uint16_t val16 = value;
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OMAP_16B_REG(addr);
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cpu_physical_memory_write(addr, (void *) &val16, 2);
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| 64 |
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}
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| 65 |
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uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret;
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OMAP_32B_REG(addr);
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cpu_physical_memory_read(addr, (void *) &ret, 4);
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return ret;
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}
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void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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| 77 |
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{
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OMAP_32B_REG(addr);
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cpu_physical_memory_write(addr, (void *) &value, 4);
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}
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/* Interrupt Handlers */
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struct omap_intr_handler_bank_s {
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uint32_t irqs;
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uint32_t inputs;
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uint32_t mask;
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uint32_t fiq;
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uint32_t sens_edge;
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unsigned char priority[32];
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};
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struct omap_intr_handler_s {
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qemu_irq *pins;
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qemu_irq parent_intr[2];
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target_phys_addr_t base;
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unsigned char nbanks;
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/* state */
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uint32_t new_agr[2];
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int sir_intr[2];
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struct omap_intr_handler_bank_s banks[];
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};
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static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
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{
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int i, j, sir_intr, p_intr, p, f;
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uint32_t level;
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sir_intr = 0;
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p_intr = 255;
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/* Find the interrupt line with the highest dynamic priority.
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* Note: 0 denotes the hightest priority.
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* If all interrupts have the same priority, the default order is IRQ_N,
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* IRQ_N-1,...,IRQ_0. */
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for (j = 0; j < s->nbanks; ++j) {
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level = s->banks[j].irqs & ~s->banks[j].mask &
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(is_fiq ? s->banks[j].fiq : ~s->banks[j].fiq);
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for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
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level >>= f) {
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p = s->banks[j].priority[i];
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if (p <= p_intr) {
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p_intr = p;
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sir_intr = 32 * j + i;
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}
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f = ffs(level >> 1);
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}
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}
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s->sir_intr[is_fiq] = sir_intr;
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}
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static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
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{
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int i;
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uint32_t has_intr = 0;
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for (i = 0; i < s->nbanks; ++i)
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has_intr |= s->banks[i].irqs & ~s->banks[i].mask &
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(is_fiq ? s->banks[i].fiq : ~s->banks[i].fiq);
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if (s->new_agr[is_fiq] && has_intr) {
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s->new_agr[is_fiq] = 0;
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omap_inth_sir_update(s, is_fiq);
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qemu_set_irq(s->parent_intr[is_fiq], 1);
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| 144 |
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}
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| 145 |
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}
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#define INT_FALLING_EDGE 0
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#define INT_LOW_LEVEL 1
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static void omap_set_intr(void *opaque, int irq, int req)
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| 151 |
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{
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struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
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uint32_t rise;
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| 154 |
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struct omap_intr_handler_bank_s *bank = &ih->banks[irq >> 5];
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int n = irq & 31;
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| 157 |
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| 158 |
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if (req) {
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| 159 |
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rise = ~bank->irqs & (1 << n);
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| 160 |
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if (~bank->sens_edge & (1 << n))
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rise &= ~bank->inputs & (1 << n);
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| 162 |
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bank->inputs |= (1 << n);
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| 164 |
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if (rise) {
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| 165 |
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bank->irqs |= rise;
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omap_inth_update(ih, 0);
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omap_inth_update(ih, 1);
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| 168 |
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}
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} else {
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rise = bank->sens_edge & bank->irqs & (1 << n);
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bank->irqs &= ~rise;
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bank->inputs &= ~(1 << n);
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}
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}
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static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
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| 177 |
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{
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
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int i, offset = addr - s->base;
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int bank_no = offset >> 8;
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int line_no;
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struct omap_intr_handler_bank_s *bank = &s->banks[bank_no];
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offset &= 0xff;
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switch (offset) {
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case 0x00: /* ITR */
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return bank->irqs;
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case 0x04: /* MIR */
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return bank->mask;
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case 0x10: /* SIR_IRQ_CODE */
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case 0x14: /* SIR_FIQ_CODE */
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if (bank_no != 0)
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break;
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line_no = s->sir_intr[(offset - 0x10) >> 2];
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bank = &s->banks[line_no >> 5];
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i = line_no & 31;
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if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
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bank->irqs &= ~(1 << i);
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return line_no;
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|
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case 0x18: /* CONTROL_REG */
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if (bank_no != 0)
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break;
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return 0;
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| 207 |
|
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| 208 |
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case 0x1c: /* ILR0 */
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| 209 |
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case 0x20: /* ILR1 */
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| 210 |
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case 0x24: /* ILR2 */
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| 211 |
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case 0x28: /* ILR3 */
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| 212 |
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case 0x2c: /* ILR4 */
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| 213 |
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case 0x30: /* ILR5 */
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| 214 |
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case 0x34: /* ILR6 */
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case 0x38: /* ILR7 */
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| 216 |
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case 0x3c: /* ILR8 */
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| 217 |
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case 0x40: /* ILR9 */
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| 218 |
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case 0x44: /* ILR10 */
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| 219 |
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case 0x48: /* ILR11 */
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| 220 |
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case 0x4c: /* ILR12 */
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| 221 |
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case 0x50: /* ILR13 */
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| 222 |
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case 0x54: /* ILR14 */
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| 223 |
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case 0x58: /* ILR15 */
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| 224 |
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case 0x5c: /* ILR16 */
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| 225 |
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case 0x60: /* ILR17 */
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| 226 |
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case 0x64: /* ILR18 */
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| 227 |
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case 0x68: /* ILR19 */
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| 228 |
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case 0x6c: /* ILR20 */
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| 229 |
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case 0x70: /* ILR21 */
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| 230 |
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case 0x74: /* ILR22 */
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| 231 |
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case 0x78: /* ILR23 */
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| 232 |
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case 0x7c: /* ILR24 */
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| 233 |
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case 0x80: /* ILR25 */
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| 234 |
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case 0x84: /* ILR26 */
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| 235 |
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case 0x88: /* ILR27 */
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| 236 |
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case 0x8c: /* ILR28 */
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| 237 |
|
case 0x90: /* ILR29 */
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| 238 |
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case 0x94: /* ILR30 */
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| 239 |
|
case 0x98: /* ILR31 */
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| 240 |
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i = (offset - 0x1c) >> 2;
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| 241 |
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return (bank->priority[i] << 2) |
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| 242 |
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(((bank->sens_edge >> i) & 1) << 1) |
|
| 243 |
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((bank->fiq >> i) & 1);
|
| 244 |
|
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| 245 |
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case 0x9c: /* ISR */
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| 246 |
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return 0x00000000;
|
| 247 |
|
|
| 248 |
|
}
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| 249 |
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OMAP_BAD_REG(addr);
|
| 250 |
|
return 0;
|
| 251 |
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}
|
| 252 |
|
|
| 253 |
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static void omap_inth_write(void *opaque, target_phys_addr_t addr,
|
| 254 |
|
uint32_t value)
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| 255 |
|
{
|
| 256 |
|
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
|
| 257 |
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int i, offset = addr - s->base;
|
| 258 |
|
int bank_no = offset >> 8;
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| 259 |
|
struct omap_intr_handler_bank_s *bank = &s->banks[bank_no];
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| 260 |
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offset &= 0xff;
|
| 261 |
|
|
| 262 |
|
switch (offset) {
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| 263 |
|
case 0x00: /* ITR */
|
| 264 |
|
/* Important: ignore the clearing if the IRQ is level-triggered and
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| 265 |
|
the input bit is 1 */
|
| 266 |
|
bank->irqs &= value | (bank->inputs & bank->sens_edge);
|
| 267 |
|
return;
|
| 268 |
|
|
| 269 |
|
case 0x04: /* MIR */
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| 270 |
|
bank->mask = value;
|
| 271 |
|
omap_inth_update(s, 0);
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| 272 |
|
omap_inth_update(s, 1);
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| 273 |
|
return;
|
| 274 |
|
|
| 275 |
|
case 0x10: /* SIR_IRQ_CODE */
|
| 276 |
|
case 0x14: /* SIR_FIQ_CODE */
|
| 277 |
|
OMAP_RO_REG(addr);
|
| 278 |
|
break;
|
| 279 |
|
|
| 280 |
|
case 0x18: /* CONTROL_REG */
|
| 281 |
|
if (bank_no != 0)
|
| 282 |
|
break;
|
| 283 |
|
if (value & 2) {
|
| 284 |
|
qemu_set_irq(s->parent_intr[1], 0);
|
| 285 |
|
s->new_agr[1] = ~0;
|
| 286 |
|
omap_inth_update(s, 1);
|
| 287 |
|
}
|
| 288 |
|
if (value & 1) {
|
| 289 |
|
qemu_set_irq(s->parent_intr[0], 0);
|
| 290 |
|
s->new_agr[0] = ~0;
|
| 291 |
|
omap_inth_update(s, 0);
|
| 292 |
|
}
|
| 293 |
|
return;
|
| 294 |
|
|
| 295 |
|
case 0x1c: /* ILR0 */
|
| 296 |
|
case 0x20: /* ILR1 */
|
| 297 |
|
case 0x24: /* ILR2 */
|
| 298 |
|
case 0x28: /* ILR3 */
|
| 299 |
|
case 0x2c: /* ILR4 */
|
| 300 |
|
case 0x30: /* ILR5 */
|
| 301 |
|
case 0x34: /* ILR6 */
|
| 302 |
|
case 0x38: /* ILR7 */
|
| 303 |
|
case 0x3c: /* ILR8 */
|
| 304 |
|
case 0x40: /* ILR9 */
|
| 305 |
|
case 0x44: /* ILR10 */
|
| 306 |
|
case 0x48: /* ILR11 */
|
| 307 |
|
case 0x4c: /* ILR12 */
|
| 308 |
|
case 0x50: /* ILR13 */
|
| 309 |
|
case 0x54: /* ILR14 */
|
| 310 |
|
case 0x58: /* ILR15 */
|
| 311 |
|
case 0x5c: /* ILR16 */
|
| 312 |
|
case 0x60: /* ILR17 */
|
| 313 |
|
case 0x64: /* ILR18 */
|
| 314 |
|
case 0x68: /* ILR19 */
|
| 315 |
|
case 0x6c: /* ILR20 */
|
| 316 |
|
case 0x70: /* ILR21 */
|
| 317 |
|
case 0x74: /* ILR22 */
|
| 318 |
|
case 0x78: /* ILR23 */
|
| 319 |
|
case 0x7c: /* ILR24 */
|
| 320 |
|
case 0x80: /* ILR25 */
|
| 321 |
|
case 0x84: /* ILR26 */
|
| 322 |
|
case 0x88: /* ILR27 */
|
| 323 |
|
case 0x8c: /* ILR28 */
|
| 324 |
|
case 0x90: /* ILR29 */
|
| 325 |
|
case 0x94: /* ILR30 */
|
| 326 |
|
case 0x98: /* ILR31 */
|
| 327 |
|
i = (offset - 0x1c) >> 2;
|
| 328 |
|
bank->priority[i] = (value >> 2) & 0x1f;
|
| 329 |
|
bank->sens_edge &= ~(1 << i);
|
| 330 |
|
bank->sens_edge |= ((value >> 1) & 1) << i;
|
| 331 |
|
bank->fiq &= ~(1 << i);
|
| 332 |
|
bank->fiq |= (value & 1) << i;
|
| 333 |
|
return;
|
| 334 |
|
|
| 335 |
|
case 0x9c: /* ISR */
|
| 336 |
|
for (i = 0; i < 32; i ++)
|
| 337 |
|
if (value & (1 << i)) {
|
| 338 |
|
omap_set_intr(s, 32 * bank_no + i, 1);
|
| 339 |
|
return;
|
| 340 |
|
}
|
| 341 |
|
return;
|
| 342 |
|
}
|
| 343 |
|
OMAP_BAD_REG(addr);
|
| 344 |
|
}
|
| 345 |
|
|
| 346 |
|
static CPUReadMemoryFunc *omap_inth_readfn[] = {
|
| 347 |
|
omap_badwidth_read32,
|
| 348 |
|
omap_badwidth_read32,
|
| 349 |
|
omap_inth_read,
|
| 350 |
|
};
|
| 351 |
|
|
| 352 |
|
static CPUWriteMemoryFunc *omap_inth_writefn[] = {
|
| 353 |
|
omap_inth_write,
|
| 354 |
|
omap_inth_write,
|
| 355 |
|
omap_inth_write,
|
| 356 |
|
};
|
| 357 |
|
|
| 358 |
|
void omap_inth_reset(struct omap_intr_handler_s *s)
|
| 359 |
|
{
|
| 360 |
|
int i;
|
| 361 |
|
|
| 362 |
|
for (i = 0; i < s->nbanks; ++i){
|
| 363 |
|
s->banks[i].irqs = 0x00000000;
|
| 364 |
|
s->banks[i].mask = 0xffffffff;
|
| 365 |
|
s->banks[i].sens_edge = 0x00000000;
|
| 366 |
|
s->banks[i].fiq = 0x00000000;
|
| 367 |
|
s->banks[i].inputs = 0x00000000;
|
| 368 |
|
memset(s->banks[i].priority, 0, sizeof(s->banks[i].priority));
|
| 369 |
|
}
|
| 370 |
|
|
| 371 |
|
s->new_agr[0] = ~0;
|
| 372 |
|
s->new_agr[1] = ~0;
|
| 373 |
|
s->sir_intr[0] = 0;
|
| 374 |
|
s->sir_intr[1] = 0;
|
| 375 |
|
|
| 376 |
|
qemu_set_irq(s->parent_intr[0], 0);
|
| 377 |
|
qemu_set_irq(s->parent_intr[1], 0);
|
| 378 |
|
}
|
| 379 |
|
|
| 380 |
|
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
| 381 |
|
unsigned long size, unsigned char nbanks,
|
| 382 |
|
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
|
| 383 |
|
{
|
| 384 |
|
int iomemtype;
|
| 385 |
|
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
|
| 386 |
|
qemu_mallocz(sizeof(struct omap_intr_handler_s) +
|
| 387 |
|
sizeof(struct omap_intr_handler_bank_s) * nbanks);
|
| 388 |
|
|
| 389 |
|
s->parent_intr[0] = parent_irq;
|
| 390 |
|
s->parent_intr[1] = parent_fiq;
|
| 391 |
|
s->base = base;
|
| 392 |
|
s->nbanks = nbanks;
|
| 393 |
|
s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
|
| 394 |
|
|
| 395 |
|
omap_inth_reset(s);
|
| 396 |
|
|
| 397 |
|
iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
|
| 398 |
|
omap_inth_writefn, s);
|
| 399 |
|
cpu_register_physical_memory(s->base, size, iomemtype);
|
| 400 |
|
|
| 401 |
|
return s;
|
| 402 |
|
}
|
| 403 |
|
|
| 404 |
|
/* OMAP1 DMA module */
|
| 405 |
|
struct omap_dma_channel_s {
|
| 406 |
|
/* transfer data */
|
| 407 |
|
int burst[2];
|
| 408 |
|
int pack[2];
|
| 409 |
|
enum omap_dma_port port[2];
|
| 410 |
|
target_phys_addr_t addr[2];
|
| 411 |
|
omap_dma_addressing_t mode[2];
|
| 412 |
|
uint16_t elements;
|
| 413 |
|
uint16_t frames;
|
| 414 |
|
int16_t frame_index[2];
|
| 415 |
|
int16_t element_index[2];
|
| 416 |
|
int data_type;
|
| 417 |
|
|
| 418 |
|
/* transfer type */
|
| 419 |
|
int transparent_copy;
|
| 420 |
|
int constant_fill;
|
| 421 |
|
uint32_t color;
|
| 422 |
|
|
| 423 |
|
/* auto init and linked channel data */
|
| 424 |
|
int end_prog;
|
| 425 |
|
int repeat;
|
| 426 |
|
int auto_init;
|
| 427 |
|
int link_enabled;
|
| 428 |
|
int link_next_ch;
|
| 429 |
|
|
| 430 |
|
/* interruption data */
|
| 431 |
|
int interrupts;
|
| 432 |
|
int status;
|
| 433 |
|
|
| 434 |
|
/* state data */
|
| 435 |
|
int active;
|
| 436 |
|
int enable;
|
| 437 |
|
int sync;
|
| 438 |
|
int pending_request;
|
| 439 |
|
int waiting_end_prog;
|
| 440 |
|
uint16_t cpc;
|
| 441 |
|
|
| 442 |
|
/* sync type */
|
| 443 |
|
int fs;
|
| 444 |
|
int bs;
|
| 445 |
|
|
| 446 |
|
/* compatibility */
|
| 447 |
|
int omap_3_1_compatible_disable;
|
| 448 |
|
|
| 449 |
|
qemu_irq irq;
|
| 450 |
|
struct omap_dma_channel_s *sibling;
|
| 451 |
|
|
| 452 |
|
struct omap_dma_reg_set_s {
|
| 453 |
|
target_phys_addr_t src, dest;
|
| 454 |
|
int frame;
|
| 455 |
|
int element;
|
| 456 |
|
int frame_delta[2];
|
| 457 |
|
int elem_delta[2];
|
| 458 |
|
int frames;
|
| 459 |
|
int elements;
|
| 460 |
|
} active_set;
|
| 461 |
|
|
| 462 |
|
/* unused parameters */
|
| 463 |
|
int priority;
|
| 464 |
|
int interleave_disabled;
|
| 465 |
|
int type;
|
| 466 |
|
};
|
| 467 |
|
|
| 468 |
|
struct omap_dma_s {
|
| 469 |
|
QEMUTimer *tm;
|
| 470 |
|
struct omap_mpu_state_s *mpu;
|
| 471 |
|
target_phys_addr_t base;
|
| 472 |
|
omap_clk clk;
|
| 473 |
|
int64_t delay;
|
| 474 |
|
uint32_t drq;
|
| 475 |
|
enum omap_dma_model model;
|
| 476 |
|
int omap_3_1_mapping_disabled;
|
| 477 |
|
|
| 478 |
|
uint16_t gcr;
|
| 479 |
|
int run_count;
|
| 480 |
|
|
| 481 |
|
int chans;
|
| 482 |
|
struct omap_dma_channel_s ch[16];
|
| 483 |
|
struct omap_dma_lcd_channel_s lcd_ch;
|
| 484 |
|
};
|
| 485 |
|
|
| 486 |
|
/* Interrupts */
|
| 487 |
|
#define TIMEOUT_INTR (1 << 0)
|
| 488 |
|
#define EVENT_DROP_INTR (1 << 1)
|
| 489 |
|
#define HALF_FRAME_INTR (1 << 2)
|
| 490 |
|
#define END_FRAME_INTR (1 << 3)
|
| 491 |
|
#define LAST_FRAME_INTR (1 << 4)
|
| 492 |
|
#define END_BLOCK_INTR (1 << 5)
|
| 493 |
|
#define SYNC (1 << 6)
|
| 494 |
|
|
| 495 |
|
static void omap_dma_interrupts_update(struct omap_dma_s *s)
|
| 496 |
|
{
|
| 497 |
|
struct omap_dma_channel_s *ch = s->ch;
|
| 498 |
|
int i;
|
| 499 |
|
|
| 500 |
|
if (s->omap_3_1_mapping_disabled) {
|
| 501 |
|
for (i = 0; i < s->chans; i ++, ch ++)
|
| 502 |
|
if (ch->status)
|
| 503 |
|
qemu_irq_raise(ch->irq);
|
| 504 |
|
} else {
|
| 505 |
|
/* First three interrupts are shared between two channels each. */
|
| 506 |
|
for (i = 0; i < 6; i ++, ch ++) {
|
| 507 |
|
if (ch->status || (ch->sibling && ch->sibling->status))
|
| 508 |
|
qemu_irq_raise(ch->irq);
|
| 509 |
|
}
|
| 510 |
|
}
|
| 511 |
|
}
|
| 512 |
|
|
| 513 |
|
static void omap_dma_channel_load(struct omap_dma_s *s,
|
| 514 |
|
struct omap_dma_channel_s *ch)
|
| 515 |
|
{
|
| 516 |
|
struct omap_dma_reg_set_s *a = &ch->active_set;
|
| 517 |
|
int i;
|
| 518 |
|
int omap_3_1 = !ch->omap_3_1_compatible_disable;
|
| 519 |
|
|
| 520 |
|
/*
|
| 521 |
|
* TODO: verify address ranges and alignment
|
| 522 |
|
* TODO: port endianness
|
| 523 |
|
*/
|
| 524 |
|
|
| 525 |
|
a->src = ch->addr[0];
|
| 526 |
|
a->dest = ch->addr[1];
|
| 527 |
|
a->frames = ch->frames;
|
| 528 |
|
a->elements = ch->elements;
|
| 529 |
|
a->frame = 0;
|
| 530 |
|
a->element = 0;
|
| 531 |
|
|
| 532 |
|
if (unlikely(!ch->elements || !ch->frames)) {
|
| 533 |
|
printf("%s: bad DMA request\n", __FUNCTION__);
|
| 534 |
|
return;
|
| 535 |
|
}
|
| 536 |
|
|
| 537 |
|
for (i = 0; i < 2; i ++)
|
| 538 |
|
switch (ch->mode[i]) {
|
| 539 |
|
case constant:
|
| 540 |
|
a->elem_delta[i] = 0;
|
| 541 |
|
a->frame_delta[i] = 0;
|
| 542 |
|
break;
|
| 543 |
|
case post_incremented:
|
| 544 |
|
a->elem_delta[i] = ch->data_type;
|
| 545 |
|
a->frame_delta[i] = 0;
|
| 546 |
|
break;
|
| 547 |
|
case single_index:
|
| 548 |
|
a->elem_delta[i] = ch->data_type +
|
| 549 |
|
ch->element_index[omap_3_1 ? 0 : i] - 1;
|
| 550 |
|
a->frame_delta[i] = 0;
|
| 551 |
|
break;
|
| 552 |
|
case double_index:
|
| 553 |
|
a->elem_delta[i] = ch->data_type +
|
| 554 |
|
ch->element_index[omap_3_1 ? 0 : i] - 1;
|
| 555 |
|
a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
|
| 556 |
|
ch->element_index[omap_3_1 ? 0 : i];
|
| 557 |
|
break;
|
| 558 |
|
default:
|
| 559 |
|
break;
|
| 560 |
|
}
|
| 561 |
|
}
|
| 562 |
|
|
| 563 |
|
static void omap_dma_activate_channel(struct omap_dma_s *s,
|
| 564 |
|
struct omap_dma_channel_s *ch)
|
| 565 |
|
{
|
| 566 |
|
if (!ch->active) {
|
| 567 |
|
ch->active = 1;
|
| 568 |
|
if (ch->sync)
|
| 569 |
|
ch->status |= SYNC;
|
| 570 |
|
s->run_count ++;
|
| 571 |
|
}
|
| 572 |
|
|
| 573 |
|
if (s->delay && !qemu_timer_pending(s->tm))
|
| 574 |
|
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
|
| 575 |
|
}
|
| 576 |
|
|
| 577 |
|
static void omap_dma_deactivate_channel(struct omap_dma_s *s,
|
| 578 |
|
struct omap_dma_channel_s *ch)
|
| 579 |
|
{
|
| 580 |
|
/* Update cpc */
|
| 581 |
|
ch->cpc = ch->active_set.dest & 0xffff;
|
| 582 |
|
|
| 583 |
|
if (ch->pending_request && !ch->waiting_end_prog) {
|
| 584 |
|
/* Don't deactivate the channel */
|
| 585 |
|
ch->pending_request = 0;
|
| 586 |
|
if (ch->enable)
|
| 587 |
|
return;
|
| 588 |
|
}
|
| 589 |
|
|
| 590 |
|
/* Don't deactive the channel if it is synchronized and the DMA request is
|
| 591 |
|
active */
|
| 592 |
|
if (ch->sync && (s->drq & (1 << ch->sync)) && ch->enable)
|
| 593 |
|
return;
|
| 594 |
|
|
| 595 |
|
if (ch->active) {
|
| 596 |
|
ch->active = 0;
|
| 597 |
|
ch->status &= ~SYNC;
|
| 598 |
|
s->run_count --;
|
| 599 |
|
}
|
| 600 |
|
|
| 601 |
|
if (!s->run_count)
|
| 602 |
|
qemu_del_timer(s->tm);
|
| 603 |
|
}
|
| 604 |
|
|
| 605 |
|
static void omap_dma_enable_channel(struct omap_dma_s *s,
|
| 606 |
|
struct omap_dma_channel_s *ch)
|
| 607 |
|
{
|
| 608 |
|
if (!ch->enable) {
|
| 609 |
|
ch->enable = 1;
|
| 610 |
|
ch->waiting_end_prog = 0;
|
| 611 |
|
omap_dma_channel_load(s, ch);
|
| 612 |
|
if ((!ch->sync) || (s->drq & (1 << ch->sync)))
|
| 613 |
|
omap_dma_activate_channel(s, ch);
|
| 614 |
|
}
|
| 615 |
|
}
|
| 616 |
|
|
| 617 |
|
static void omap_dma_disable_channel(struct omap_dma_s *s,
|
| 618 |
|
struct omap_dma_channel_s *ch)
|
| 619 |
|
{
|
| 620 |
|
if (ch->enable) {
|
| 621 |
|
ch->enable = 0;
|
| 622 |
|
/* Discard any pending request */
|
| 623 |
|
ch->pending_request = 0;
|
| 624 |
|
omap_dma_deactivate_channel(s, ch);
|
| 625 |
|
}
|
| 626 |
|
}
|
| 627 |
|
|
| 628 |
|
static void omap_dma_channel_end_prog(struct omap_dma_s *s,
|
| 629 |
|
struct omap_dma_channel_s *ch)
|
| 630 |
|
{
|
| 631 |
|
if (ch->waiting_end_prog) {
|
| 632 |
|
ch->waiting_end_prog = 0;
|
| 633 |
|
if (!ch->sync || ch->pending_request) {
|
| 634 |
|
ch->pending_request = 0;
|
| 635 |
|
omap_dma_activate_channel(s, ch);
|
| 636 |
|
}
|
| 637 |
|
}
|
| 638 |
|
}
|
| 639 |
|
|
| 640 |
|
static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
|
| 641 |
|
{
|
| 642 |
|
s->omap_3_1_mapping_disabled = 0;
|
| 643 |
|
s->chans = 9;
|
| 644 |
|
}
|
| 645 |
|
|
| 646 |
|
static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
|
| 647 |
|
{
|
| 648 |
|
s->omap_3_1_mapping_disabled = 1;
|
| 649 |
|
s->chans = 16;
|
| 650 |
|
}
|
| 651 |
|
|
| 652 |
|
static void omap_dma_process_request(struct omap_dma_s *s, int request)
|
| 653 |
|
{
|
| 654 |
|
int channel;
|
| 655 |
|
int drop_event = 0;
|
| 656 |
|
struct omap_dma_channel_s *ch = s->ch;
|
| 657 |
|
|
| 658 |
|
for (channel = 0; channel < s->chans; channel ++, ch ++) {
|
| 659 |
|
if (ch->enable && ch->sync == request) {
|
| 660 |
|
if (!ch->active)
|
| 661 |
|
omap_dma_activate_channel(s, ch);
|
| 662 |
|
else if (!ch->pending_request)
|
| 663 |
|
ch->pending_request = 1;
|
| 664 |
|
else {
|
| 665 |
|
/* Request collision */
|
| 666 |
|
/* Second request received while processing other request */
|
| 667 |
|
ch->status |= EVENT_DROP_INTR;
|
| 668 |
|
drop_event = 1;
|
| 669 |
|
}
|
| 670 |
|
}
|
| 671 |
|
}
|
| 672 |
|
|
| 673 |
|
if (drop_event)
|
| 674 |
|
omap_dma_interrupts_update(s);
|
| 675 |
|
}
|
| 676 |
|
|
| 677 |
|
static void omap_dma_channel_run(struct omap_dma_s *s)
|
| 678 |
|
{
|
| 679 |
|
int n = s->chans;
|
| 680 |
|
uint16_t status;
|
| 681 |
|
uint8_t value[4];
|
| 682 |
|
struct omap_dma_port_if_s *src_p, *dest_p;
|
| 683 |
|
struct omap_dma_reg_set_s *a;
|
| 684 |
|
struct omap_dma_channel_s *ch;
|
| 685 |
|
|
| 686 |
|
for (ch = s->ch; n; n --, ch ++) {
|
| 687 |
|
if (!ch->active)
|
| 688 |
|
continue;
|
| 689 |
|
|
| 690 |
|
a = &ch->active_set;
|
| 691 |
|
|
| 692 |
|
src_p = &s->mpu->port[ch->port[0]];
|
| 693 |
|
dest_p = &s->mpu->port[ch->port[1]];
|
| 694 |
|
if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
|
| 695 |
|
(!dest_p->addr_valid(s->mpu, a->dest))) {
|
| 696 |
|
#if 0
|
| 697 |
|
/* Bus time-out */
|
| 698 |
|
if (ch->interrupts & TIMEOUT_INTR)
|
| 699 |
|
ch->status |= TIMEOUT_INTR;
|
| 700 |
|
omap_dma_deactivate_channel(s, ch);
|
| 701 |
|
continue;
|
| 702 |
|
#endif
|
| 703 |
|
printf("%s: Bus time-out in DMA%i operation\n",
|
| 704 |
|
__FUNCTION__, s->chans - n);
|
| 705 |
|
}
|
| 706 |
|
|
| 707 |
|
status = ch->status;
|
| 708 |
|
while (status == ch->status && ch->active) {
|
| 709 |
|
/* Transfer a single element */
|
| 710 |
|
/* FIXME: check the endianness */
|
| 711 |
|
if (!ch->constant_fill)
|
| 712 |
|
cpu_physical_memory_read(a->src, value, ch->data_type);
|
| 713 |
|
else
|
| 714 |
|
*(uint32_t *) value = ch->color;
|
| 715 |
|
|
| 716 |
|
if (!ch->transparent_copy ||
|
| 717 |
|
*(uint32_t *) value != ch->color)
|
| 718 |
|
cpu_physical_memory_write(a->dest, value, ch->data_type);
|
| 719 |
|
|
| 720 |
|
a->src += a->elem_delta[0];
|
| 721 |
|
a->dest += a->elem_delta[1];
|
| 722 |
|
a->element ++;
|
| 723 |
|
|
| 724 |
|
/* If the channel is element synchronized, deactivate it */
|
| 725 |
|
if (ch->sync && !ch->fs && !ch->bs)
|
| 726 |
|
omap_dma_deactivate_channel(s, ch);
|
| 727 |
|
|
| 728 |
|
/* If it is the last frame, set the LAST_FRAME interrupt */
|
| 729 |
|
if (a->element == 1 && a->frame == a->frames - 1)
|
| 730 |
|
if (ch->interrupts & LAST_FRAME_INTR)
|
| 731 |
|
ch->status |= LAST_FRAME_INTR;
|
| 732 |
|
|
| 733 |
|
/* If the half of the frame was reached, set the HALF_FRAME
|
| 734 |
|
interrupt */
|
| 735 |
|
if (a->element == (a->elements >> 1))
|
| 736 |
|
if (ch->interrupts & HALF_FRAME_INTR)
|
| 737 |
|
ch->status |= HALF_FRAME_INTR;
|
| 738 |
|
|
| 739 |
|
if (a->element == a->elements) {
|
| 740 |
|
/* End of Frame */
|
| 741 |
|
a->element = 0;
|
| 742 |
|
a->src += a->frame_delta[0];
|
| 743 |
|
a->dest += a->frame_delta[1];
|
| 744 |
|
a->frame ++;
|
| 745 |
|
|
| 746 |
|
/* If the channel is frame synchronized, deactivate it */
|
| 747 |
|
if (ch->sync && ch->fs)
|
| 748 |
|
omap_dma_deactivate_channel(s, ch);
|
| 749 |
|
|
| 750 |
|
/* If the channel is async, update cpc */
|
| 751 |
|
if (!ch->sync)
|
| 752 |
|
ch->cpc = a->dest & 0xffff;
|
| 753 |
|
|
| 754 |
|
/* Set the END_FRAME interrupt */
|
| 755 |
|
if (ch->interrupts & END_FRAME_INTR)
|
| 756 |
|
ch->status |= END_FRAME_INTR;
|
| 757 |
|
|
| 758 |
|
if (a->frame == a->frames) {
|
| 759 |
|
/* End of Block */
|
| 760 |
|
/* Disable the channel */
|
| 761 |
|
|
| 762 |
|
if (ch->omap_3_1_compatible_disable) {
|
| 763 |
|
omap_dma_disable_channel(s, ch);
|
| 764 |
|
if (ch->link_enabled)
|
| 765 |
|
omap_dma_enable_channel(s,
|
| 766 |
|
&s->ch[ch->link_next_ch]);
|
| 767 |
|
} else {
|
| 768 |
|
if (!ch->auto_init)
|
| 769 |
|
omap_dma_disable_channel(s, ch);
|
| 770 |
|
else if (ch->repeat || ch->end_prog)
|
| 771 |
|
omap_dma_channel_load(s, ch);
|
| 772 |
|
else {
|
| 773 |
|
ch->waiting_end_prog = 1;
|
| 774 |
|
omap_dma_deactivate_channel(s, ch);
|
| 775 |
|
}
|
| 776 |
|
}
|
| 777 |
|
|
| 778 |
|
if (ch->interrupts & END_BLOCK_INTR)
|
| 779 |
|
ch->status |= END_BLOCK_INTR;
|
| 780 |
|
}
|
| 781 |
|
}
|
| 782 |
|
}
|
| 783 |
|
}
|
| 784 |
|
|
| 785 |
|
omap_dma_interrupts_update(s);
|
| 786 |
|
if (s->run_count && s->delay)
|
| 787 |
|
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
|
| 788 |
|
}
|
| 789 |
|
|
| 790 |
|
static void omap_dma_reset(struct omap_dma_s *s)
|
| 791 |
|
{
|
| 792 |
|
int i;
|
| 793 |
|
|
| 794 |
|
qemu_del_timer(s->tm);
|
| 795 |
|
s->gcr = 0x0004;
|
| 796 |
|
s->drq = 0x00000000;
|
| 797 |
|
s->run_count = 0;
|
| 798 |
|
s->lcd_ch.src = emiff;
|
| 799 |
|
s->lcd_ch.condition = 0;
|
| 800 |
|
s->lcd_ch.interrupts = 0;
|
| 801 |
|
s->lcd_ch.dual = 0;
|
| 802 |
|
omap_dma_enable_3_1_mapping(s);
|
| 803 |
|
for (i = 0; i < s->chans; i ++) {
|
| 804 |
|
memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
|
| 805 |
|
memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
|
| 806 |
|
memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
|
| 807 |
|
memset(&s->ch[i].elements, 0, sizeof(s->ch[i].elements));
|
| 808 |
|
memset(&s->ch[i].frames, 0, sizeof(s->ch[i].frames));
|
| 809 |
|
memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
|
| 810 |
|
memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
|
| 811 |
|
memset(&s->ch[i].data_type, 0, sizeof(s->ch[i].data_type));
|
| 812 |
|
memset(&s->ch[i].transparent_copy, 0,
|
| 813 |
|
sizeof(s->ch[i].transparent_copy));
|
| 814 |
|
memset(&s->ch[i].constant_fill, 0, sizeof(s->ch[i].constant_fill));
|
| 815 |
|
memset(&s->ch[i].color, 0, sizeof(s->ch[i].color));
|
| 816 |
|
memset(&s->ch[i].end_prog, 0, sizeof(s->ch[i].end_prog));
|
| 817 |
|
memset(&s->ch[i].repeat, 0, sizeof(s->ch[i].repeat));
|
| 818 |
|
memset(&s->ch[i].auto_init, 0, sizeof(s->ch[i].auto_init));
|
| 819 |
|
memset(&s->ch[i].link_enabled, 0, sizeof(s->ch[i].link_enabled));
|
| 820 |
|
memset(&s->ch[i].link_next_ch, 0, sizeof(s->ch[i].link_next_ch));
|
| 821 |
|
s->ch[i].interrupts = 0x0003;
|
| 822 |
|
memset(&s->ch[i].status, 0, sizeof(s->ch[i].status));
|
| 823 |
|
memset(&s->ch[i].active, 0, sizeof(s->ch[i].active));
|
| 824 |
|
memset(&s->ch[i].enable, 0, sizeof(s->ch[i].enable));
|
| 825 |
|
memset(&s->ch[i].sync, 0, sizeof(s->ch[i].sync));
|
| 826 |
|
memset(&s->ch[i].pending_request, 0, sizeof(s->ch[i].pending_request));
|
| 827 |
|
memset(&s->ch[i].waiting_end_prog, 0,
|
| 828 |
|
sizeof(s->ch[i].waiting_end_prog));
|
| 829 |
|
memset(&s->ch[i].cpc, 0, sizeof(s->ch[i].cpc));
|
| 830 |
|
memset(&s->ch[i].fs, 0, sizeof(s->ch[i].fs));
|
| 831 |
|
memset(&s->ch[i].bs, 0, sizeof(s->ch[i].bs));
|
| 832 |
|
memset(&s->ch[i].omap_3_1_compatible_disable, 0,
|
| 833 |
|
sizeof(s->ch[i].omap_3_1_compatible_disable));
|
| 834 |
|
memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
|
| 835 |
|
memset(&s->ch[i].priority, 0, sizeof(s->ch[i].priority));
|
| 836 |
|
memset(&s->ch[i].interleave_disabled, 0,
|
| 837 |
|
sizeof(s->ch[i].interleave_disabled));
|
| 838 |
|
memset(&s->ch[i].type, 0, sizeof(s->ch[i].type));
|
| 839 |
|
}
|
| 840 |
|
}
|
| 841 |
|
|
| 842 |
|
static int omap_dma_ch_reg_read(struct omap_dma_s *s,
|
| 843 |
|
struct omap_dma_channel_s *ch, int reg, uint16_t *value)
|
| 844 |
|
{
|
| 845 |
|
switch (reg) {
|
| 846 |
|
case 0x00: /* SYS_DMA_CSDP_CH0 */
|
| 847 |
|
*value = (ch->burst[1] << 14) |
|
| 848 |
|
(ch->pack[1] << 13) |
|
| 849 |
|
(ch->port[1] << 9) |
|
| 850 |
|
(ch->burst[0] << 7) |
|
| 851 |
|
(ch->pack[0] << 6) |
|
| 852 |
|
(ch->port[0] << 2) |
|
| 853 |
|
(ch->data_type >> 1);
|
| 854 |
|
break;
|
| 855 |
|
|
| 856 |
|
case 0x02: /* SYS_DMA_CCR_CH0 */
|
| 857 |
|
if (s->model == omap_dma_3_1)
|
| 858 |
|
*value = 0 << 10; /* FIFO_FLUSH reads as 0 */
|
| 859 |
|
else
|
| 860 |
|
*value = ch->omap_3_1_compatible_disable << 10;
|
| 861 |
|
*value |= (ch->mode[1] << 14) |
|
| 862 |
|
(ch->mode[0] << 12) |
|
| 863 |
|
(ch->end_prog << 11) |
|
| 864 |
|
(ch->repeat << 9) |
|
| 865 |
|
(ch->auto_init << 8) |
|
| 866 |
|
(ch->enable << 7) |
|
| 867 |
|
(ch->priority << 6) |
|
| 868 |
|
(ch->fs << 5) | ch->sync;
|
| 869 |
|
break;
|
| 870 |
|
|
| 871 |
|
case 0x04: /* SYS_DMA_CICR_CH0 */
|
| 872 |
|
*value = ch->interrupts;
|
| 873 |
|
break;
|
| 874 |
|
|
| 875 |
|
case 0x06: /* SYS_DMA_CSR_CH0 */
|
| 876 |
|
*value = ch->status;
|
| 877 |
|
ch->status &= SYNC;
|
| 878 |
|
if (!ch->omap_3_1_compatible_disable && ch->sibling) {
|
| 879 |
|
*value |= (ch->sibling->status & 0x3f) << 6;
|
| 880 |
|
ch->sibling->status &= SYNC;
|
| 881 |
|
}
|
| 882 |
|
qemu_irq_lower(ch->irq);
|
| 883 |
|
break;
|
| 884 |
|
|
| 885 |
|
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
|
| 886 |
|
*value = ch->addr[0] & 0x0000ffff;
|
| 887 |
|
break;
|
| 888 |
|
|
| 889 |
|
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
|
| 890 |
|
*value = ch->addr[0] >> 16;
|
| 891 |
|
break;
|
| 892 |
|
|
| 893 |
|
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
|
| 894 |
|
*value = ch->addr[1] & 0x0000ffff;
|
| 895 |
|
break;
|
| 896 |
|
|
| 897 |
|
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
|
| 898 |
|
*value = ch->addr[1] >> 16;
|
| 899 |
|
break;
|
| 900 |
|
|
| 901 |
|
case 0x10: /* SYS_DMA_CEN_CH0 */
|
| 902 |
|
*value = ch->elements;
|
| 903 |
|
break;
|
| 904 |
|
|
| 905 |
|
case 0x12: /* SYS_DMA_CFN_CH0 */
|
| 906 |
|
*value = ch->frames;
|
| 907 |
|
break;
|
| 908 |
|
|
| 909 |
|
case 0x14: /* SYS_DMA_CFI_CH0 */
|
| 910 |
|
*value = ch->frame_index[0];
|
| 911 |
|
break;
|
| 912 |
|
|
| 913 |
|
case 0x16: /* SYS_DMA_CEI_CH0 */
|
| 914 |
|
*value = ch->element_index[0];
|
| 915 |
|
break;
|
| 916 |
|
|
| 917 |
|
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
|
| 918 |
|
if (ch->omap_3_1_compatible_disable)
|
| 919 |
|
*value = ch->active_set.src & 0xffff; /* CSAC */
|
| 920 |
|
else
|
| 921 |
|
*value = ch->cpc;
|
| 922 |
|
break;
|
| 923 |
|
|
| 924 |
|
case 0x1a: /* DMA_CDAC */
|
| 925 |
|
*value = ch->active_set.dest & 0xffff; /* CDAC */
|
| 926 |
|
break;
|
| 927 |
|
|
| 928 |
|
case 0x1c: /* DMA_CDEI */
|
| 929 |
|
*value = ch->element_index[1];
|
| 930 |
|
break;
|
| 931 |
|
|
| 932 |
|
case 0x1e: /* DMA_CDFI */
|
| 933 |
|
*value = ch->frame_index[1];
|
| 934 |
|
break;
|
| 935 |
|
|
| 936 |
|
case 0x20: /* DMA_COLOR_L */
|
| 937 |
|
*value = ch->color & 0xffff;
|
| 938 |
|
break;
|
| 939 |
|
|
| 940 |
|
case 0x22: /* DMA_COLOR_U */
|
| 941 |
|
*value = ch->color >> 16;
|
| 942 |
|
break;
|
| 943 |
|
|
| 944 |
|
case 0x24: /* DMA_CCR2 */
|
| 945 |
|
*value = (ch->bs << 2) |
|
| 946 |
|
(ch->transparent_copy << 1) |
|
| 947 |
|
ch->constant_fill;
|
| 948 |
|
break;
|
| 949 |
|
|
| 950 |
|
case 0x28: /* DMA_CLNK_CTRL */
|
| 951 |
|
*value = (ch->link_enabled << 15) |
|
| 952 |
|
(ch->link_next_ch & 0xf);
|
| 953 |
|
break;
|
| 954 |
|
|
| 955 |
|
case 0x2a: /* DMA_LCH_CTRL */
|
| 956 |
|
*value = (ch->interleave_disabled << 15) |
|
| 957 |
|
ch->type;
|
| 958 |
|
break;
|
| 959 |
|
|
| 960 |
|
default:
|
| 961 |
|
return 1;
|
| 962 |
|
}
|
| 963 |
|
return 0;
|
| 964 |
|
}
|
| 965 |
|
|
| 966 |
|
static int omap_dma_ch_reg_write(struct omap_dma_s *s,
|
| 967 |
|
struct omap_dma_channel_s *ch, int reg, uint16_t value)
|
| 968 |
|
{
|
| 969 |
|
switch (reg) {
|
| 970 |
|
case 0x00: /* SYS_DMA_CSDP_CH0 */
|
| 971 |
|
ch->burst[1] = (value & 0xc000) >> 14;
|
| 972 |
|
ch->pack[1] = (value & 0x2000) >> 13;
|
| 973 |
|
ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
|
| 974 |
|
ch->burst[0] = (value & 0x0180) >> 7;
|
| 975 |
|
ch->pack[0] = (value & 0x0040) >> 6;
|
| 976 |
|
ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
|
| 977 |
|
ch->data_type = (1 << (value & 3));
|
| 978 |
|
if (ch->port[0] >= omap_dma_port_last)
|
| 979 |
|
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
| 980 |
|
ch->port[0]);
|
| 981 |
|
if (ch->port[1] >= omap_dma_port_last)
|
| 982 |
|
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
| 983 |
|
ch->port[1]);
|
| 984 |
|
if ((value & 3) == 3)
|
| 985 |
|
printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
|
| 986 |
|
break;
|
| 987 |
|
|
| 988 |
|
case 0x02: /* SYS_DMA_CCR_CH0 */
|
| 989 |
|
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
|
| 990 |
|
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
|
| 991 |
|
ch->end_prog = (value & 0x0800) >> 11;
|
| 992 |
|
if (s->model > omap_dma_3_1)
|
| 993 |
|
ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
|
| 994 |
|
ch->repeat = (value & 0x0200) >> 9;
|
| 995 |
|
ch->auto_init = (value & 0x0100) >> 8;
|
| 996 |
|
ch->priority = (value & 0x0040) >> 6;
|
| 997 |
|
ch->fs = (value & 0x0020) >> 5;
|
| 998 |
|
ch->sync = value & 0x001f;
|
| 999 |
|
|
| 1000 |
|
if (value & 0x0080)
|
| 1001 |
|
omap_dma_enable_channel(s, ch);
|
| 1002 |
|
else
|
| 1003 |
|
omap_dma_disable_channel(s, ch);
|
| 1004 |
|
|
| 1005 |
|
if (ch->end_prog)
|
| 1006 |
|
omap_dma_channel_end_prog(s, ch);
|
| 1007 |
|
|
| 1008 |
|
break;
|
| 1009 |
|
|
| 1010 |
|
case 0x04: /* SYS_DMA_CICR_CH0 */
|
| 1011 |
|
ch->interrupts = value;
|
| 1012 |
|
break;
|
| 1013 |
|
|
| 1014 |
|
case 0x06: /* SYS_DMA_CSR_CH0 */
|
| 1015 |
|
OMAP_RO_REG((target_phys_addr_t) reg);
|
| 1016 |
|
break;
|
| 1017 |
|
|
| 1018 |
|
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
|
| 1019 |
|
ch->addr[0] &= 0xffff0000;
|
| 1020 |
|
ch->addr[0] |= value;
|
| 1021 |
|
break;
|
| 1022 |
|
|
| 1023 |
|
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
|
| 1024 |
|
ch->addr[0] &= 0x0000ffff;
|
| 1025 |
|
ch->addr[0] |= (uint32_t) value << 16;
|
| 1026 |
|
break;
|
| 1027 |
|
|
| 1028 |
|
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
|
| 1029 |
|
ch->addr[1] &= 0xffff0000;
|
| 1030 |
|
ch->addr[1] |= value;
|
| 1031 |
|
break;
|
| 1032 |
|
|
| 1033 |
|
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
|
| 1034 |
|
ch->addr[1] &= 0x0000ffff;
|
| 1035 |
|
ch->addr[1] |= (uint32_t) value << 16;
|
| 1036 |
|
break;
|
| 1037 |
|
|
| 1038 |
|
case 0x10: /* SYS_DMA_CEN_CH0 */
|
| 1039 |
|
ch->elements = value;
|
| 1040 |
|
break;
|
| 1041 |
|
|
| 1042 |
|
case 0x12: /* SYS_DMA_CFN_CH0 */
|
| 1043 |
|
ch->frames = value;
|
| 1044 |
|
break;
|
| 1045 |
|
|
| 1046 |
|
case 0x14: /* SYS_DMA_CFI_CH0 */
|
| 1047 |
|
ch->frame_index[0] = (int16_t) value;
|
| 1048 |
|
break;
|
| 1049 |
|
|
| 1050 |
|
case 0x16: /* SYS_DMA_CEI_CH0 */
|
| 1051 |
|
ch->element_index[0] = (int16_t) value;
|
| 1052 |
|
break;
|
| 1053 |
|
|
| 1054 |
|
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
|
| 1055 |
|
OMAP_RO_REG((target_phys_addr_t) reg);
|
| 1056 |
|
break;
|
| 1057 |
|
|
| 1058 |
|
case 0x1c: /* DMA_CDEI */
|
| 1059 |
|
ch->element_index[1] = (int16_t) value;
|
| 1060 |
|
break;
|
| 1061 |
|
|
| 1062 |
|
case 0x1e: /* DMA_CDFI */
|
| 1063 |
|
ch->frame_index[1] = (int16_t) value;
|
| 1064 |
|
break;
|
| 1065 |
|
|
| 1066 |
|
case 0x20: /* DMA_COLOR_L */
|
| 1067 |
|
ch->color &= 0xffff0000;
|
| 1068 |
|
ch->color |= value;
|
| 1069 |
|
break;
|
| 1070 |
|
|
| 1071 |
|
case 0x22: /* DMA_COLOR_U */
|
| 1072 |
|
ch->color &= 0xffff;
|
| 1073 |
|
ch->color |= value << 16;
|
| 1074 |
|
break;
|
| 1075 |
|
|
| 1076 |
|
case 0x24: /* DMA_CCR2 */
|
| 1077 |
|
ch->bs = (value >> 2) & 0x1;
|
| 1078 |
|
ch->transparent_copy = (value >> 1) & 0x1;
|
| 1079 |
|
ch->constant_fill = value & 0x1;
|
| 1080 |
|
break;
|
| 1081 |
|
|
| 1082 |
|
case 0x28: /* DMA_CLNK_CTRL */
|
| 1083 |
|
ch->link_enabled = (value >> 15) & 0x1;
|
| 1084 |
|
if (value & (1 << 14)) { /* Stop_Lnk */
|
| 1085 |
|
ch->link_enabled = 0;
|
| 1086 |
|
omap_dma_disable_channel(s, ch);
|
| 1087 |
|
}
|
| 1088 |
|
ch->link_next_ch = value & 0x1f;
|
| 1089 |
|
break;
|
| 1090 |
|
|
| 1091 |
|
case 0x2a: /* DMA_LCH_CTRL */
|
| 1092 |
|
ch->interleave_disabled = (value >> 15) & 0x1;
|
| 1093 |
|
ch->type = value & 0xf;
|
| 1094 |
|
break;
|
| 1095 |
|
|
| 1096 |
|
default:
|
| 1097 |
|
return 1;
|
| 1098 |
|
}
|
| 1099 |
|
return 0;
|
| 1100 |
|
}
|
| 1101 |
|
|
| 1102 |
|
static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
|
| 1103 |
|
uint16_t value)
|
| 1104 |
|
{
|
| 1105 |
|
switch (offset) {
|
| 1106 |
|
case 0xbc0: /* DMA_LCD_CSDP */
|
| 1107 |
|
s->brust_f2 = (value >> 14) & 0x3;
|
| 1108 |
|
s->pack_f2 = (value >> 13) & 0x1;
|
| 1109 |
|
s->data_type_f2 = (1 << ((value >> 11) & 0x3));
|
| 1110 |
|
s->brust_f1 = (value >> 7) & 0x3;
|
| 1111 |
|
s->pack_f1 = (value >> 6) & 0x1;
|
| 1112 |
|
s->data_type_f1 = (1 << ((value >> 0) & 0x3));
|
| 1113 |
|
break;
|
| 1114 |
|
|
| 1115 |
|
case 0xbc2: /* DMA_LCD_CCR */
|
| 1116 |
|
s->mode_f2 = (value >> 14) & 0x3;
|
| 1117 |
|
s->mode_f1 = (value >> 12) & 0x3;
|
| 1118 |
|
s->end_prog = (value >> 11) & 0x1;
|
| 1119 |
|
s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
|
| 1120 |
|
s->repeat = (value >> 9) & 0x1;
|
| 1121 |
|
s->auto_init = (value >> 8) & 0x1;
|
| 1122 |
|
s->running = (value >> 7) & 0x1;
|
| 1123 |
|
s->priority = (value >> 6) & 0x1;
|
| 1124 |
|
s->bs = (value >> 4) & 0x1;
|
| 1125 |
|
break;
|
| 1126 |
|
|
| 1127 |
|
case 0xbc4: /* DMA_LCD_CTRL */
|
| 1128 |
|
s->dst = (value >> 8) & 0x1;
|
| 1129 |
|
s->src = ((value >> 6) & 0x3) << 1;
|
| 1130 |
|
s->condition = 0;
|
| 1131 |
|
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
| 1132 |
|
s->interrupts = (value >> 1) & 1;
|
| 1133 |
|
s->dual = value & 1;
|
| 1134 |
|
break;
|
| 1135 |
|
|
| 1136 |
|
case 0xbc8: /* TOP_B1_L */
|
| 1137 |
|
s->src_f1_top &= 0xffff0000;
|
| 1138 |
|
s->src_f1_top |= 0x0000ffff & value;
|
| 1139 |
|
break;
|
| 1140 |
|
|
| 1141 |
|
case 0xbca: /* TOP_B1_U */
|
| 1142 |
|
s->src_f1_top &= 0x0000ffff;
|
| 1143 |
|
s->src_f1_top |= value << 16;
|
| 1144 |
|
break;
|
| 1145 |
|
|
| 1146 |
|
case 0xbcc: /* BOT_B1_L */
|
| 1147 |
|
s->src_f1_bottom &= 0xffff0000;
|
| 1148 |
|
s->src_f1_bottom |= 0x0000ffff & value;
|
| 1149 |
|
break;
|
| 1150 |
|
|
| 1151 |
|
case 0xbce: /* BOT_B1_U */
|
| 1152 |
|
s->src_f1_bottom &= 0x0000ffff;
|
| 1153 |
|
s->src_f1_bottom |= (uint32_t) value << 16;
|
| 1154 |
|
break;
|
| 1155 |
|
|
| 1156 |
|
case 0xbd0: /* TOP_B2_L */
|
| 1157 |
|
s->src_f2_top &= 0xffff0000;
|
| 1158 |
|
s->src_f2_top |= 0x0000ffff & value;
|
| 1159 |
|
break;
|
| 1160 |
|
|
| 1161 |
|
case 0xbd2: /* TOP_B2_U */
|
| 1162 |
|
s->src_f2_top &= 0x0000ffff;
|
| 1163 |
|
s->src_f2_top |= (uint32_t) value << 16;
|
| 1164 |
|
break;
|
| 1165 |
|
|
| 1166 |
|
case 0xbd4: /* BOT_B2_L */
|
| 1167 |
|
s->src_f2_bottom &= 0xffff0000;
|
| 1168 |
|
s->src_f2_bottom |= 0x0000ffff & value;
|
| 1169 |
|
break;
|
| 1170 |
|
|
| 1171 |
|
case 0xbd6: /* BOT_B2_U */
|
| 1172 |
|
s->src_f2_bottom &= 0x0000ffff;
|
| 1173 |
|
s->src_f2_bottom |= (uint32_t) value << 16;
|
| 1174 |
|
break;
|
| 1175 |
|
|
| 1176 |
|
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
|
| 1177 |
|
s->element_index_f1 = value;
|
| 1178 |
|
break;
|
| 1179 |
|
|
| 1180 |
|
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
|
| 1181 |
|
s->frame_index_f1 &= 0xffff0000;
|
| 1182 |
|
s->frame_index_f1 |= 0x0000ffff & value;
|
| 1183 |
|
break;
|
| 1184 |
|
|
| 1185 |
|
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
|
| 1186 |
|
s->frame_index_f1 &= 0x0000ffff;
|
| 1187 |
|
s->frame_index_f1 |= (uint32_t) value << 16;
|
| 1188 |
|
break;
|
| 1189 |
|
|
| 1190 |
|
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
|
| 1191 |
|
s->element_index_f2 = value;
|
| 1192 |
|
break;
|
| 1193 |
|
|
| 1194 |
|
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
|
| 1195 |
|
s->frame_index_f2 &= 0xffff0000;
|
| 1196 |
|
s->frame_index_f2 |= 0x0000ffff & value;
|
| 1197 |
|
break;
|
| 1198 |
|
|
| 1199 |
|
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
|
| 1200 |
|
s->frame_index_f2 &= 0x0000ffff;
|
| 1201 |
|
s->frame_index_f2 |= (uint32_t) value << 16;
|
| 1202 |
|
break;
|
| 1203 |
|
|
| 1204 |
|
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
|
| 1205 |
|
s->elements_f1 = value;
|
| 1206 |
|
break;
|
| 1207 |
|
|
| 1208 |
|
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
|
| 1209 |
|
s->frames_f1 = value;
|
| 1210 |
|
break;
|
| 1211 |
|
|
| 1212 |
|
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
|
| 1213 |
|
s->elements_f2 = value;
|
| 1214 |
|
break;
|
| 1215 |
|
|
| 1216 |
|
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
|
| 1217 |
|
s->frames_f2 = value;
|
| 1218 |
|
break;
|
| 1219 |
|
|
| 1220 |
|
case 0xbea: /* DMA_LCD_LCH_CTRL */
|
| 1221 |
|
s->lch_type = value & 0xf;
|
| 1222 |
|
break;
|
| 1223 |
|
|
| 1224 |
|
default:
|
| 1225 |
|
return 1;
|
| 1226 |
|
}
|
| 1227 |
|
return 0;
|
| 1228 |
|
}
|
| 1229 |
|
|
| 1230 |
|
static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
|
| 1231 |
|
uint16_t *ret)
|
| 1232 |
|
{
|
| 1233 |
|
switch (offset) {
|
| 1234 |
|
case 0xbc0: /* DMA_LCD_CSDP */
|
| 1235 |
|
*ret = (s->brust_f2 << 14) |
|
| 1236 |
|
(s->pack_f2 << 13) |
|
| 1237 |
|
((s->data_type_f2 >> 1) << 11) |
|
| 1238 |
|
(s->brust_f1 << 7) |
|
| 1239 |
|
(s->pack_f1 << 6) |
|
| 1240 |
|
((s->data_type_f1 >> 1) << 0);
|
| 1241 |
|
break;
|
| 1242 |
|
|
| 1243 |
|
case 0xbc2: /* DMA_LCD_CCR */
|
| 1244 |
|
*ret = (s->mode_f2 << 14) |
|
| 1245 |
|
(s->mode_f1 << 12) |
|
| 1246 |
|
(s->end_prog << 11) |
|
| 1247 |
|
(s->omap_3_1_compatible_disable << 10) |
|
| 1248 |
|
(s->repeat << 9) |
|
| 1249 |
|
(s->auto_init << 8) |
|
| 1250 |
|
(s->running << 7) |
|
| 1251 |
|
(s->priority << 6) |
|
| 1252 |
|
(s->bs << 4);
|
| 1253 |
|
break;
|
| 1254 |
|
|
| 1255 |
|
case 0xbc4: /* DMA_LCD_CTRL */
|
| 1256 |
|
qemu_irq_lower(s->irq);
|
| 1257 |
|
*ret = (s->dst << 8) |
|
| 1258 |
|
((s->src & 0x6) << 5) |
|
| 1259 |
|
(s->condition << 3) |
|
| 1260 |
|
(s->interrupts << 1) |
|
| 1261 |
|
s->dual;
|
| 1262 |
|
break;
|
| 1263 |
|
|
| 1264 |
|
case 0xbc8: /* TOP_B1_L */
|
| 1265 |
|
*ret = s->src_f1_top & 0xffff;
|
| 1266 |
|
break;
|
| 1267 |
|
|
| 1268 |
|
case 0xbca: /* TOP_B1_U */
|
| 1269 |
|
*ret = s->src_f1_top >> 16;
|
| 1270 |
|
break;
|
| 1271 |
|
|
| 1272 |
|
case 0xbcc: /* BOT_B1_L */
|
| 1273 |
|
*ret = s->src_f1_bottom & 0xffff;
|
| 1274 |
|
break;
|
| 1275 |
|
|
| 1276 |
|
case 0xbce: /* BOT_B1_U */
|
| 1277 |
|
*ret = s->src_f1_bottom >> 16;
|
| 1278 |
|
break;
|
| 1279 |
|
|
| 1280 |
|
case 0xbd0: /* TOP_B2_L */
|
| 1281 |
|
*ret = s->src_f2_top & 0xffff;
|
| 1282 |
|
break;
|
| 1283 |
|
|
| 1284 |
|
case 0xbd2: /* TOP_B2_U */
|
| 1285 |
|
*ret = s->src_f2_top >> 16;
|
| 1286 |
|
break;
|
| 1287 |
|
|
| 1288 |
|
case 0xbd4: /* BOT_B2_L */
|
| 1289 |
|
*ret = s->src_f2_bottom & 0xffff;
|
| 1290 |
|
break;
|
| 1291 |
|
|
| 1292 |
|
case 0xbd6: /* BOT_B2_U */
|
| 1293 |
|
*ret = s->src_f2_bottom >> 16;
|
| 1294 |
|
break;
|
| 1295 |
|
|
| 1296 |
|
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
|
| 1297 |
|
*ret = s->element_index_f1;
|
| 1298 |
|
break;
|
| 1299 |
|
|
| 1300 |
|
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
|
| 1301 |
|
*ret = s->frame_index_f1 & 0xffff;
|
| 1302 |
|
break;
|
| 1303 |
|
|
| 1304 |
|
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
|
| 1305 |
|
*ret = s->frame_index_f1 >> 16;
|
| 1306 |
|
break;
|
| 1307 |
|
|
| 1308 |
|
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
|
| 1309 |
|
*ret = s->element_index_f2;
|
| 1310 |
|
break;
|
| 1311 |
|
|
| 1312 |
|
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
|
| 1313 |
|
*ret = s->frame_index_f2 & 0xffff;
|
| 1314 |
|
break;
|
| 1315 |
|
|
| 1316 |
|
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
|
| 1317 |
|
*ret = s->frame_index_f2 >> 16;
|
| 1318 |
|
break;
|
| 1319 |
|
|
| 1320 |
|
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
|
| 1321 |
|
*ret = s->elements_f1;
|
| 1322 |
|
break;
|
| 1323 |
|
|
| 1324 |
|
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
|
| 1325 |
|
*ret = s->frames_f1;
|
| 1326 |
|
break;
|
| 1327 |
|
|
| 1328 |
|
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
|
| 1329 |
|
*ret = s->elements_f2;
|
| 1330 |
|
break;
|
| 1331 |
|
|
| 1332 |
|
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
|
| 1333 |
|
*ret = s->frames_f2;
|
| 1334 |
|
break;
|
| 1335 |
|
|
| 1336 |
|
case 0xbea: /* DMA_LCD_LCH_CTRL */
|
| 1337 |
|
*ret = s->lch_type;
|
| 1338 |
|
break;
|
| 1339 |
|
|
| 1340 |
|
default:
|
| 1341 |
|
return 1;
|
| 1342 |
|
}
|
| 1343 |
|
return 0;
|
| 1344 |
|
}
|
| 1345 |
|
|
| 1346 |
|
static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
|
| 1347 |
|
uint16_t value)
|
| 1348 |
|
{
|
| 1349 |
|
switch (offset) {
|
| 1350 |
|
case 0x300: /* SYS_DMA_LCD_CTRL */
|
| 1351 |
|
s->src = (value & 0x40) ? imif : emiff;
|
| 1352 |
|
s->condition = 0;
|
| 1353 |
|
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
| 1354 |
|
s->interrupts = (value >> 1) & 1;
|
| 1355 |
|
s->dual = value & 1;
|
| 1356 |
|
break;
|
| 1357 |
|
|
| 1358 |
|
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
|
| 1359 |
|
s->src_f1_top &= 0xffff0000;
|
| 1360 |
|
s->src_f1_top |= 0x0000ffff & value;
|
| 1361 |
|
break;
|
| 1362 |
|
|
| 1363 |
|
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
|
| 1364 |
|
s->src_f1_top &= 0x0000ffff;
|
| 1365 |
|
s->src_f1_top |= value << 16;
|
| 1366 |
|
break;
|
| 1367 |
|
|
| 1368 |
|
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
|
| 1369 |
|
s->src_f1_bottom &= 0xffff0000;
|
| 1370 |
|
s->src_f1_bottom |= 0x0000ffff & value;
|
| 1371 |
|
break;
|
| 1372 |
|
|
| 1373 |
|
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
|
| 1374 |
|
s->src_f1_bottom &= 0x0000ffff;
|
| 1375 |
|
s->src_f1_bottom |= value << 16;
|
| 1376 |
|
break;
|
| 1377 |
|
|
| 1378 |
|
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
|
| 1379 |
|
s->src_f2_top &= 0xffff0000;
|
| 1380 |
|
s->src_f2_top |= 0x0000ffff & value;
|
| 1381 |
|
break;
|
| 1382 |
|
|
| 1383 |
|
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
|
| 1384 |
|
s->src_f2_top &= 0x0000ffff;
|
| 1385 |
|
s->src_f2_top |= value << 16;
|
| 1386 |
|
break;
|
| 1387 |
|
|
| 1388 |
|
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
|
| 1389 |
|
s->src_f2_bottom &= 0xffff0000;
|
| 1390 |
|
s->src_f2_bottom |= 0x0000ffff & value;
|
| 1391 |
|
break;
|
| 1392 |
|
|
| 1393 |
|
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
|
| 1394 |
|
s->src_f2_bottom &= 0x0000ffff;
|
| 1395 |
|
s->src_f2_bottom |= value << 16;
|
| 1396 |
|
break;
|
| 1397 |
|
|
| 1398 |
|
default:
|
| 1399 |
|
return 1;
|
| 1400 |
|
}
|
| 1401 |
|
return 0;
|
| 1402 |
|
}
|
| 1403 |
|
|
| 1404 |
|
static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
|
| 1405 |
|
uint16_t *ret)
|
| 1406 |
|
{
|
| 1407 |
|
int i;
|
| 1408 |
|
|
| 1409 |
|
switch (offset) {
|
| 1410 |
|
case 0x300: /* SYS_DMA_LCD_CTRL */
|
| 1411 |
|
i = s->condition;
|
| 1412 |
|
s->condition = 0;
|
| 1413 |
|
qemu_irq_lower(s->irq);
|
| 1414 |
|
*ret = ((s->src == imif) << 6) | (i << 3) |
|
| 1415 |
|
(s->interrupts << 1) | s->dual;
|
| 1416 |
|
break;
|
| 1417 |
|
|
| 1418 |
|
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
|
| 1419 |
|
*ret = s->src_f1_top & 0xffff;
|
| 1420 |
|
break;
|
| 1421 |
|
|
| 1422 |
|
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
|
| 1423 |
|
*ret = s->src_f1_top >> 16;
|
| 1424 |
|
break;
|
| 1425 |
|
|
| 1426 |
|
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
|
| 1427 |
|
*ret = s->src_f1_bottom & 0xffff;
|
| 1428 |
|
break;
|
| 1429 |
|
|
| 1430 |
|
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
|
| 1431 |
|
*ret = s->src_f1_bottom >> 16;
|
| 1432 |
|
break;
|
| 1433 |
|
|
| 1434 |
|
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
|
| 1435 |
|
*ret = s->src_f2_top & 0xffff;
|
| 1436 |
|
break;
|
| 1437 |
|
|
| 1438 |
|
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
|
| 1439 |
|
*ret = s->src_f2_top >> 16;
|
| 1440 |
|
break;
|
| 1441 |
|
|
| 1442 |
|
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
|
| 1443 |
|
*ret = s->src_f2_bottom & 0xffff;
|
| 1444 |
|
break;
|
| 1445 |
|
|
| 1446 |
|
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
|
| 1447 |
|
*ret = s->src_f2_bottom >> 16;
|
| 1448 |
|
break;
|
| 1449 |
|
|
| 1450 |
|
default:
|
| 1451 |
|
return 1;
|
| 1452 |
|
}
|
| 1453 |
|
return 0;
|
| 1454 |
|
}
|
| 1455 |
|
|
| 1456 |
|
static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
|
| 1457 |
|
{
|
| 1458 |
|
switch (offset) {
|
| 1459 |
|
case 0x400: /* SYS_DMA_GCR */
|
| 1460 |
|
s->gcr = value;
|
| 1461 |
|
break;
|
| 1462 |
|
|
| 1463 |
|
case 0x404: /* DMA_GSCR */
|
| 1464 |
|
if (value & 0x8)
|
| 1465 |
|
omap_dma_disable_3_1_mapping(s);
|
| 1466 |
|
else
|
| 1467 |
|
omap_dma_enable_3_1_mapping(s);
|
| 1468 |
|
break;
|
| 1469 |
|
|
| 1470 |
|
case 0x408: /* DMA_GRST */
|
| 1471 |
|
if (value & 0x1)
|
| 1472 |
|
omap_dma_reset(s);
|