Revision b4ff5987 target-sparc/cpu.h
| b/target-sparc/cpu.h | ||
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| 29 | 29 |
#define PSR_PS (1<<6) |
| 30 | 30 |
#define PSR_ET (1<<5) |
| 31 | 31 |
#define PSR_CWP 0x1f |
| 32 |
/* Fake impl 0, version 4 */ |
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#define GET_PSR(env) ((0 << 28) | (4 << 24) | env->psr | \ |
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(env->psref? PSR_EF : 0) | \ |
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(env->psrpil << 8) | \ |
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(env->psrs? PSR_S : 0) | \ |
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(env->psrs? PSR_PS : 0) | \ |
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(env->psret? PSR_ET : 0) | env->cwp) |
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#define PUT_PSR(env, val) do { int _tmp = val; \
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env->psr = _tmp & ~PSR_ICC; \ |
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env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
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env->psrpil = (_tmp & PSR_PIL) >> 8; \ |
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env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
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env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
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env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
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set_cwp(_tmp & PSR_CWP & (NWINDOWS - 1)); \ |
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} while (0) |
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| 49 | 32 |
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| 50 | 33 |
/* Trap base register */ |
| 51 | 34 |
#define TBR_BASE_MASK 0xfffff000 |
| ... | ... | |
| 171 | 154 |
void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f); |
| 172 | 155 |
double cpu_put_fp64(uint64_t mant, uint16_t exp); |
| 173 | 156 |
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/* Fake impl 0, version 4 */ |
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#define GET_PSR(env) ((0 << 28) | (4 << 24) | env->psr | \ |
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(env->psref? PSR_EF : 0) | \ |
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(env->psrpil << 8) | \ |
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(env->psrs? PSR_S : 0) | \ |
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(env->psrs? PSR_PS : 0) | \ |
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(env->psret? PSR_ET : 0) | env->cwp) |
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#ifndef NO_CPU_IO_DEFS |
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void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
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#endif |
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#define PUT_PSR(env, val) do { int _tmp = val; \
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env->psr = _tmp & ~PSR_ICC; \ |
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env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
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env->psrpil = (_tmp & PSR_PIL) >> 8; \ |
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env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
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env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
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env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
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cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \ |
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} while (0) |
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| 174 | 179 |
struct siginfo; |
| 175 | 180 |
int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); |
| 176 | 181 |
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