Revision b50a6563 hw/palm.c
b/hw/palm.c | ||
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76 | 76 |
#define PALMTE_MMC2_GPIO 7 |
77 | 77 |
#define PALMTE_MMC3_GPIO 11 |
78 | 78 |
|
79 |
static void palmte_pintdav(void *opaque, int line, int level) |
|
80 |
{ |
|
81 |
struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque; |
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82 |
|
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qemu_set_irq(omap_gpio_in_get(cpu->gpio)[PALMTE_PINTDAV_GPIO], |
|
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!level); |
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} |
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86 |
|
|
87 | 79 |
static void palmte_microwire_setup(struct omap_mpu_state_s *cpu) |
88 | 80 |
{ |
81 |
qemu_irq p_int = omap_gpio_in_get(cpu->gpio)[PALMTE_PINTDAV_GPIO]; |
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82 |
|
|
89 | 83 |
omap_uwire_attach( |
90 | 84 |
cpu->microwire, |
91 |
tsc2102_init( |
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qemu_allocate_irqs(palmte_pintdav, cpu, 1)[0]), |
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tsc2102_init(qemu_irq_invert(p_int)), |
|
93 | 86 |
0); |
94 | 87 |
} |
95 | 88 |
|
... | ... | |
122 | 115 |
!(keycode & 0x80)); |
123 | 116 |
} |
124 | 117 |
|
125 |
static void palmte_mmc_cover(void *opaque, int line, int level) |
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{ |
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struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque; |
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|
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qemu_set_irq(omap_mpuio_in_get(cpu->mpuio)[PALMTE_MMC_SWITCH_GPIO], |
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!level); |
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} |
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132 |
|
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133 | 118 |
static void palmte_init(int ram_size, int vga_ram_size, int boot_device, |
134 | 119 |
DisplayState *ds, const char **fd_filename, int snapshot, |
135 | 120 |
const char *kernel_filename, const char *kernel_cmdline, |
... | ... | |
174 | 159 |
|
175 | 160 |
omap_mmc_handlers(cpu->mmc, |
176 | 161 |
omap_gpio_in_get(cpu->gpio)[PALMTE_MMC_WP_GPIO], |
177 |
qemu_allocate_irqs(palmte_mmc_cover, cpu, 1)[0]); |
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qemu_irq_invert(omap_mpuio_in_get(cpu->mpuio) |
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[PALMTE_MMC_SWITCH_GPIO])); |
|
178 | 164 |
|
179 | 165 |
/* Setup initial (reset) machine state */ |
180 | 166 |
if (nb_option_roms) { |
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