| 26 |
26 |
uint32_t nvflags;
|
| 27 |
27 |
uint32_t resetlevel;
|
| 28 |
28 |
uint32_t proc_id;
|
|
29 |
uint32_t sys_mci;
|
| 29 |
30 |
} arm_sysctl_state;
|
| 30 |
31 |
|
| 31 |
32 |
static const VMStateDescription vmstate_arm_sysctl = {
|
| ... | ... | |
| 44 |
45 |
}
|
| 45 |
46 |
};
|
| 46 |
47 |
|
|
48 |
/* The PB926 actually uses a different format for
|
|
49 |
* its SYS_ID register. Fortunately the bits which are
|
|
50 |
* board type on later boards are distinct.
|
|
51 |
*/
|
|
52 |
#define BOARD_ID_PB926 0x100
|
|
53 |
#define BOARD_ID_EB 0x140
|
|
54 |
#define BOARD_ID_PBA8 0x178
|
|
55 |
#define BOARD_ID_PBX 0x182
|
|
56 |
|
|
57 |
static int board_id(arm_sysctl_state *s)
|
|
58 |
{
|
|
59 |
/* Extract the board ID field from the SYS_ID register value */
|
|
60 |
return (s->sys_id >> 16) & 0xfff;
|
|
61 |
}
|
|
62 |
|
| 47 |
63 |
static void arm_sysctl_reset(DeviceState *d)
|
| 48 |
64 |
{
|
| 49 |
65 |
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
|
| ... | ... | |
| 92 |
108 |
case 0x44: /* PCICTL */
|
| 93 |
109 |
return 1;
|
| 94 |
110 |
case 0x48: /* MCI */
|
| 95 |
|
return 0;
|
|
111 |
return s->sys_mci;
|
| 96 |
112 |
case 0x4c: /* FLASH */
|
| 97 |
113 |
return 0;
|
| 98 |
114 |
case 0x50: /* CLCD */
|
| ... | ... | |
| 218 |
234 |
arm_sysctl_write
|
| 219 |
235 |
};
|
| 220 |
236 |
|
|
237 |
static void arm_sysctl_gpio_set(void *opaque, int line, int level)
|
|
238 |
{
|
|
239 |
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
|
|
240 |
switch (line) {
|
|
241 |
case ARM_SYSCTL_GPIO_MMC_WPROT:
|
|
242 |
{
|
|
243 |
/* For PB926 and EB write-protect is bit 2 of SYS_MCI;
|
|
244 |
* for all later boards it is bit 1.
|
|
245 |
*/
|
|
246 |
int bit = 2;
|
|
247 |
if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
|
|
248 |
bit = 4;
|
|
249 |
}
|
|
250 |
s->sys_mci &= ~bit;
|
|
251 |
if (level) {
|
|
252 |
s->sys_mci |= bit;
|
|
253 |
}
|
|
254 |
break;
|
|
255 |
}
|
|
256 |
case ARM_SYSCTL_GPIO_MMC_CARDIN:
|
|
257 |
s->sys_mci &= ~1;
|
|
258 |
if (level) {
|
|
259 |
s->sys_mci |= 1;
|
|
260 |
}
|
|
261 |
break;
|
|
262 |
}
|
|
263 |
}
|
|
264 |
|
| 221 |
265 |
static int arm_sysctl_init1(SysBusDevice *dev)
|
| 222 |
266 |
{
|
| 223 |
267 |
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
|
| ... | ... | |
| 227 |
271 |
arm_sysctl_writefn, s,
|
| 228 |
272 |
DEVICE_NATIVE_ENDIAN);
|
| 229 |
273 |
sysbus_init_mmio(dev, 0x1000, iomemtype);
|
|
274 |
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
|
| 230 |
275 |
/* ??? Save/restore. */
|
| 231 |
276 |
return 0;
|
| 232 |
277 |
}
|