Archipelago » qemu

 *

 ***************************************/

{

    CirrusVGAState *s;

    s = qemu_mallocz(sizeof(CirrusVGAState));

    cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);

    s->ds = graphic_console_init(s->update, s->invalidate,

                                 s->screen_dump, s->text_update, s);

    vga_dirty_log_start((VGAState *)s);

}

{

    PCICirrusVGAState *d;

    uint8_t *pci_conf;

    /* setup VGA */

    s = &d->cirrus_vga;

    cirrus_init_common(s, device_id, 1);

    s->ds = graphic_console_init(s->update, s->invalidate,

    qemu_put_be32(f, s->height);

}

                   target_phys_addr_t ctrl_base, int it_shift,

                   qemu_irq irq)

{

    s = qemu_mallocz(sizeof(G364State));

    s->vram_size = vram_size;

    s->irq = irq;

void ds1225y_set_protection(void *opaque, int protection);

/* g364fb.c */

                   target_phys_addr_t ctrl_base, int it_shift,

                   qemu_irq irq);

    qemu_irq esp_reset;

    ram_addr_t ram_offset;

    ram_addr_t bios_offset;

    /* init CPUs */

    if (cpu_model == NULL) {

    ram_offset = qemu_ram_alloc(ram_size);

    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);

    bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);

    cpu_register_physical_memory(0x1fc00000LL,

                                 MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);

    /* Video card */

    switch (jazz_model) {

    case JAZZ_MAGNUM:

        break;

    case JAZZ_PICA61:

        break;

    default:

        break;

{

    char buf[1024];

    ram_addr_t ram_offset;

    ram_addr_t bios_offset;

    target_long bios_size;

    int64_t kernel_entry;

        exit(1);

    }

    ram_offset = qemu_ram_alloc(ram_size);

    bios_offset = qemu_ram_alloc(BIOS_SIZE);

    /* Optional PCI video card */

    if (cirrus_vga_enabled) {

    } else if (vmsvga_enabled) {

    } else if (std_vga_enabled) {

    }

}

{

    char buf[1024];

    ram_addr_t ram_offset;

    ram_addr_t bios_offset;

    int bios_size;

    CPUState *env;

        exit(1);

    }

    ram_offset = qemu_ram_alloc(ram_size);

    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);

        }

    }

    if (nd_table[0].vlan)

        isa_ne2000_init(0x300, i8259[9], &nd_table[0]);

{

    char buf[1024];

    int ret, linux_boot, i;

    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;

    int bios_size, isa_bios_size, oprom_area_size;

    PCIBus *pci_bus;

    }

    /* BIOS load */

    if (bios_name == NULL)

        bios_name = BIOS_FILENAME;

    if (cirrus_vga_enabled) {

        if (pci_enabled) {

        } else {

        }

    } else if (vmsvga_enabled) {

        if (pci_enabled)

        else

            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);

    } else if (std_vga_enabled) {

        if (pci_enabled) {

        } else {

        }

    }

#define VGA_RAM_SIZE (9 * 1024 * 1024)

#endif

                 unsigned long vga_bios_offset, int vga_bios_size);

/* cirrus_vga.c */

/* ide.c */

void isa_ide_init(int iobase, int iobase2, qemu_irq irq,

void *lsi_scsi_init(PCIBus *bus, int devfn);

/* vmware_vga.c */

/* usb-uhci.c */

void usb_uhci_piix3_init(PCIBus *bus, int devfn);

    qemu_irq *pic, **openpic_irqs;

    int unin_memory;

    int linux_boot, i;

    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    PCIBus *pci_bus;

    MacIONVRAMState *nvr;

    ram_offset = qemu_ram_alloc(ram_size);

    cpu_register_physical_memory(0, ram_size, ram_offset);

    /* allocate and load BIOS */

    bios_offset = qemu_ram_alloc(BIOS_SIZE);

    if (bios_name == NULL)

    pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);

    pci_bus = pci_pmac_init(pic);

    /* init basic PC hardware */

                 vga_bios_offset, vga_bios_size);

    /* XXX: suppress that */

    char buf[1024];

    qemu_irq *pic, **heathrow_irqs;

    int linux_boot, i;

    uint32_t kernel_base, initrd_base;

    int32_t kernel_size, initrd_size;

    PCIBus *pci_bus;

    ram_offset = qemu_ram_alloc(ram_size);

    cpu_register_physical_memory(0, ram_size, ram_offset);

    /* allocate and load BIOS */

    bios_offset = qemu_ram_alloc(BIOS_SIZE);

    if (bios_name == NULL)

    }

    pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);

    pci_bus = pci_grackle_init(0xfec00000, pic);

                 vga_bios_offset, vga_bios_size);

    escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],

    m48t59_t *m48t59;

    int PPC_io_memory;

    int linux_boot, i, nb_nics1, bios_size;

    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    PCIBus *pci_bus;

    qemu_irq *i8259;

    ram_offset = qemu_ram_alloc(ram_size);

    cpu_register_physical_memory(0, ram_size, ram_offset);

    /* allocate and load BIOS */

    bios_offset = qemu_ram_alloc(BIOS_SIZE);

    if (bios_name == NULL)

    cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);

    /* init basic PC hardware */

    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);

    //    pit = pit_init(0x40, i8259[0]);

    rtc_init(0x70, i8259[8], 2000);

    m48t59_t *nvram;

    int ret, linux_boot;

    unsigned int i;

    long initrd_size, kernel_size;

    PCIBus *pci_bus, *pci_bus2, *pci_bus3;

    QEMUBH *bh;

    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,

                           &pci_bus3);

    isa_mem_base = VGA_BASE;

    // XXX Should be pci_bus3

    pci_ebus_init(pci_bus, -1);

    vga_dirty_log_start(s);

}

{

    int i, j, v, b;

        expand4to8[i] = v;

    }

    s->vram_size = vga_ram_size;

    s->get_bpp = vga_get_bpp;

    s->get_offsets = vga_get_offsets;

    qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);

}

{

    VGAState *s;

    s = qemu_mallocz(sizeof(VGAState));

    vga_init(s);

    s->ds = graphic_console_init(s->update, s->invalidate,

#ifdef CONFIG_BOCHS_VBE

    /* XXX: use optimized standard vga accesses */

    cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,

#endif

    return 0;

}

{

    VGAState *s;

    s = qemu_mallocz(sizeof(VGAState));

    vga_mm_init(s, vram_base, ctrl_base, it_shift);

    s->ds = graphic_console_init(s->update, s->invalidate,

#ifdef CONFIG_BOCHS_VBE

    /* XXX: use optimized standard vga accesses */

    cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,

#endif

    return 0;

}

    vga_dirty_log_start(s);

}

                 unsigned long vga_bios_offset, int vga_bios_size)

{

    PCIVGAState *d;

        return -1;

    s = &d->vga_state;

    vga_init(s);

    s->ds = graphic_console_init(s->update, s->invalidate,

    return (v << 2) | (b << 1) | b;

}

void vga_init(VGAState *s);

void vga_reset(void *s);

    DisplayState *ds;

    int vram_size;

    ram_addr_t vram_offset;

#endif

    target_phys_addr_t vram_base;

    int index;

    bypl = s->bypp * s->width;

    width = s->bypp * w;

    start = s->bypp * x + bypl * y;

    dst = ds_get_data(s->ds) + start;

    for (; line > 0; line --, src += bypl, dst += bypl)

static inline void vmsvga_update_screen(struct vmsvga_state_s *s)

{

#ifndef DIRECT_VRAM

#endif

    dpy_update(s->ds, 0, 0, s->width, s->height);

# ifdef DIRECT_VRAM

    uint8_t *vram = ds_get_data(s->ds);

# else

# endif

    int bypl = s->bypp * s->width;

    int width = s->bypp * w;

# ifdef DIRECT_VRAM

    uint8_t *vram = ds_get_data(s->ds);

# else

# endif

    int bypp = s->bypp;

    int bypl = bypp * s->width;

    case SVGA_REG_CONFIG_DONE:

        if (value) {

            /* Check range and alignment.  */

            if ((CMD(min) | CMD(max) |

                        CMD(next_cmd) | CMD(stop)) & 3)

    if (s->depth == 32) {

        DisplaySurface *ds = qemu_create_displaysurface_from(s->width,

        ppm_save(filename, ds);

        qemu_free(ds);

    }

    if (addr < s->fb_size)

        return *(uint8_t *) (ds_get_data(s->ds) + addr);

    else

}

static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)

    if (addr < s->fb_size)

        return *(uint16_t *) (ds_get_data(s->ds) + addr);

    else

}

static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)

    if (addr < s->fb_size)

        return *(uint32_t *) (ds_get_data(s->ds) + addr);

    else

}

static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,

    if (addr < s->fb_size)

        *(uint8_t *) (ds_get_data(s->ds) + addr) = value;

    else

}

static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,

    if (addr < s->fb_size)

        *(uint16_t *) (ds_get_data(s->ds) + addr) = value;

    else

}

static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,

    if (addr < s->fb_size)

        *(uint32_t *) (ds_get_data(s->ds) + addr) = value;

    else

}

static CPUReadMemoryFunc *vmsvga_vram_read[] = {

    s->invalidated = 1;

    if (s->config)

    return 0;

}

{

    s->scratch_size = SVGA_SCRATCH_SIZE;

    s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);

    vmsvga_reset(s);

#ifdef EMBED_STDVGA

    vga_init((VGAState *) s);

#endif

    s->ds = graphic_console_init(vmsvga_update_display,

#ifdef CONFIG_BOCHS_VBE

    /* XXX: use optimized standard vga accesses */

    cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,

#endif

}

#define PCI_CLASS_HEADERTYPE_00h	0x00

{

    struct pci_vmsvga_state_s *s;

    pci_register_io_region(&s->card, 1, vga_ram_size,

                    PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);

    register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);

}