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1
/*
2
 * QEMU PPC PREP hardware System Emulator
3
 *
4
 * Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "nvram.h"
26
#include "pc.h"
27
#include "fdc.h"
28
#include "net.h"
29
#include "sysemu.h"
30
#include "isa.h"
31
#include "pci.h"
32
#include "ppc.h"
33
#include "boards.h"
34
#include "qemu-log.h"
35

    
36
//#define HARD_DEBUG_PPC_IO
37
//#define DEBUG_PPC_IO
38

    
39
/* SMP is not enabled, for now */
40
#define MAX_CPUS 1
41

    
42
#define MAX_IDE_BUS 2
43

    
44
#define BIOS_FILENAME "ppc_rom.bin"
45
#define KERNEL_LOAD_ADDR 0x01000000
46
#define INITRD_LOAD_ADDR 0x01800000
47

    
48
#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
49
#define DEBUG_PPC_IO
50
#endif
51

    
52
#if defined (HARD_DEBUG_PPC_IO)
53
#define PPC_IO_DPRINTF(fmt, args...)                     \
54
do {                                                     \
55
    if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
56
        qemu_log("%s: " fmt, __func__ , ##args); \
57
    } else {                                             \
58
        printf("%s : " fmt, __func__ , ##args);          \
59
    }                                                    \
60
} while (0)
61
#elif defined (DEBUG_PPC_IO)
62
#define PPC_IO_DPRINTF(fmt, args...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
63
#else
64
#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
65
#endif
66

    
67
/* Constants for devices init */
68
static const int ide_iobase[2] = { 0x1f0, 0x170 };
69
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
70
static const int ide_irq[2] = { 13, 13 };
71

    
72
#define NE2000_NB_MAX 6
73

    
74
static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
75
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
76

    
77
//static PITState *pit;
78

    
79
/* ISA IO ports bridge */
80
#define PPC_IO_BASE 0x80000000
81

    
82
#if 0
83
/* Speaker port 0x61 */
84
static int speaker_data_on;
85
static int dummy_refresh_clock;
86
#endif
87

    
88
static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
89
{
90
#if 0
91
    speaker_data_on = (val >> 1) & 1;
92
    pit_set_gate(pit, 2, val & 1);
93
#endif
94
}
95

    
96
static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
97
{
98
#if 0
99
    int out;
100
    out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
101
    dummy_refresh_clock ^= 1;
102
    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
103
        (dummy_refresh_clock << 4);
104
#endif
105
    return 0;
106
}
107

    
108
/* PCI intack register */
109
/* Read-only register (?) */
110
static void _PPC_intack_write (void *opaque,
111
                               target_phys_addr_t addr, uint32_t value)
112
{
113
//    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
114
}
115

    
116
static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
117
{
118
    uint32_t retval = 0;
119

    
120
    if ((addr & 0xf) == 0)
121
        retval = pic_intack_read(isa_pic);
122
//   printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
123

    
124
    return retval;
125
}
126

    
127
static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
128
{
129
    return _PPC_intack_read(addr);
130
}
131

    
132
static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
133
{
134
#ifdef TARGET_WORDS_BIGENDIAN
135
    return bswap16(_PPC_intack_read(addr));
136
#else
137
    return _PPC_intack_read(addr);
138
#endif
139
}
140

    
141
static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
142
{
143
#ifdef TARGET_WORDS_BIGENDIAN
144
    return bswap32(_PPC_intack_read(addr));
145
#else
146
    return _PPC_intack_read(addr);
147
#endif
148
}
149

    
150
static CPUWriteMemoryFunc *PPC_intack_write[] = {
151
    &_PPC_intack_write,
152
    &_PPC_intack_write,
153
    &_PPC_intack_write,
154
};
155

    
156
static CPUReadMemoryFunc *PPC_intack_read[] = {
157
    &PPC_intack_readb,
158
    &PPC_intack_readw,
159
    &PPC_intack_readl,
160
};
161

    
162
/* PowerPC control and status registers */
163
#if 0 // Not used
164
static struct {
165
    /* IDs */
166
    uint32_t veni_devi;
167
    uint32_t revi;
168
    /* Control and status */
169
    uint32_t gcsr;
170
    uint32_t xcfr;
171
    uint32_t ct32;
172
    uint32_t mcsr;
173
    /* General purpose registers */
174
    uint32_t gprg[6];
175
    /* Exceptions */
176
    uint32_t feen;
177
    uint32_t fest;
178
    uint32_t fema;
179
    uint32_t fecl;
180
    uint32_t eeen;
181
    uint32_t eest;
182
    uint32_t eecl;
183
    uint32_t eeint;
184
    uint32_t eemck0;
185
    uint32_t eemck1;
186
    /* Error diagnostic */
187
} XCSR;
188

189
static void PPC_XCSR_writeb (void *opaque,
190
                             target_phys_addr_t addr, uint32_t value)
191
{
192
    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
193
}
194

195
static void PPC_XCSR_writew (void *opaque,
196
                             target_phys_addr_t addr, uint32_t value)
197
{
198
#ifdef TARGET_WORDS_BIGENDIAN
199
    value = bswap16(value);
200
#endif
201
    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
202
}
203

    
204
static void PPC_XCSR_writel (void *opaque,
205
                             target_phys_addr_t addr, uint32_t value)
206
{
207
#ifdef TARGET_WORDS_BIGENDIAN
208
    value = bswap32(value);
209
#endif
210
    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
211
}
212

    
213
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
214
{
215
    uint32_t retval = 0;
216

    
217
    printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
218

    
219
    return retval;
220
}
221

    
222
static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
223
{
224
    uint32_t retval = 0;
225

    
226
    printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
227
#ifdef TARGET_WORDS_BIGENDIAN
228
    retval = bswap16(retval);
229
#endif
230

    
231
    return retval;
232
}
233

    
234
static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
235
{
236
    uint32_t retval = 0;
237

    
238
    printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
239
#ifdef TARGET_WORDS_BIGENDIAN
240
    retval = bswap32(retval);
241
#endif
242

    
243
    return retval;
244
}
245

    
246
static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
247
    &PPC_XCSR_writeb,
248
    &PPC_XCSR_writew,
249
    &PPC_XCSR_writel,
250
};
251

    
252
static CPUReadMemoryFunc *PPC_XCSR_read[] = {
253
    &PPC_XCSR_readb,
254
    &PPC_XCSR_readw,
255
    &PPC_XCSR_readl,
256
};
257
#endif
258

    
259
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
260
typedef struct sysctrl_t {
261
    qemu_irq reset_irq;
262
    m48t59_t *nvram;
263
    uint8_t state;
264
    uint8_t syscontrol;
265
    uint8_t fake_io[2];
266
    int contiguous_map;
267
    int endian;
268
} sysctrl_t;
269

    
270
enum {
271
    STATE_HARDFILE = 0x01,
272
};
273

    
274
static sysctrl_t *sysctrl;
275

    
276
static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
277
{
278
    sysctrl_t *sysctrl = opaque;
279

    
280
    PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
281
                   val);
282
    sysctrl->fake_io[addr - 0x0398] = val;
283
}
284

    
285
static uint32_t PREP_io_read (void *opaque, uint32_t addr)
286
{
287
    sysctrl_t *sysctrl = opaque;
288

    
289
    PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
290
                   sysctrl->fake_io[addr - 0x0398]);
291
    return sysctrl->fake_io[addr - 0x0398];
292
}
293

    
294
static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
295
{
296
    sysctrl_t *sysctrl = opaque;
297

    
298
    PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
299
                   addr - PPC_IO_BASE, val);
300
    switch (addr) {
301
    case 0x0092:
302
        /* Special port 92 */
303
        /* Check soft reset asked */
304
        if (val & 0x01) {
305
            qemu_irq_raise(sysctrl->reset_irq);
306
        } else {
307
            qemu_irq_lower(sysctrl->reset_irq);
308
        }
309
        /* Check LE mode */
310
        if (val & 0x02) {
311
            sysctrl->endian = 1;
312
        } else {
313
            sysctrl->endian = 0;
314
        }
315
        break;
316
    case 0x0800:
317
        /* Motorola CPU configuration register : read-only */
318
        break;
319
    case 0x0802:
320
        /* Motorola base module feature register : read-only */
321
        break;
322
    case 0x0803:
323
        /* Motorola base module status register : read-only */
324
        break;
325
    case 0x0808:
326
        /* Hardfile light register */
327
        if (val & 1)
328
            sysctrl->state |= STATE_HARDFILE;
329
        else
330
            sysctrl->state &= ~STATE_HARDFILE;
331
        break;
332
    case 0x0810:
333
        /* Password protect 1 register */
334
        if (sysctrl->nvram != NULL)
335
            m48t59_toggle_lock(sysctrl->nvram, 1);
336
        break;
337
    case 0x0812:
338
        /* Password protect 2 register */
339
        if (sysctrl->nvram != NULL)
340
            m48t59_toggle_lock(sysctrl->nvram, 2);
341
        break;
342
    case 0x0814:
343
        /* L2 invalidate register */
344
        //        tlb_flush(first_cpu, 1);
345
        break;
346
    case 0x081C:
347
        /* system control register */
348
        sysctrl->syscontrol = val & 0x0F;
349
        break;
350
    case 0x0850:
351
        /* I/O map type register */
352
        sysctrl->contiguous_map = val & 0x01;
353
        break;
354
    default:
355
        printf("ERROR: unaffected IO port write: %04" PRIx32
356
               " => %02" PRIx32"\n", addr, val);
357
        break;
358
    }
359
}
360

    
361
static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
362
{
363
    sysctrl_t *sysctrl = opaque;
364
    uint32_t retval = 0xFF;
365

    
366
    switch (addr) {
367
    case 0x0092:
368
        /* Special port 92 */
369
        retval = 0x00;
370
        break;
371
    case 0x0800:
372
        /* Motorola CPU configuration register */
373
        retval = 0xEF; /* MPC750 */
374
        break;
375
    case 0x0802:
376
        /* Motorola Base module feature register */
377
        retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
378
        break;
379
    case 0x0803:
380
        /* Motorola base module status register */
381
        retval = 0xE0; /* Standard MPC750 */
382
        break;
383
    case 0x080C:
384
        /* Equipment present register:
385
         *  no L2 cache
386
         *  no upgrade processor
387
         *  no cards in PCI slots
388
         *  SCSI fuse is bad
389
         */
390
        retval = 0x3C;
391
        break;
392
    case 0x0810:
393
        /* Motorola base module extended feature register */
394
        retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
395
        break;
396
    case 0x0814:
397
        /* L2 invalidate: don't care */
398
        break;
399
    case 0x0818:
400
        /* Keylock */
401
        retval = 0x00;
402
        break;
403
    case 0x081C:
404
        /* system control register
405
         * 7 - 6 / 1 - 0: L2 cache enable
406
         */
407
        retval = sysctrl->syscontrol;
408
        break;
409
    case 0x0823:
410
        /* */
411
        retval = 0x03; /* no L2 cache */
412
        break;
413
    case 0x0850:
414
        /* I/O map type register */
415
        retval = sysctrl->contiguous_map;
416
        break;
417
    default:
418
        printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
419
        break;
420
    }
421
    PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
422
                   addr - PPC_IO_BASE, retval);
423

    
424
    return retval;
425
}
426

    
427
static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
428
                                                         target_phys_addr_t
429
                                                         addr)
430
{
431
    if (sysctrl->contiguous_map == 0) {
432
        /* 64 KB contiguous space for IOs */
433
        addr &= 0xFFFF;
434
    } else {
435
        /* 8 MB non-contiguous space for IOs */
436
        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
437
    }
438

    
439
    return addr;
440
}
441

    
442
static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
443
                                uint32_t value)
444
{
445
    sysctrl_t *sysctrl = opaque;
446

    
447
    addr = prep_IO_address(sysctrl, addr);
448
    cpu_outb(NULL, addr, value);
449
}
450

    
451
static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
452
{
453
    sysctrl_t *sysctrl = opaque;
454
    uint32_t ret;
455

    
456
    addr = prep_IO_address(sysctrl, addr);
457
    ret = cpu_inb(NULL, addr);
458

    
459
    return ret;
460
}
461

    
462
static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
463
                                uint32_t value)
464
{
465
    sysctrl_t *sysctrl = opaque;
466

    
467
    addr = prep_IO_address(sysctrl, addr);
468
#ifdef TARGET_WORDS_BIGENDIAN
469
    value = bswap16(value);
470
#endif
471
    PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
472
    cpu_outw(NULL, addr, value);
473
}
474

    
475
static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
476
{
477
    sysctrl_t *sysctrl = opaque;
478
    uint32_t ret;
479

    
480
    addr = prep_IO_address(sysctrl, addr);
481
    ret = cpu_inw(NULL, addr);
482
#ifdef TARGET_WORDS_BIGENDIAN
483
    ret = bswap16(ret);
484
#endif
485
    PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
486

    
487
    return ret;
488
}
489

    
490
static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
491
                                uint32_t value)
492
{
493
    sysctrl_t *sysctrl = opaque;
494

    
495
    addr = prep_IO_address(sysctrl, addr);
496
#ifdef TARGET_WORDS_BIGENDIAN
497
    value = bswap32(value);
498
#endif
499
    PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
500
    cpu_outl(NULL, addr, value);
501
}
502

    
503
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
504
{
505
    sysctrl_t *sysctrl = opaque;
506
    uint32_t ret;
507

    
508
    addr = prep_IO_address(sysctrl, addr);
509
    ret = cpu_inl(NULL, addr);
510
#ifdef TARGET_WORDS_BIGENDIAN
511
    ret = bswap32(ret);
512
#endif
513
    PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
514

    
515
    return ret;
516
}
517

    
518
static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
519
    &PPC_prep_io_writeb,
520
    &PPC_prep_io_writew,
521
    &PPC_prep_io_writel,
522
};
523

    
524
static CPUReadMemoryFunc *PPC_prep_io_read[] = {
525
    &PPC_prep_io_readb,
526
    &PPC_prep_io_readw,
527
    &PPC_prep_io_readl,
528
};
529

    
530
#define NVRAM_SIZE        0x2000
531

    
532
/* PowerPC PREP hardware initialisation */
533
static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
534
                           const char *boot_device,
535
                           const char *kernel_filename,
536
                           const char *kernel_cmdline,
537
                           const char *initrd_filename,
538
                           const char *cpu_model)
539
{
540
    CPUState *env = NULL, *envs[MAX_CPUS];
541
    char buf[1024];
542
    nvram_t nvram;
543
    m48t59_t *m48t59;
544
    int PPC_io_memory;
545
    int linux_boot, i, nb_nics1, bios_size;
546
    ram_addr_t ram_offset, bios_offset;
547
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
548
    PCIBus *pci_bus;
549
    qemu_irq *i8259;
550
    int ppc_boot_device;
551
    int index;
552
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
553
    BlockDriverState *fd[MAX_FD];
554

    
555
    sysctrl = qemu_mallocz(sizeof(sysctrl_t));
556

    
557
    linux_boot = (kernel_filename != NULL);
558

    
559
    /* init CPUs */
560
    if (cpu_model == NULL)
561
        cpu_model = "default";
562
    for (i = 0; i < smp_cpus; i++) {
563
        env = cpu_init(cpu_model);
564
        if (!env) {
565
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
566
            exit(1);
567
        }
568
        if (env->flags & POWERPC_FLAG_RTC_CLK) {
569
            /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
570
            cpu_ppc_tb_init(env, 7812500UL);
571
        } else {
572
            /* Set time-base frequency to 100 Mhz */
573
            cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
574
        }
575
        qemu_register_reset(&cpu_ppc_reset, env);
576
        envs[i] = env;
577
    }
578

    
579
    /* allocate RAM */
580
    ram_offset = qemu_ram_alloc(ram_size);
581
    cpu_register_physical_memory(0, ram_size, ram_offset);
582

    
583
    /* allocate and load BIOS */
584
    bios_offset = qemu_ram_alloc(BIOS_SIZE);
585
    if (bios_name == NULL)
586
        bios_name = BIOS_FILENAME;
587
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
588
    bios_size = get_image_size(buf);
589
    if (bios_size > 0 && bios_size <= BIOS_SIZE) {
590
        target_phys_addr_t bios_addr;
591
        bios_size = (bios_size + 0xfff) & ~0xfff;
592
        bios_addr = (uint32_t)(-bios_size);
593
        cpu_register_physical_memory(bios_addr, bios_size,
594
                                     bios_offset | IO_MEM_ROM);
595
        bios_size = load_image_targphys(buf, bios_addr, bios_size);
596
    }
597
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
598
        cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
599
        exit(1);
600
    }
601
    if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
602
        cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
603
    }
604

    
605
    if (linux_boot) {
606
        kernel_base = KERNEL_LOAD_ADDR;
607
        /* now we can load the kernel */
608
        kernel_size = load_image_targphys(kernel_filename, kernel_base,
609
                                          ram_size - kernel_base);
610
        if (kernel_size < 0) {
611
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
612
                      kernel_filename);
613
            exit(1);
614
        }
615
        /* load initrd */
616
        if (initrd_filename) {
617
            initrd_base = INITRD_LOAD_ADDR;
618
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
619
                                              ram_size - initrd_base);
620
            if (initrd_size < 0) {
621
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
622
                          initrd_filename);
623
                exit(1);
624
            }
625
        } else {
626
            initrd_base = 0;
627
            initrd_size = 0;
628
        }
629
        ppc_boot_device = 'm';
630
    } else {
631
        kernel_base = 0;
632
        kernel_size = 0;
633
        initrd_base = 0;
634
        initrd_size = 0;
635
        ppc_boot_device = '\0';
636
        /* For now, OHW cannot boot from the network. */
637
        for (i = 0; boot_device[i] != '\0'; i++) {
638
            if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
639
                ppc_boot_device = boot_device[i];
640
                break;
641
            }
642
        }
643
        if (ppc_boot_device == '\0') {
644
            fprintf(stderr, "No valid boot device for Mac99 machine\n");
645
            exit(1);
646
        }
647
    }
648

    
649
    isa_mem_base = 0xc0000000;
650
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
651
        cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
652
        exit(1);
653
    }
654
    i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
655
    pci_bus = pci_prep_init(i8259);
656
    //    pci_bus = i440fx_init();
657
    /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
658
    PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
659
                                           PPC_prep_io_write, sysctrl);
660
    cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
661

    
662
    /* init basic PC hardware */
663
    pci_vga_init(pci_bus, vga_ram_size, 0, 0);
664
    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
665
    //    pit = pit_init(0x40, i8259[0]);
666
    rtc_init(0x70, i8259[8], 2000);
667

    
668
    serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
669
    nb_nics1 = nb_nics;
670
    if (nb_nics1 > NE2000_NB_MAX)
671
        nb_nics1 = NE2000_NB_MAX;
672
    for(i = 0; i < nb_nics1; i++) {
673
        if (nd_table[i].model == NULL) {
674
            nd_table[i].model = "ne2k_isa";
675
        }
676
        if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
677
            isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
678
        } else {
679
            pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
680
        }
681
    }
682

    
683
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
684
        fprintf(stderr, "qemu: too many IDE bus\n");
685
        exit(1);
686
    }
687

    
688
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
689
        index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
690
        if (index != -1)
691
            hd[i] = drives_table[index].bdrv;
692
        else
693
            hd[i] = NULL;
694
    }
695

    
696
    for(i = 0; i < MAX_IDE_BUS; i++) {
697
        isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
698
                     hd[2 * i],
699
                     hd[2 * i + 1]);
700
    }
701
    i8042_init(i8259[1], i8259[12], 0x60);
702
    DMA_init(1);
703
    //    AUD_init();
704
    //    SB16_init();
705

    
706
    for(i = 0; i < MAX_FD; i++) {
707
        index = drive_get_index(IF_FLOPPY, 0, i);
708
        if (index != -1)
709
            fd[i] = drives_table[index].bdrv;
710
        else
711
            fd[i] = NULL;
712
    }
713
    fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
714

    
715
    /* Register speaker port */
716
    register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
717
    register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
718
    /* Register fake IO ports for PREP */
719
    sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
720
    register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
721
    register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
722
    /* System control ports */
723
    register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
724
    register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
725
    register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
726
    register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
727
    /* PCI intack location */
728
    PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
729
                                           PPC_intack_write, NULL);
730
    cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
731
    /* PowerPC control and status register group */
732
#if 0
733
    PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
734
                                           NULL);
735
    cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
736
#endif
737

    
738
    if (usb_enabled) {
739
        usb_ohci_init_pci(pci_bus, 3, -1);
740
    }
741

    
742
    m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
743
    if (m48t59 == NULL)
744
        return;
745
    sysctrl->nvram = m48t59;
746

    
747
    /* Initialise NVRAM */
748
    nvram.opaque = m48t59;
749
    nvram.read_fn = &m48t59_read;
750
    nvram.write_fn = &m48t59_write;
751
    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
752
                         kernel_base, kernel_size,
753
                         kernel_cmdline,
754
                         initrd_base, initrd_size,
755
                         /* XXX: need an option to load a NVRAM image */
756
                         0,
757
                         graphic_width, graphic_height, graphic_depth);
758

    
759
    /* Special port to get debug messages from Open-Firmware */
760
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
761
}
762

    
763
QEMUMachine prep_machine = {
764
    .name = "prep",
765
    .desc = "PowerPC PREP platform",
766
    .init = ppc_prep_init,
767
    .ram_require = BIOS_SIZE + VGA_RAM_SIZE,
768
    .max_cpus = MAX_CPUS,
769
};