Revision b5dc7732 target-mips/cpu.h
| b/target-mips/cpu.h | ||
|---|---|---|
| 134 | 134 |
#define MIPS_TC_MAX 5 |
| 135 | 135 |
#define MIPS_DSP_ACC 4 |
| 136 | 136 |
|
| 137 |
typedef struct TCState TCState; |
|
| 138 |
struct TCState {
|
|
| 139 |
target_ulong gpr[32]; |
|
| 140 |
target_ulong PC; |
|
| 141 |
target_ulong HI[MIPS_DSP_ACC]; |
|
| 142 |
target_ulong LO[MIPS_DSP_ACC]; |
|
| 143 |
target_ulong ACX[MIPS_DSP_ACC]; |
|
| 144 |
target_ulong DSPControl; |
|
| 145 |
int32_t CP0_TCStatus; |
|
| 146 |
#define CP0TCSt_TCU3 31 |
|
| 147 |
#define CP0TCSt_TCU2 30 |
|
| 148 |
#define CP0TCSt_TCU1 29 |
|
| 149 |
#define CP0TCSt_TCU0 28 |
|
| 150 |
#define CP0TCSt_TMX 27 |
|
| 151 |
#define CP0TCSt_RNST 23 |
|
| 152 |
#define CP0TCSt_TDS 21 |
|
| 153 |
#define CP0TCSt_DT 20 |
|
| 154 |
#define CP0TCSt_DA 15 |
|
| 155 |
#define CP0TCSt_A 13 |
|
| 156 |
#define CP0TCSt_TKSU 11 |
|
| 157 |
#define CP0TCSt_IXMT 10 |
|
| 158 |
#define CP0TCSt_TASID 0 |
|
| 159 |
int32_t CP0_TCBind; |
|
| 160 |
#define CP0TCBd_CurTC 21 |
|
| 161 |
#define CP0TCBd_TBE 17 |
|
| 162 |
#define CP0TCBd_CurVPE 0 |
|
| 163 |
target_ulong CP0_TCHalt; |
|
| 164 |
target_ulong CP0_TCContext; |
|
| 165 |
target_ulong CP0_TCSchedule; |
|
| 166 |
target_ulong CP0_TCScheFBack; |
|
| 167 |
int32_t CP0_Debug_tcstatus; |
|
| 168 |
}; |
|
| 169 |
|
|
| 137 | 170 |
typedef struct CPUMIPSState CPUMIPSState; |
| 138 | 171 |
struct CPUMIPSState {
|
| 139 |
/* General integer registers */ |
|
| 140 |
target_ulong gpr[MIPS_SHADOW_SET_MAX][32]; |
|
| 141 |
/* Special registers */ |
|
| 142 |
target_ulong PC[MIPS_TC_MAX]; |
|
| 172 |
TCState active_tc; |
|
| 173 |
|
|
| 143 | 174 |
/* temporary hack for FP globals */ |
| 144 | 175 |
#ifndef USE_HOST_FLOAT_REGS |
| 145 | 176 |
fpr_t ft0; |
| 146 | 177 |
fpr_t ft1; |
| 147 | 178 |
fpr_t ft2; |
| 148 | 179 |
#endif |
| 149 |
target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; |
|
| 150 |
target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; |
|
| 151 |
target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC]; |
|
| 152 |
target_ulong DSPControl[MIPS_TC_MAX]; |
|
| 153 |
|
|
| 154 | 180 |
CPUMIPSMVPContext *mvp; |
| 155 | 181 |
CPUMIPSTLBContext *tlb; |
| 156 | 182 |
CPUMIPSFPUContext *fpu; |
| 157 | 183 |
uint32_t current_tc; |
| 158 |
target_ulong *current_tc_gprs; |
|
| 159 |
target_ulong *current_tc_hi; |
|
| 160 | 184 |
|
| 161 | 185 |
uint32_t SEGBITS; |
| 162 | 186 |
target_ulong SEGMask; |
| ... | ... | |
| 206 | 230 |
#define CP0VPEOpt_DWX1 1 |
| 207 | 231 |
#define CP0VPEOpt_DWX0 0 |
| 208 | 232 |
target_ulong CP0_EntryLo0; |
| 209 |
int32_t CP0_TCStatus[MIPS_TC_MAX]; |
|
| 210 |
#define CP0TCSt_TCU3 31 |
|
| 211 |
#define CP0TCSt_TCU2 30 |
|
| 212 |
#define CP0TCSt_TCU1 29 |
|
| 213 |
#define CP0TCSt_TCU0 28 |
|
| 214 |
#define CP0TCSt_TMX 27 |
|
| 215 |
#define CP0TCSt_RNST 23 |
|
| 216 |
#define CP0TCSt_TDS 21 |
|
| 217 |
#define CP0TCSt_DT 20 |
|
| 218 |
#define CP0TCSt_DA 15 |
|
| 219 |
#define CP0TCSt_A 13 |
|
| 220 |
#define CP0TCSt_TKSU 11 |
|
| 221 |
#define CP0TCSt_IXMT 10 |
|
| 222 |
#define CP0TCSt_TASID 0 |
|
| 223 |
int32_t CP0_TCBind[MIPS_TC_MAX]; |
|
| 224 |
#define CP0TCBd_CurTC 21 |
|
| 225 |
#define CP0TCBd_TBE 17 |
|
| 226 |
#define CP0TCBd_CurVPE 0 |
|
| 227 |
target_ulong CP0_TCHalt[MIPS_TC_MAX]; |
|
| 228 |
target_ulong CP0_TCContext[MIPS_TC_MAX]; |
|
| 229 |
target_ulong CP0_TCSchedule[MIPS_TC_MAX]; |
|
| 230 |
target_ulong CP0_TCScheFBack[MIPS_TC_MAX]; |
|
| 231 | 233 |
target_ulong CP0_EntryLo1; |
| 232 | 234 |
target_ulong CP0_Context; |
| 233 | 235 |
int32_t CP0_PageMask; |
| ... | ... | |
| 398 | 400 |
#define CP0DB_DDBL 2 |
| 399 | 401 |
#define CP0DB_DBp 1 |
| 400 | 402 |
#define CP0DB_DSS 0 |
| 401 |
int32_t CP0_Debug_tcstatus[MIPS_TC_MAX]; |
|
| 402 | 403 |
target_ulong CP0_DEPC; |
| 403 | 404 |
int32_t CP0_Performance0; |
| 404 | 405 |
int32_t CP0_TagLo; |
| ... | ... | |
| 407 | 408 |
int32_t CP0_DataHi; |
| 408 | 409 |
target_ulong CP0_ErrorEPC; |
| 409 | 410 |
int32_t CP0_DESAVE; |
| 411 |
/* We waste some space so we can handle shadow registers like TCs. */ |
|
| 412 |
TCState tcs[MIPS_SHADOW_SET_MAX]; |
|
| 410 | 413 |
/* Qemu */ |
| 411 | 414 |
int interrupt_request; |
| 412 | 415 |
int error_code; |
| ... | ... | |
| 501 | 504 |
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
| 502 | 505 |
{
|
| 503 | 506 |
if (newsp) |
| 504 |
env->gpr[env->current_tc][29] = newsp;
|
|
| 505 |
env->gpr[env->current_tc][7] = 0;
|
|
| 506 |
env->gpr[env->current_tc][2] = 0;
|
|
| 507 |
env->active_tc.gpr[29] = newsp;
|
|
| 508 |
env->active_tc.gpr[7] = 0;
|
|
| 509 |
env->active_tc.gpr[2] = 0;
|
|
| 507 | 510 |
} |
| 508 | 511 |
#endif |
| 509 | 512 |
|
Also available in: Unified diff