Revision b5dc7732 target-mips/helper.c
| b/target-mips/helper.c | ||
|---|---|---|
| 241 | 241 |
cpu_dump_state(env, logfile, fprintf, 0); |
| 242 | 242 |
#endif |
| 243 | 243 |
fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", |
| 244 |
__func__, env->PC[env->current_tc], address, rw, mmu_idx, is_softmmu);
|
|
| 244 |
__func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
|
|
| 245 | 245 |
} |
| 246 | 246 |
|
| 247 | 247 |
rw &= 1; |
| ... | ... | |
| 370 | 370 |
name = excp_names[env->exception_index]; |
| 371 | 371 |
|
| 372 | 372 |
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", |
| 373 |
__func__, env->PC[env->current_tc], env->CP0_EPC, name);
|
|
| 373 |
__func__, env->active_tc.PC, env->CP0_EPC, name);
|
|
| 374 | 374 |
} |
| 375 | 375 |
if (env->exception_index == EXCP_EXT_INTERRUPT && |
| 376 | 376 |
(env->hflags & MIPS_HFLAG_DM)) |
| ... | ... | |
| 384 | 384 |
* (but we assume the pc has always been updated during |
| 385 | 385 |
* code translation). |
| 386 | 386 |
*/ |
| 387 |
env->CP0_DEPC = env->PC[env->current_tc];
|
|
| 387 |
env->CP0_DEPC = env->active_tc.PC;
|
|
| 388 | 388 |
goto enter_debug_mode; |
| 389 | 389 |
case EXCP_DINT: |
| 390 | 390 |
env->CP0_Debug |= 1 << CP0DB_DINT; |
| ... | ... | |
| 404 | 404 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 405 | 405 |
/* If the exception was raised from a delay slot, |
| 406 | 406 |
come back to the jump. */ |
| 407 |
env->CP0_DEPC = env->PC[env->current_tc] - 4;
|
|
| 407 |
env->CP0_DEPC = env->active_tc.PC - 4;
|
|
| 408 | 408 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 409 | 409 |
} else {
|
| 410 |
env->CP0_DEPC = env->PC[env->current_tc];
|
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| 410 |
env->CP0_DEPC = env->active_tc.PC;
|
|
| 411 | 411 |
} |
| 412 | 412 |
enter_debug_mode: |
| 413 | 413 |
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
| ... | ... | |
| 415 | 415 |
/* EJTAG probe trap enable is not implemented... */ |
| 416 | 416 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
| 417 | 417 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
| 418 |
env->PC[env->current_tc] = (int32_t)0xBFC00480;
|
|
| 418 |
env->active_tc.PC = (int32_t)0xBFC00480;
|
|
| 419 | 419 |
break; |
| 420 | 420 |
case EXCP_RESET: |
| 421 | 421 |
cpu_reset(env); |
| ... | ... | |
| 430 | 430 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 431 | 431 |
/* If the exception was raised from a delay slot, |
| 432 | 432 |
come back to the jump. */ |
| 433 |
env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
|
|
| 433 |
env->CP0_ErrorEPC = env->active_tc.PC - 4;
|
|
| 434 | 434 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 435 | 435 |
} else {
|
| 436 |
env->CP0_ErrorEPC = env->PC[env->current_tc];
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| 436 |
env->CP0_ErrorEPC = env->active_tc.PC;
|
|
| 437 | 437 |
} |
| 438 | 438 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
| 439 | 439 |
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
| 440 | 440 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
| 441 | 441 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
| 442 | 442 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
| 443 |
env->PC[env->current_tc] = (int32_t)0xBFC00000;
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|
| 443 |
env->active_tc.PC = (int32_t)0xBFC00000;
|
|
| 444 | 444 |
break; |
| 445 | 445 |
case EXCP_EXT_INTERRUPT: |
| 446 | 446 |
cause = 0; |
| ... | ... | |
| 545 | 545 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 546 | 546 |
/* If the exception was raised from a delay slot, |
| 547 | 547 |
come back to the jump. */ |
| 548 |
env->CP0_EPC = env->PC[env->current_tc] - 4;
|
|
| 548 |
env->CP0_EPC = env->active_tc.PC - 4;
|
|
| 549 | 549 |
env->CP0_Cause |= (1 << CP0Ca_BD); |
| 550 | 550 |
} else {
|
| 551 |
env->CP0_EPC = env->PC[env->current_tc];
|
|
| 551 |
env->CP0_EPC = env->active_tc.PC;
|
|
| 552 | 552 |
env->CP0_Cause &= ~(1 << CP0Ca_BD); |
| 553 | 553 |
} |
| 554 | 554 |
env->CP0_Status |= (1 << CP0St_EXL); |
| ... | ... | |
| 557 | 557 |
} |
| 558 | 558 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 559 | 559 |
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
| 560 |
env->PC[env->current_tc] = (int32_t)0xBFC00200;
|
|
| 560 |
env->active_tc.PC = (int32_t)0xBFC00200;
|
|
| 561 | 561 |
} else {
|
| 562 |
env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
|
|
| 562 |
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
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| 563 | 563 |
} |
| 564 |
env->PC[env->current_tc] += offset;
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| 564 |
env->active_tc.PC += offset;
|
|
| 565 | 565 |
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
| 566 | 566 |
break; |
| 567 | 567 |
default: |
| ... | ... | |
| 575 | 575 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
| 576 | 576 |
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
| 577 | 577 |
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
| 578 |
__func__, env->PC[env->current_tc], env->CP0_EPC, cause,
|
|
| 578 |
__func__, env->active_tc.PC, env->CP0_EPC, cause,
|
|
| 579 | 579 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
| 580 | 580 |
env->CP0_DEPC); |
| 581 | 581 |
} |
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