Statistics
| Branch: | Revision:

root / target-i386 / svm.h @ b6abf97d

History | View | Annotate | Download (10.1 kB)

1 239fbd86 ths
#ifndef __SVM_H
2 239fbd86 ths
#define __SVM_H
3 239fbd86 ths
4 239fbd86 ths
enum {
5 239fbd86 ths
        /* We shift all the intercept bits so we can OR them with the
6 239fbd86 ths
           TB flags later on */
7 239fbd86 ths
        INTERCEPT_INTR = HF_HIF_SHIFT,
8 239fbd86 ths
        INTERCEPT_NMI,
9 239fbd86 ths
        INTERCEPT_SMI,
10 239fbd86 ths
        INTERCEPT_INIT,
11 239fbd86 ths
        INTERCEPT_VINTR,
12 239fbd86 ths
        INTERCEPT_SELECTIVE_CR0,
13 239fbd86 ths
        INTERCEPT_STORE_IDTR,
14 239fbd86 ths
        INTERCEPT_STORE_GDTR,
15 239fbd86 ths
        INTERCEPT_STORE_LDTR,
16 239fbd86 ths
        INTERCEPT_STORE_TR,
17 239fbd86 ths
        INTERCEPT_LOAD_IDTR,
18 239fbd86 ths
        INTERCEPT_LOAD_GDTR,
19 239fbd86 ths
        INTERCEPT_LOAD_LDTR,
20 239fbd86 ths
        INTERCEPT_LOAD_TR,
21 239fbd86 ths
        INTERCEPT_RDTSC,
22 239fbd86 ths
        INTERCEPT_RDPMC,
23 239fbd86 ths
        INTERCEPT_PUSHF,
24 239fbd86 ths
        INTERCEPT_POPF,
25 239fbd86 ths
        INTERCEPT_CPUID,
26 239fbd86 ths
        INTERCEPT_RSM,
27 239fbd86 ths
        INTERCEPT_IRET,
28 239fbd86 ths
        INTERCEPT_INTn,
29 239fbd86 ths
        INTERCEPT_INVD,
30 239fbd86 ths
        INTERCEPT_PAUSE,
31 239fbd86 ths
        INTERCEPT_HLT,
32 239fbd86 ths
        INTERCEPT_INVLPG,
33 239fbd86 ths
        INTERCEPT_INVLPGA,
34 239fbd86 ths
        INTERCEPT_IOIO_PROT,
35 239fbd86 ths
        INTERCEPT_MSR_PROT,
36 239fbd86 ths
        INTERCEPT_TASK_SWITCH,
37 239fbd86 ths
        INTERCEPT_FERR_FREEZE,
38 239fbd86 ths
        INTERCEPT_SHUTDOWN,
39 239fbd86 ths
        INTERCEPT_VMRUN,
40 239fbd86 ths
        INTERCEPT_VMMCALL,
41 239fbd86 ths
        INTERCEPT_VMLOAD,
42 239fbd86 ths
        INTERCEPT_VMSAVE,
43 239fbd86 ths
        INTERCEPT_STGI,
44 239fbd86 ths
        INTERCEPT_CLGI,
45 239fbd86 ths
        INTERCEPT_SKINIT,
46 239fbd86 ths
        INTERCEPT_RDTSCP,
47 239fbd86 ths
        INTERCEPT_ICEBP,
48 239fbd86 ths
        INTERCEPT_WBINVD,
49 239fbd86 ths
};
50 239fbd86 ths
/* This is not really an intercept but rather a placeholder to
51 239fbd86 ths
   show that we are in an SVM (just like a hidden flag, but keeps the
52 239fbd86 ths
   TBs clean) */
53 239fbd86 ths
#define INTERCEPT_SVM 63
54 239fbd86 ths
#define INTERCEPT_SVM_MASK (1ULL << INTERCEPT_SVM)
55 239fbd86 ths
56 239fbd86 ths
struct __attribute__ ((__packed__)) vmcb_control_area {
57 239fbd86 ths
        uint16_t intercept_cr_read;
58 239fbd86 ths
        uint16_t intercept_cr_write;
59 239fbd86 ths
        uint16_t intercept_dr_read;
60 239fbd86 ths
        uint16_t intercept_dr_write;
61 239fbd86 ths
        uint32_t intercept_exceptions;
62 239fbd86 ths
        uint64_t intercept;
63 239fbd86 ths
        uint8_t reserved_1[44];
64 239fbd86 ths
        uint64_t iopm_base_pa;
65 239fbd86 ths
        uint64_t msrpm_base_pa;
66 239fbd86 ths
        uint64_t tsc_offset;
67 239fbd86 ths
        uint32_t asid;
68 239fbd86 ths
        uint8_t tlb_ctl;
69 239fbd86 ths
        uint8_t reserved_2[3];
70 239fbd86 ths
        uint32_t int_ctl;
71 239fbd86 ths
        uint32_t int_vector;
72 239fbd86 ths
        uint32_t int_state;
73 239fbd86 ths
        uint8_t reserved_3[4];
74 b8b6a50b bellard
        uint64_t exit_code;
75 239fbd86 ths
        uint64_t exit_info_1;
76 239fbd86 ths
        uint64_t exit_info_2;
77 239fbd86 ths
        uint32_t exit_int_info;
78 239fbd86 ths
        uint32_t exit_int_info_err;
79 239fbd86 ths
        uint64_t nested_ctl;
80 239fbd86 ths
        uint8_t reserved_4[16];
81 239fbd86 ths
        uint32_t event_inj;
82 239fbd86 ths
        uint32_t event_inj_err;
83 239fbd86 ths
        uint64_t nested_cr3;
84 239fbd86 ths
        uint64_t lbr_ctl;
85 239fbd86 ths
        uint8_t reserved_5[832];
86 239fbd86 ths
};
87 239fbd86 ths
88 239fbd86 ths
89 239fbd86 ths
#define TLB_CONTROL_DO_NOTHING 0
90 239fbd86 ths
#define TLB_CONTROL_FLUSH_ALL_ASID 1
91 239fbd86 ths
92 239fbd86 ths
#define V_TPR_MASK 0x0f
93 239fbd86 ths
94 239fbd86 ths
#define V_IRQ_SHIFT 8
95 239fbd86 ths
#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
96 239fbd86 ths
97 239fbd86 ths
#define V_INTR_PRIO_SHIFT 16
98 239fbd86 ths
#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
99 239fbd86 ths
100 239fbd86 ths
#define V_IGN_TPR_SHIFT 20
101 239fbd86 ths
#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
102 239fbd86 ths
103 239fbd86 ths
#define V_INTR_MASKING_SHIFT 24
104 239fbd86 ths
#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
105 239fbd86 ths
106 239fbd86 ths
#define SVM_INTERRUPT_SHADOW_MASK 1
107 239fbd86 ths
108 239fbd86 ths
#define SVM_IOIO_STR_SHIFT 2
109 239fbd86 ths
#define SVM_IOIO_REP_SHIFT 3
110 239fbd86 ths
#define SVM_IOIO_SIZE_SHIFT 4
111 239fbd86 ths
#define SVM_IOIO_ASIZE_SHIFT 7
112 239fbd86 ths
113 239fbd86 ths
#define SVM_IOIO_TYPE_MASK 1
114 239fbd86 ths
#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
115 239fbd86 ths
#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
116 239fbd86 ths
#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
117 239fbd86 ths
#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
118 239fbd86 ths
119 239fbd86 ths
struct __attribute__ ((__packed__)) vmcb_seg {
120 239fbd86 ths
        uint16_t selector;
121 239fbd86 ths
        uint16_t attrib;
122 239fbd86 ths
        uint32_t limit;
123 239fbd86 ths
        uint64_t base;
124 239fbd86 ths
};
125 239fbd86 ths
126 239fbd86 ths
struct __attribute__ ((__packed__)) vmcb_save_area {
127 239fbd86 ths
        struct vmcb_seg es;
128 239fbd86 ths
        struct vmcb_seg cs;
129 239fbd86 ths
        struct vmcb_seg ss;
130 239fbd86 ths
        struct vmcb_seg ds;
131 239fbd86 ths
        struct vmcb_seg fs;
132 239fbd86 ths
        struct vmcb_seg gs;
133 239fbd86 ths
        struct vmcb_seg gdtr;
134 239fbd86 ths
        struct vmcb_seg ldtr;
135 239fbd86 ths
        struct vmcb_seg idtr;
136 239fbd86 ths
        struct vmcb_seg tr;
137 239fbd86 ths
        uint8_t reserved_1[43];
138 239fbd86 ths
        uint8_t cpl;
139 239fbd86 ths
        uint8_t reserved_2[4];
140 239fbd86 ths
        uint64_t efer;
141 239fbd86 ths
        uint8_t reserved_3[112];
142 239fbd86 ths
        uint64_t cr4;
143 239fbd86 ths
        uint64_t cr3;
144 239fbd86 ths
        uint64_t cr0;
145 239fbd86 ths
        uint64_t dr7;
146 239fbd86 ths
        uint64_t dr6;
147 239fbd86 ths
        uint64_t rflags;
148 239fbd86 ths
        uint64_t rip;
149 239fbd86 ths
        uint8_t reserved_4[88];
150 239fbd86 ths
        uint64_t rsp;
151 239fbd86 ths
        uint8_t reserved_5[24];
152 239fbd86 ths
        uint64_t rax;
153 239fbd86 ths
        uint64_t star;
154 239fbd86 ths
        uint64_t lstar;
155 239fbd86 ths
        uint64_t cstar;
156 239fbd86 ths
        uint64_t sfmask;
157 239fbd86 ths
        uint64_t kernel_gs_base;
158 239fbd86 ths
        uint64_t sysenter_cs;
159 239fbd86 ths
        uint64_t sysenter_esp;
160 239fbd86 ths
        uint64_t sysenter_eip;
161 239fbd86 ths
        uint64_t cr2;
162 239fbd86 ths
        /* qemu: cr8 added to reuse this as hsave */
163 239fbd86 ths
        uint64_t cr8;
164 239fbd86 ths
        uint8_t reserved_6[32 - 8]; /* originally 32 */
165 239fbd86 ths
        uint64_t g_pat;
166 239fbd86 ths
        uint64_t dbgctl;
167 239fbd86 ths
        uint64_t br_from;
168 239fbd86 ths
        uint64_t br_to;
169 239fbd86 ths
        uint64_t last_excp_from;
170 239fbd86 ths
        uint64_t last_excp_to;
171 239fbd86 ths
};
172 239fbd86 ths
173 239fbd86 ths
struct __attribute__ ((__packed__)) vmcb {
174 239fbd86 ths
        struct vmcb_control_area control;
175 239fbd86 ths
        struct vmcb_save_area save;
176 239fbd86 ths
};
177 239fbd86 ths
178 239fbd86 ths
#define SVM_CPUID_FEATURE_SHIFT 2
179 239fbd86 ths
#define SVM_CPUID_FUNC 0x8000000a
180 239fbd86 ths
181 239fbd86 ths
#define MSR_EFER_SVME_MASK (1ULL << 12)
182 239fbd86 ths
183 239fbd86 ths
#define SVM_SELECTOR_S_SHIFT 4
184 239fbd86 ths
#define SVM_SELECTOR_DPL_SHIFT 5
185 239fbd86 ths
#define SVM_SELECTOR_P_SHIFT 7
186 239fbd86 ths
#define SVM_SELECTOR_AVL_SHIFT 8
187 239fbd86 ths
#define SVM_SELECTOR_L_SHIFT 9
188 239fbd86 ths
#define SVM_SELECTOR_DB_SHIFT 10
189 239fbd86 ths
#define SVM_SELECTOR_G_SHIFT 11
190 239fbd86 ths
191 239fbd86 ths
#define SVM_SELECTOR_TYPE_MASK (0xf)
192 239fbd86 ths
#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
193 239fbd86 ths
#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
194 239fbd86 ths
#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
195 239fbd86 ths
#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
196 239fbd86 ths
#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
197 239fbd86 ths
#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
198 239fbd86 ths
#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
199 239fbd86 ths
200 239fbd86 ths
#define SVM_SELECTOR_WRITE_MASK (1 << 1)
201 239fbd86 ths
#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
202 239fbd86 ths
#define SVM_SELECTOR_CODE_MASK (1 << 3)
203 239fbd86 ths
204 239fbd86 ths
#define INTERCEPT_CR0_MASK 1
205 239fbd86 ths
#define INTERCEPT_CR3_MASK (1 << 3)
206 239fbd86 ths
#define INTERCEPT_CR4_MASK (1 << 4)
207 239fbd86 ths
208 239fbd86 ths
#define INTERCEPT_DR0_MASK 1
209 239fbd86 ths
#define INTERCEPT_DR1_MASK (1 << 1)
210 239fbd86 ths
#define INTERCEPT_DR2_MASK (1 << 2)
211 239fbd86 ths
#define INTERCEPT_DR3_MASK (1 << 3)
212 239fbd86 ths
#define INTERCEPT_DR4_MASK (1 << 4)
213 239fbd86 ths
#define INTERCEPT_DR5_MASK (1 << 5)
214 239fbd86 ths
#define INTERCEPT_DR6_MASK (1 << 6)
215 239fbd86 ths
#define INTERCEPT_DR7_MASK (1 << 7)
216 239fbd86 ths
217 239fbd86 ths
#define SVM_EVTINJ_VEC_MASK 0xff
218 239fbd86 ths
219 239fbd86 ths
#define SVM_EVTINJ_TYPE_SHIFT 8
220 239fbd86 ths
#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
221 239fbd86 ths
222 239fbd86 ths
#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
223 239fbd86 ths
#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
224 239fbd86 ths
#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
225 239fbd86 ths
#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
226 239fbd86 ths
227 239fbd86 ths
#define SVM_EVTINJ_VALID (1 << 31)
228 239fbd86 ths
#define SVM_EVTINJ_VALID_ERR (1 << 11)
229 239fbd86 ths
230 239fbd86 ths
#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
231 239fbd86 ths
232 239fbd86 ths
#define        SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
233 239fbd86 ths
#define        SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
234 239fbd86 ths
#define        SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
235 239fbd86 ths
#define        SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
236 239fbd86 ths
237 239fbd86 ths
#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
238 239fbd86 ths
#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
239 239fbd86 ths
240 239fbd86 ths
#define        SVM_EXIT_READ_CR0         0x000
241 239fbd86 ths
#define        SVM_EXIT_READ_CR3         0x003
242 239fbd86 ths
#define        SVM_EXIT_READ_CR4         0x004
243 239fbd86 ths
#define        SVM_EXIT_READ_CR8         0x008
244 239fbd86 ths
#define        SVM_EXIT_WRITE_CR0         0x010
245 239fbd86 ths
#define        SVM_EXIT_WRITE_CR3         0x013
246 239fbd86 ths
#define        SVM_EXIT_WRITE_CR4         0x014
247 239fbd86 ths
#define        SVM_EXIT_WRITE_CR8         0x018
248 239fbd86 ths
#define        SVM_EXIT_READ_DR0         0x020
249 239fbd86 ths
#define        SVM_EXIT_READ_DR1         0x021
250 239fbd86 ths
#define        SVM_EXIT_READ_DR2         0x022
251 239fbd86 ths
#define        SVM_EXIT_READ_DR3         0x023
252 239fbd86 ths
#define        SVM_EXIT_READ_DR4         0x024
253 239fbd86 ths
#define        SVM_EXIT_READ_DR5         0x025
254 239fbd86 ths
#define        SVM_EXIT_READ_DR6         0x026
255 239fbd86 ths
#define        SVM_EXIT_READ_DR7         0x027
256 239fbd86 ths
#define        SVM_EXIT_WRITE_DR0         0x030
257 239fbd86 ths
#define        SVM_EXIT_WRITE_DR1         0x031
258 239fbd86 ths
#define        SVM_EXIT_WRITE_DR2         0x032
259 239fbd86 ths
#define        SVM_EXIT_WRITE_DR3         0x033
260 239fbd86 ths
#define        SVM_EXIT_WRITE_DR4         0x034
261 239fbd86 ths
#define        SVM_EXIT_WRITE_DR5         0x035
262 239fbd86 ths
#define        SVM_EXIT_WRITE_DR6         0x036
263 239fbd86 ths
#define        SVM_EXIT_WRITE_DR7         0x037
264 239fbd86 ths
#define SVM_EXIT_EXCP_BASE      0x040
265 239fbd86 ths
#define SVM_EXIT_INTR                0x060
266 239fbd86 ths
#define SVM_EXIT_NMI                0x061
267 239fbd86 ths
#define SVM_EXIT_SMI                0x062
268 239fbd86 ths
#define SVM_EXIT_INIT                0x063
269 239fbd86 ths
#define SVM_EXIT_VINTR                0x064
270 239fbd86 ths
#define SVM_EXIT_CR0_SEL_WRITE        0x065
271 239fbd86 ths
#define SVM_EXIT_IDTR_READ        0x066
272 239fbd86 ths
#define SVM_EXIT_GDTR_READ        0x067
273 239fbd86 ths
#define SVM_EXIT_LDTR_READ        0x068
274 239fbd86 ths
#define SVM_EXIT_TR_READ        0x069
275 239fbd86 ths
#define SVM_EXIT_IDTR_WRITE        0x06a
276 239fbd86 ths
#define SVM_EXIT_GDTR_WRITE        0x06b
277 239fbd86 ths
#define SVM_EXIT_LDTR_WRITE        0x06c
278 239fbd86 ths
#define SVM_EXIT_TR_WRITE        0x06d
279 239fbd86 ths
#define SVM_EXIT_RDTSC                0x06e
280 239fbd86 ths
#define SVM_EXIT_RDPMC                0x06f
281 239fbd86 ths
#define SVM_EXIT_PUSHF                0x070
282 239fbd86 ths
#define SVM_EXIT_POPF                0x071
283 239fbd86 ths
#define SVM_EXIT_CPUID                0x072
284 239fbd86 ths
#define SVM_EXIT_RSM                0x073
285 239fbd86 ths
#define SVM_EXIT_IRET                0x074
286 239fbd86 ths
#define SVM_EXIT_SWINT                0x075
287 239fbd86 ths
#define SVM_EXIT_INVD                0x076
288 239fbd86 ths
#define SVM_EXIT_PAUSE                0x077
289 239fbd86 ths
#define SVM_EXIT_HLT                0x078
290 239fbd86 ths
#define SVM_EXIT_INVLPG                0x079
291 239fbd86 ths
#define SVM_EXIT_INVLPGA        0x07a
292 239fbd86 ths
#define SVM_EXIT_IOIO                0x07b
293 239fbd86 ths
#define SVM_EXIT_MSR                0x07c
294 239fbd86 ths
#define SVM_EXIT_TASK_SWITCH        0x07d
295 239fbd86 ths
#define SVM_EXIT_FERR_FREEZE        0x07e
296 239fbd86 ths
#define SVM_EXIT_SHUTDOWN        0x07f
297 239fbd86 ths
#define SVM_EXIT_VMRUN                0x080
298 239fbd86 ths
#define SVM_EXIT_VMMCALL        0x081
299 239fbd86 ths
#define SVM_EXIT_VMLOAD                0x082
300 239fbd86 ths
#define SVM_EXIT_VMSAVE                0x083
301 239fbd86 ths
#define SVM_EXIT_STGI                0x084
302 239fbd86 ths
#define SVM_EXIT_CLGI                0x085
303 239fbd86 ths
#define SVM_EXIT_SKINIT                0x086
304 239fbd86 ths
#define SVM_EXIT_RDTSCP                0x087
305 239fbd86 ths
#define SVM_EXIT_ICEBP                0x088
306 239fbd86 ths
#define SVM_EXIT_WBINVD                0x089
307 239fbd86 ths
/* only included in documentation, maybe wrong */
308 239fbd86 ths
#define SVM_EXIT_MONITOR        0x08a
309 239fbd86 ths
#define SVM_EXIT_MWAIT                0x08b
310 239fbd86 ths
#define SVM_EXIT_NPF                  0x400
311 239fbd86 ths
312 239fbd86 ths
#define SVM_EXIT_ERR                -1
313 239fbd86 ths
314 239fbd86 ths
#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
315 239fbd86 ths
316 239fbd86 ths
#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
317 239fbd86 ths
#define SVM_VMRUN  ".byte 0x0f, 0x01, 0xd8"
318 239fbd86 ths
#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
319 239fbd86 ths
#define SVM_CLGI   ".byte 0x0f, 0x01, 0xdd"
320 239fbd86 ths
#define SVM_STGI   ".byte 0x0f, 0x01, 0xdc"
321 239fbd86 ths
#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
322 239fbd86 ths
323 239fbd86 ths
/* function references */
324 239fbd86 ths
325 239fbd86 ths
#define INTERCEPTED(mask) (env->intercept & mask)
326 239fbd86 ths
#define INTERCEPTEDw(var, mask) (env->intercept ## var & mask)
327 239fbd86 ths
#define INTERCEPTEDl(var, mask) (env->intercept ## var & mask)
328 239fbd86 ths
329 239fbd86 ths
#define SVM_LOAD_SEG(addr, seg_index, seg) \
330 239fbd86 ths
    cpu_x86_load_seg_cache(env, \
331 239fbd86 ths
                    R_##seg_index, \
332 239fbd86 ths
                    lduw_phys(addr + offsetof(struct vmcb, save.seg.selector)),\
333 239fbd86 ths
                    ldq_phys(addr + offsetof(struct vmcb, save.seg.base)),\
334 239fbd86 ths
                    ldl_phys(addr + offsetof(struct vmcb, save.seg.limit)),\
335 239fbd86 ths
                    vmcb2cpu_attrib(lduw_phys(addr + offsetof(struct vmcb, save.seg.attrib)), ldq_phys(addr + offsetof(struct vmcb, save.seg.base)), ldl_phys(addr + offsetof(struct vmcb, save.seg.limit))))
336 239fbd86 ths
337 239fbd86 ths
#define SVM_LOAD_SEG2(addr, seg_qemu, seg_vmcb) \
338 239fbd86 ths
    env->seg_qemu.selector  = lduw_phys(addr + offsetof(struct vmcb, save.seg_vmcb.selector)); \
339 239fbd86 ths
    env->seg_qemu.base      = ldq_phys(addr + offsetof(struct vmcb, save.seg_vmcb.base)); \
340 239fbd86 ths
    env->seg_qemu.limit     = ldl_phys(addr + offsetof(struct vmcb, save.seg_vmcb.limit)); \
341 239fbd86 ths
    env->seg_qemu.flags     = vmcb2cpu_attrib(lduw_phys(addr + offsetof(struct vmcb, save.seg_vmcb.attrib)), env->seg_qemu.base, env->seg_qemu.limit)
342 239fbd86 ths
343 239fbd86 ths
#define SVM_SAVE_SEG(addr, seg_qemu, seg_vmcb) \
344 239fbd86 ths
    stw_phys(addr + offsetof(struct vmcb, save.seg_vmcb.selector), env->seg_qemu.selector); \
345 239fbd86 ths
    stq_phys(addr + offsetof(struct vmcb, save.seg_vmcb.base), env->seg_qemu.base); \
346 239fbd86 ths
    stl_phys(addr + offsetof(struct vmcb, save.seg_vmcb.limit), env->seg_qemu.limit); \
347 239fbd86 ths
    stw_phys(addr + offsetof(struct vmcb, save.seg_vmcb.attrib), cpu2vmcb_attrib(env->seg_qemu.flags))
348 239fbd86 ths
349 239fbd86 ths
#endif