Revision b6abf97d target-i386/translate.c
| b/target-i386/translate.c | ||
|---|---|---|
| 58 | 58 |
//#define MACRO_TEST 1 |
| 59 | 59 |
|
| 60 | 60 |
/* global register indexes */ |
| 61 |
static TCGv cpu_env, cpu_T[2], cpu_A0; |
|
| 61 |
static TCGv cpu_env, cpu_T[2], cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst; |
|
| 62 |
static TCGv cpu_T3; |
|
| 62 | 63 |
/* local register indexes (only used inside old micro ops) */ |
| 63 |
static TCGv cpu_tmp0, cpu_tmp1, cpu_tmp2, cpu_tmp3, cpu_ptr0, cpu_ptr1; |
|
| 64 |
static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1; |
|
| 65 |
static TCGv cpu_tmp5, cpu_tmp6; |
|
| 64 | 66 |
|
| 65 | 67 |
#ifdef TARGET_X86_64 |
| 66 | 68 |
static int x86_64_hregs; |
| ... | ... | |
| 428 | 430 |
|
| 429 | 431 |
static inline void gen_op_set_cc_op(int32_t val) |
| 430 | 432 |
{
|
| 431 |
tcg_gen_movi_tl(cpu_tmp0, val); |
|
| 432 |
tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, cc_op)); |
|
| 433 |
tcg_gen_movi_i32(cpu_cc_op, val); |
|
| 433 | 434 |
} |
| 434 | 435 |
|
| 435 | 436 |
static inline void gen_op_addl_A0_reg_sN(int shift, int reg) |
| ... | ... | |
| 556 | 557 |
#endif |
| 557 | 558 |
}; |
| 558 | 559 |
|
| 559 |
#define DEF_SHIFT(SUFFIX)\ |
|
| 560 |
{\
|
|
| 561 |
gen_op_rolb ## SUFFIX ## _T0_T1_cc,\ |
|
| 562 |
gen_op_rorb ## SUFFIX ## _T0_T1_cc,\ |
|
| 563 |
gen_op_rclb ## SUFFIX ## _T0_T1_cc,\ |
|
| 564 |
gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\ |
|
| 565 |
gen_op_shlb ## SUFFIX ## _T0_T1_cc,\ |
|
| 566 |
gen_op_shrb ## SUFFIX ## _T0_T1_cc,\ |
|
| 567 |
gen_op_shlb ## SUFFIX ## _T0_T1_cc,\ |
|
| 568 |
gen_op_sarb ## SUFFIX ## _T0_T1_cc,\ |
|
| 569 |
},\ |
|
| 570 |
{\
|
|
| 571 |
gen_op_rolw ## SUFFIX ## _T0_T1_cc,\ |
|
| 572 |
gen_op_rorw ## SUFFIX ## _T0_T1_cc,\ |
|
| 573 |
gen_op_rclw ## SUFFIX ## _T0_T1_cc,\ |
|
| 574 |
gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\ |
|
| 575 |
gen_op_shlw ## SUFFIX ## _T0_T1_cc,\ |
|
| 576 |
gen_op_shrw ## SUFFIX ## _T0_T1_cc,\ |
|
| 577 |
gen_op_shlw ## SUFFIX ## _T0_T1_cc,\ |
|
| 578 |
gen_op_sarw ## SUFFIX ## _T0_T1_cc,\ |
|
| 579 |
},\ |
|
| 580 |
{\
|
|
| 581 |
gen_op_roll ## SUFFIX ## _T0_T1_cc,\ |
|
| 582 |
gen_op_rorl ## SUFFIX ## _T0_T1_cc,\ |
|
| 583 |
gen_op_rcll ## SUFFIX ## _T0_T1_cc,\ |
|
| 584 |
gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\ |
|
| 585 |
gen_op_shll ## SUFFIX ## _T0_T1_cc,\ |
|
| 586 |
gen_op_shrl ## SUFFIX ## _T0_T1_cc,\ |
|
| 587 |
gen_op_shll ## SUFFIX ## _T0_T1_cc,\ |
|
| 588 |
gen_op_sarl ## SUFFIX ## _T0_T1_cc,\ |
|
| 589 |
},\ |
|
| 590 |
{\
|
|
| 591 |
X86_64_ONLY(gen_op_rolq ## SUFFIX ## _T0_T1_cc),\ |
|
| 592 |
X86_64_ONLY(gen_op_rorq ## SUFFIX ## _T0_T1_cc),\ |
|
| 593 |
X86_64_ONLY(gen_op_rclq ## SUFFIX ## _T0_T1_cc),\ |
|
| 594 |
X86_64_ONLY(gen_op_rcrq ## SUFFIX ## _T0_T1_cc),\ |
|
| 595 |
X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\ |
|
| 596 |
X86_64_ONLY(gen_op_shrq ## SUFFIX ## _T0_T1_cc),\ |
|
| 597 |
X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\ |
|
| 598 |
X86_64_ONLY(gen_op_sarq ## SUFFIX ## _T0_T1_cc),\ |
|
| 599 |
}, |
|
| 600 |
|
|
| 601 |
static GenOpFunc *gen_op_shift_T0_T1_cc[4][8] = {
|
|
| 602 |
DEF_SHIFT( ) |
|
| 603 |
}; |
|
| 604 |
|
|
| 605 |
static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3 * 4][8] = {
|
|
| 606 |
DEF_SHIFT(_raw) |
|
| 607 |
#ifndef CONFIG_USER_ONLY |
|
| 608 |
DEF_SHIFT(_kernel) |
|
| 609 |
DEF_SHIFT(_user) |
|
| 610 |
#endif |
|
| 611 |
}; |
|
| 612 |
|
|
| 613 |
#define DEF_SHIFTD(SUFFIX, op)\ |
|
| 614 |
{\
|
|
| 615 |
NULL,\ |
|
| 616 |
NULL,\ |
|
| 617 |
},\ |
|
| 618 |
{\
|
|
| 619 |
gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\ |
|
| 620 |
gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\ |
|
| 621 |
},\ |
|
| 622 |
{\
|
|
| 623 |
gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\ |
|
| 624 |
gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\ |
|
| 625 |
},\ |
|
| 626 |
{\
|
|
| 627 |
X86_64_DEF(gen_op_shldq ## SUFFIX ## _T0_T1_ ## op ## _cc,\ |
|
| 628 |
gen_op_shrdq ## SUFFIX ## _T0_T1_ ## op ## _cc,)\ |
|
| 629 |
}, |
|
| 630 |
|
|
| 631 |
static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[4][2] = {
|
|
| 632 |
DEF_SHIFTD(, im) |
|
| 633 |
}; |
|
| 634 |
|
|
| 635 |
static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[4][2] = {
|
|
| 636 |
DEF_SHIFTD(, ECX) |
|
| 637 |
}; |
|
| 638 |
|
|
| 639 |
static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[3 * 4][2] = {
|
|
| 640 |
DEF_SHIFTD(_raw, im) |
|
| 641 |
#ifndef CONFIG_USER_ONLY |
|
| 642 |
DEF_SHIFTD(_kernel, im) |
|
| 643 |
DEF_SHIFTD(_user, im) |
|
| 644 |
#endif |
|
| 645 |
}; |
|
| 646 |
|
|
| 647 |
static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[3 * 4][2] = {
|
|
| 648 |
DEF_SHIFTD(_raw, ECX) |
|
| 649 |
#ifndef CONFIG_USER_ONLY |
|
| 650 |
DEF_SHIFTD(_kernel, ECX) |
|
| 651 |
DEF_SHIFTD(_user, ECX) |
|
| 652 |
#endif |
|
| 653 |
}; |
|
| 654 |
|
|
| 655 | 560 |
static GenOpFunc *gen_op_btx_T0_T1_cc[3][4] = {
|
| 656 | 561 |
[0] = {
|
| 657 | 562 |
gen_op_btw_T0_T1_cc, |
| ... | ... | |
| 933 | 838 |
gen_op_set_cc_op(s->cc_op); |
| 934 | 839 |
gen_jmp_im(cur_eip); |
| 935 | 840 |
state_saved = 1; |
| 936 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 841 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 937 | 842 |
tcg_gen_helper_0_1(gen_check_io_func[ot], |
| 938 |
cpu_tmp2); |
|
| 843 |
cpu_tmp2_i32);
|
|
| 939 | 844 |
} |
| 940 | 845 |
if(s->flags & (1ULL << INTERCEPT_IOIO_PROT)) {
|
| 941 | 846 |
if (!state_saved) {
|
| ... | ... | |
| 946 | 851 |
} |
| 947 | 852 |
svm_flags |= (1 << (4 + ot)); |
| 948 | 853 |
next_eip = s->pc - s->cs_base; |
| 949 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 854 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 950 | 855 |
tcg_gen_helper_0_3(helper_svm_check_io, |
| 951 |
cpu_tmp2, |
|
| 856 |
cpu_tmp2_i32,
|
|
| 952 | 857 |
tcg_const_i32(svm_flags), |
| 953 | 858 |
tcg_const_i32(next_eip - cur_eip)); |
| 954 | 859 |
} |
| ... | ... | |
| 984 | 889 |
} |
| 985 | 890 |
} |
| 986 | 891 |
|
| 892 |
static void gen_op_update1_cc(void) |
|
| 893 |
{
|
|
| 894 |
tcg_gen_discard_tl(cpu_cc_src); |
|
| 895 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
|
| 896 |
} |
|
| 897 |
|
|
| 898 |
static void gen_op_update2_cc(void) |
|
| 899 |
{
|
|
| 900 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); |
|
| 901 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
|
| 902 |
} |
|
| 903 |
|
|
| 904 |
static inline void gen_op_cmpl_T0_T1_cc(void) |
|
| 905 |
{
|
|
| 906 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); |
|
| 907 |
tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
|
| 908 |
} |
|
| 909 |
|
|
| 910 |
static inline void gen_op_testl_T0_T1_cc(void) |
|
| 911 |
{
|
|
| 912 |
tcg_gen_discard_tl(cpu_cc_src); |
|
| 913 |
tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]); |
|
| 914 |
} |
|
| 915 |
|
|
| 916 |
static void gen_op_update_neg_cc(void) |
|
| 917 |
{
|
|
| 918 |
tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]); |
|
| 919 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
|
| 920 |
} |
|
| 921 |
|
|
| 987 | 922 |
/* XXX: does not work with gdbstub "ice" single step - not a |
| 988 | 923 |
serious problem */ |
| 989 | 924 |
static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) |
| ... | ... | |
| 1083 | 1018 |
gen_op_movl_T0_0(); |
| 1084 | 1019 |
gen_op_st_T0_A0(ot + s->mem_index); |
| 1085 | 1020 |
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
| 1086 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[1]); |
|
| 1087 |
tcg_gen_andi_i32(cpu_tmp2, cpu_tmp2, 0xffff);
|
|
| 1088 |
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2); |
|
| 1021 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
|
|
| 1022 |
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
|
| 1023 |
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
|
|
| 1089 | 1024 |
gen_op_st_T0_A0(ot + s->mem_index); |
| 1090 | 1025 |
gen_op_movl_T0_Dshift[ot](); |
| 1091 | 1026 |
#ifdef TARGET_X86_64 |
| ... | ... | |
| 1106 | 1041 |
gen_op_ld_T0_A0(ot + s->mem_index); |
| 1107 | 1042 |
|
| 1108 | 1043 |
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); |
| 1109 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[1]); |
|
| 1110 |
tcg_gen_andi_i32(cpu_tmp2, cpu_tmp2, 0xffff);
|
|
| 1111 |
tcg_gen_trunc_tl_i32(cpu_tmp3, cpu_T[0]); |
|
| 1112 |
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2, cpu_tmp3);
|
|
| 1044 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
|
|
| 1045 |
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
|
| 1046 |
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
|
|
| 1047 |
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
|
|
| 1113 | 1048 |
|
| 1114 | 1049 |
gen_op_movl_T0_Dshift[ot](); |
| 1115 | 1050 |
#ifdef TARGET_X86_64 |
| ... | ... | |
| 1390 | 1325 |
the_end: ; |
| 1391 | 1326 |
} |
| 1392 | 1327 |
|
| 1328 |
/* compute eflags.C to reg */ |
|
| 1329 |
static void gen_compute_eflags_c(TCGv reg) |
|
| 1330 |
{
|
|
| 1331 |
#if TCG_TARGET_REG_BITS == 32 |
|
| 1332 |
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); |
|
| 1333 |
tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, |
|
| 1334 |
(long)cc_table + offsetof(CCTable, compute_c)); |
|
| 1335 |
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); |
|
| 1336 |
tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, |
|
| 1337 |
1, ®, 0, NULL); |
|
| 1338 |
#else |
|
| 1339 |
tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); |
|
| 1340 |
tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); |
|
| 1341 |
tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, |
|
| 1342 |
(long)cc_table + offsetof(CCTable, compute_c)); |
|
| 1343 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); |
|
| 1344 |
tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, |
|
| 1345 |
1, &cpu_tmp2_i32, 0, NULL); |
|
| 1346 |
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
|
| 1347 |
#endif |
|
| 1348 |
} |
|
| 1349 |
|
|
| 1350 |
/* compute all eflags to cc_src */ |
|
| 1351 |
static void gen_compute_eflags(TCGv reg) |
|
| 1352 |
{
|
|
| 1353 |
#if TCG_TARGET_REG_BITS == 32 |
|
| 1354 |
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); |
|
| 1355 |
tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, |
|
| 1356 |
(long)cc_table + offsetof(CCTable, compute_all)); |
|
| 1357 |
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); |
|
| 1358 |
tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, |
|
| 1359 |
1, ®, 0, NULL); |
|
| 1360 |
#else |
|
| 1361 |
tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); |
|
| 1362 |
tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); |
|
| 1363 |
tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, |
|
| 1364 |
(long)cc_table + offsetof(CCTable, compute_all)); |
|
| 1365 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); |
|
| 1366 |
tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, |
|
| 1367 |
1, &cpu_tmp2_i32, 0, NULL); |
|
| 1368 |
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); |
|
| 1369 |
#endif |
|
| 1370 |
} |
|
| 1371 |
|
|
| 1393 | 1372 |
/* if d == OR_TMP0, it means memory operand (address in A0) */ |
| 1394 | 1373 |
static void gen_inc(DisasContext *s1, int ot, int d, int c) |
| 1395 | 1374 |
{
|
| ... | ... | |
| 1400 | 1379 |
if (s1->cc_op != CC_OP_DYNAMIC) |
| 1401 | 1380 |
gen_op_set_cc_op(s1->cc_op); |
| 1402 | 1381 |
if (c > 0) {
|
| 1403 |
gen_op_incl_T0();
|
|
| 1382 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
|
|
| 1404 | 1383 |
s1->cc_op = CC_OP_INCB + ot; |
| 1405 | 1384 |
} else {
|
| 1406 |
gen_op_decl_T0();
|
|
| 1385 |
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
|
|
| 1407 | 1386 |
s1->cc_op = CC_OP_DECB + ot; |
| 1408 | 1387 |
} |
| 1409 | 1388 |
if (d != OR_TMP0) |
| 1410 | 1389 |
gen_op_mov_reg_T0(ot, d); |
| 1411 | 1390 |
else |
| 1412 | 1391 |
gen_op_st_T0_A0(ot + s1->mem_index); |
| 1413 |
gen_op_update_inc_cc(); |
|
| 1392 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
|
| 1393 |
gen_compute_eflags_c(cpu_cc_src); |
|
| 1414 | 1394 |
} |
| 1415 | 1395 |
|
| 1416 |
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) |
|
| 1396 |
/* XXX: add faster immediate case */ |
|
| 1397 |
static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, |
|
| 1398 |
int is_right, int is_arith) |
|
| 1417 | 1399 |
{
|
| 1418 |
if (d != OR_TMP0) |
|
| 1419 |
gen_op_mov_TN_reg(ot, 0, d); |
|
| 1400 |
target_ulong mask; |
|
| 1401 |
int shift_label; |
|
| 1402 |
|
|
| 1403 |
if (ot == OT_QUAD) |
|
| 1404 |
mask = 0x3f; |
|
| 1420 | 1405 |
else |
| 1421 |
gen_op_ld_T0_A0(ot + s1->mem_index); |
|
| 1422 |
if (s != OR_TMP1) |
|
| 1423 |
gen_op_mov_TN_reg(ot, 1, s); |
|
| 1424 |
/* for zero counts, flags are not updated, so must do it dynamically */ |
|
| 1425 |
if (s1->cc_op != CC_OP_DYNAMIC) |
|
| 1426 |
gen_op_set_cc_op(s1->cc_op); |
|
| 1406 |
mask = 0x1f; |
|
| 1427 | 1407 |
|
| 1428 |
if (d != OR_TMP0) |
|
| 1429 |
gen_op_shift_T0_T1_cc[ot][op](); |
|
| 1408 |
/* load */ |
|
| 1409 |
if (op1 == OR_TMP0) |
|
| 1410 |
gen_op_ld_T0_A0(ot + s->mem_index); |
|
| 1430 | 1411 |
else |
| 1431 |
gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op](); |
|
| 1432 |
if (d != OR_TMP0) |
|
| 1433 |
gen_op_mov_reg_T0(ot, d); |
|
| 1434 |
s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
|
| 1412 |
gen_op_mov_TN_reg(ot, 0, op1); |
|
| 1413 |
|
|
| 1414 |
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
|
| 1415 |
|
|
| 1416 |
tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1); |
|
| 1417 |
|
|
| 1418 |
if (is_right) {
|
|
| 1419 |
if (is_arith) {
|
|
| 1420 |
switch(ot) {
|
|
| 1421 |
case OT_BYTE: |
|
| 1422 |
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); |
|
| 1423 |
break; |
|
| 1424 |
case OT_WORD: |
|
| 1425 |
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); |
|
| 1426 |
break; |
|
| 1427 |
case OT_LONG: |
|
| 1428 |
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); |
|
| 1429 |
break; |
|
| 1430 |
default: |
|
| 1431 |
break; |
|
| 1432 |
} |
|
| 1433 |
tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5); |
|
| 1434 |
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1435 |
} else {
|
|
| 1436 |
switch(ot) {
|
|
| 1437 |
case OT_BYTE: |
|
| 1438 |
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
|
| 1439 |
break; |
|
| 1440 |
case OT_WORD: |
|
| 1441 |
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
|
| 1442 |
break; |
|
| 1443 |
case OT_LONG: |
|
| 1444 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
|
| 1445 |
break; |
|
| 1446 |
default: |
|
| 1447 |
break; |
|
| 1448 |
} |
|
| 1449 |
tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5); |
|
| 1450 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1451 |
} |
|
| 1452 |
} else {
|
|
| 1453 |
tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5); |
|
| 1454 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1455 |
} |
|
| 1456 |
|
|
| 1457 |
/* store */ |
|
| 1458 |
if (op1 == OR_TMP0) |
|
| 1459 |
gen_op_st_T0_A0(ot + s->mem_index); |
|
| 1460 |
else |
|
| 1461 |
gen_op_mov_reg_T0(ot, op1); |
|
| 1462 |
|
|
| 1463 |
/* update eflags if non zero shift */ |
|
| 1464 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 1465 |
gen_op_set_cc_op(s->cc_op); |
|
| 1466 |
|
|
| 1467 |
shift_label = gen_new_label(); |
|
| 1468 |
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), shift_label); |
|
| 1469 |
|
|
| 1470 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T3); |
|
| 1471 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
|
| 1472 |
if (is_right) |
|
| 1473 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
|
| 1474 |
else |
|
| 1475 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
|
| 1476 |
|
|
| 1477 |
gen_set_label(shift_label); |
|
| 1478 |
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
|
| 1479 |
} |
|
| 1480 |
|
|
| 1481 |
static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) |
|
| 1482 |
{
|
|
| 1483 |
if (arg2 >= 0) |
|
| 1484 |
tcg_gen_shli_tl(ret, arg1, arg2); |
|
| 1485 |
else |
|
| 1486 |
tcg_gen_shri_tl(ret, arg1, -arg2); |
|
| 1487 |
} |
|
| 1488 |
|
|
| 1489 |
/* XXX: add faster immediate case */ |
|
| 1490 |
static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, |
|
| 1491 |
int is_right) |
|
| 1492 |
{
|
|
| 1493 |
target_ulong mask; |
|
| 1494 |
int label1, label2, data_bits; |
|
| 1495 |
|
|
| 1496 |
if (ot == OT_QUAD) |
|
| 1497 |
mask = 0x3f; |
|
| 1498 |
else |
|
| 1499 |
mask = 0x1f; |
|
| 1500 |
|
|
| 1501 |
/* load */ |
|
| 1502 |
if (op1 == OR_TMP0) |
|
| 1503 |
gen_op_ld_T0_A0(ot + s->mem_index); |
|
| 1504 |
else |
|
| 1505 |
gen_op_mov_TN_reg(ot, 0, op1); |
|
| 1506 |
|
|
| 1507 |
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); |
|
| 1508 |
|
|
| 1509 |
/* Must test zero case to avoid using undefined behaviour in TCG |
|
| 1510 |
shifts. */ |
|
| 1511 |
label1 = gen_new_label(); |
|
| 1512 |
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label1); |
|
| 1513 |
|
|
| 1514 |
if (ot <= OT_WORD) |
|
| 1515 |
tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], (1 << (3 + ot)) - 1); |
|
| 1516 |
else |
|
| 1517 |
tcg_gen_mov_tl(cpu_tmp0, cpu_T[1]); |
|
| 1518 |
|
|
| 1519 |
switch(ot) {
|
|
| 1520 |
case OT_BYTE: |
|
| 1521 |
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); |
|
| 1522 |
break; |
|
| 1523 |
case OT_WORD: |
|
| 1524 |
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); |
|
| 1525 |
break; |
|
| 1526 |
case OT_LONG: |
|
| 1527 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
|
| 1528 |
break; |
|
| 1529 |
default: |
|
| 1530 |
break; |
|
| 1531 |
} |
|
| 1532 |
tcg_gen_mov_tl(cpu_T3, cpu_T[0]); |
|
| 1533 |
|
|
| 1534 |
data_bits = 8 << ot; |
|
| 1535 |
/* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: |
|
| 1536 |
fix TCG definition) */ |
|
| 1537 |
if (is_right) {
|
|
| 1538 |
tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp0); |
|
| 1539 |
tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); |
|
| 1540 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
|
| 1541 |
} else {
|
|
| 1542 |
tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp0); |
|
| 1543 |
tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); |
|
| 1544 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
|
| 1545 |
} |
|
| 1546 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp4); |
|
| 1547 |
|
|
| 1548 |
gen_set_label(label1); |
|
| 1549 |
/* store */ |
|
| 1550 |
if (op1 == OR_TMP0) |
|
| 1551 |
gen_op_st_T0_A0(ot + s->mem_index); |
|
| 1552 |
else |
|
| 1553 |
gen_op_mov_reg_T0(ot, op1); |
|
| 1554 |
|
|
| 1555 |
/* update eflags */ |
|
| 1556 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 1557 |
gen_op_set_cc_op(s->cc_op); |
|
| 1558 |
|
|
| 1559 |
label2 = gen_new_label(); |
|
| 1560 |
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label2); |
|
| 1561 |
|
|
| 1562 |
gen_compute_eflags(cpu_cc_src); |
|
| 1563 |
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); |
|
| 1564 |
tcg_gen_xor_tl(cpu_tmp0, cpu_T3, cpu_T[0]); |
|
| 1565 |
tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); |
|
| 1566 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); |
|
| 1567 |
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
|
| 1568 |
if (is_right) {
|
|
| 1569 |
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], data_bits - 1); |
|
| 1570 |
} |
|
| 1571 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_C); |
|
| 1572 |
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); |
|
| 1573 |
|
|
| 1574 |
tcg_gen_discard_tl(cpu_cc_dst); |
|
| 1575 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); |
|
| 1576 |
|
|
| 1577 |
gen_set_label(label2); |
|
| 1578 |
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
|
| 1579 |
} |
|
| 1580 |
|
|
| 1581 |
static void *helper_rotc[8] = {
|
|
| 1582 |
helper_rclb, |
|
| 1583 |
helper_rclw, |
|
| 1584 |
helper_rcll, |
|
| 1585 |
X86_64_ONLY(helper_rclq), |
|
| 1586 |
helper_rcrb, |
|
| 1587 |
helper_rcrw, |
|
| 1588 |
helper_rcrl, |
|
| 1589 |
X86_64_ONLY(helper_rcrq), |
|
| 1590 |
}; |
|
| 1591 |
|
|
| 1592 |
/* XXX: add faster immediate = 1 case */ |
|
| 1593 |
static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, |
|
| 1594 |
int is_right) |
|
| 1595 |
{
|
|
| 1596 |
int label1; |
|
| 1597 |
|
|
| 1598 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 1599 |
gen_op_set_cc_op(s->cc_op); |
|
| 1600 |
|
|
| 1601 |
/* load */ |
|
| 1602 |
if (op1 == OR_TMP0) |
|
| 1603 |
gen_op_ld_T0_A0(ot + s->mem_index); |
|
| 1604 |
else |
|
| 1605 |
gen_op_mov_TN_reg(ot, 0, op1); |
|
| 1606 |
|
|
| 1607 |
tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)], |
|
| 1608 |
cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1609 |
/* store */ |
|
| 1610 |
if (op1 == OR_TMP0) |
|
| 1611 |
gen_op_st_T0_A0(ot + s->mem_index); |
|
| 1612 |
else |
|
| 1613 |
gen_op_mov_reg_T0(ot, op1); |
|
| 1614 |
|
|
| 1615 |
/* update eflags */ |
|
| 1616 |
label1 = gen_new_label(); |
|
| 1617 |
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(-1), label1); |
|
| 1618 |
|
|
| 1619 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T3); |
|
| 1620 |
tcg_gen_discard_tl(cpu_cc_dst); |
|
| 1621 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); |
|
| 1622 |
|
|
| 1623 |
gen_set_label(label1); |
|
| 1624 |
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
|
| 1625 |
} |
|
| 1626 |
|
|
| 1627 |
/* XXX: add faster immediate case */ |
|
| 1628 |
static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, |
|
| 1629 |
int is_right) |
|
| 1630 |
{
|
|
| 1631 |
int label1, label2, data_bits; |
|
| 1632 |
target_ulong mask; |
|
| 1633 |
|
|
| 1634 |
if (ot == OT_QUAD) |
|
| 1635 |
mask = 0x3f; |
|
| 1636 |
else |
|
| 1637 |
mask = 0x1f; |
|
| 1638 |
|
|
| 1639 |
/* load */ |
|
| 1640 |
if (op1 == OR_TMP0) |
|
| 1641 |
gen_op_ld_T0_A0(ot + s->mem_index); |
|
| 1642 |
else |
|
| 1643 |
gen_op_mov_TN_reg(ot, 0, op1); |
|
| 1644 |
|
|
| 1645 |
tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); |
|
| 1646 |
/* Must test zero case to avoid using undefined behaviour in TCG |
|
| 1647 |
shifts. */ |
|
| 1648 |
label1 = gen_new_label(); |
|
| 1649 |
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1); |
|
| 1650 |
|
|
| 1651 |
tcg_gen_addi_tl(cpu_tmp5, cpu_T3, -1); |
|
| 1652 |
if (ot == OT_WORD) {
|
|
| 1653 |
/* Note: we implement the Intel behaviour for shift count > 16 */ |
|
| 1654 |
if (is_right) {
|
|
| 1655 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
|
| 1656 |
tcg_gen_shli_tl(cpu_tmp0, cpu_T[1], 16); |
|
| 1657 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
|
| 1658 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
|
| 1659 |
|
|
| 1660 |
tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); |
|
| 1661 |
|
|
| 1662 |
/* only needed if count > 16, but a test would complicate */ |
|
| 1663 |
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3); |
|
| 1664 |
tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp5); |
|
| 1665 |
|
|
| 1666 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3); |
|
| 1667 |
|
|
| 1668 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
|
| 1669 |
} else {
|
|
| 1670 |
/* XXX: not optimal */ |
|
| 1671 |
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); |
|
| 1672 |
tcg_gen_shli_tl(cpu_T[1], cpu_T[1], 16); |
|
| 1673 |
tcg_gen_or_tl(cpu_T[1], cpu_T[1], cpu_T[0]); |
|
| 1674 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); |
|
| 1675 |
|
|
| 1676 |
tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); |
|
| 1677 |
tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5); |
|
| 1678 |
tcg_gen_shr_tl(cpu_tmp6, cpu_T[1], cpu_tmp0); |
|
| 1679 |
tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6); |
|
| 1680 |
|
|
| 1681 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3); |
|
| 1682 |
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3); |
|
| 1683 |
tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5); |
|
| 1684 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1685 |
} |
|
| 1686 |
} else {
|
|
| 1687 |
data_bits = 8 << ot; |
|
| 1688 |
if (is_right) {
|
|
| 1689 |
if (ot == OT_LONG) |
|
| 1690 |
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); |
|
| 1691 |
|
|
| 1692 |
tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); |
|
| 1693 |
|
|
| 1694 |
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3); |
|
| 1695 |
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3); |
|
| 1696 |
tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp5); |
|
| 1697 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1698 |
|
|
| 1699 |
} else {
|
|
| 1700 |
if (ot == OT_LONG) |
|
| 1701 |
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); |
|
| 1702 |
|
|
| 1703 |
tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); |
|
| 1704 |
|
|
| 1705 |
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3); |
|
| 1706 |
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3); |
|
| 1707 |
tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5); |
|
| 1708 |
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 1709 |
} |
|
| 1710 |
} |
|
| 1711 |
tcg_gen_mov_tl(cpu_T[1], cpu_tmp4); |
|
| 1712 |
|
|
| 1713 |
gen_set_label(label1); |
|
| 1714 |
/* store */ |
|
| 1715 |
if (op1 == OR_TMP0) |
|
| 1716 |
gen_op_st_T0_A0(ot + s->mem_index); |
|
| 1717 |
else |
|
| 1718 |
gen_op_mov_reg_T0(ot, op1); |
|
| 1719 |
|
|
| 1720 |
/* update eflags */ |
|
| 1721 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 1722 |
gen_op_set_cc_op(s->cc_op); |
|
| 1723 |
|
|
| 1724 |
label2 = gen_new_label(); |
|
| 1725 |
tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label2); |
|
| 1726 |
|
|
| 1727 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); |
|
| 1728 |
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); |
|
| 1729 |
if (is_right) {
|
|
| 1730 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); |
|
| 1731 |
} else {
|
|
| 1732 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); |
|
| 1733 |
} |
|
| 1734 |
gen_set_label(label2); |
|
| 1735 |
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
|
| 1736 |
} |
|
| 1737 |
|
|
| 1738 |
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) |
|
| 1739 |
{
|
|
| 1740 |
if (s != OR_TMP1) |
|
| 1741 |
gen_op_mov_TN_reg(ot, 1, s); |
|
| 1742 |
switch(op) {
|
|
| 1743 |
case OP_ROL: |
|
| 1744 |
gen_rot_rm_T1(s1, ot, d, 0); |
|
| 1745 |
break; |
|
| 1746 |
case OP_ROR: |
|
| 1747 |
gen_rot_rm_T1(s1, ot, d, 1); |
|
| 1748 |
break; |
|
| 1749 |
case OP_SHL: |
|
| 1750 |
case OP_SHL1: |
|
| 1751 |
gen_shift_rm_T1(s1, ot, d, 0, 0); |
|
| 1752 |
break; |
|
| 1753 |
case OP_SHR: |
|
| 1754 |
gen_shift_rm_T1(s1, ot, d, 1, 0); |
|
| 1755 |
break; |
|
| 1756 |
case OP_SAR: |
|
| 1757 |
gen_shift_rm_T1(s1, ot, d, 1, 1); |
|
| 1758 |
break; |
|
| 1759 |
case OP_RCL: |
|
| 1760 |
gen_rotc_rm_T1(s1, ot, d, 0); |
|
| 1761 |
break; |
|
| 1762 |
case OP_RCR: |
|
| 1763 |
gen_rotc_rm_T1(s1, ot, d, 1); |
|
| 1764 |
break; |
|
| 1765 |
} |
|
| 1435 | 1766 |
} |
| 1436 | 1767 |
|
| 1437 | 1768 |
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) |
| ... | ... | |
| 1987 | 2318 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 1988 | 2319 |
gen_op_set_cc_op(s->cc_op); |
| 1989 | 2320 |
gen_jmp_im(cur_eip); |
| 1990 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 1991 |
tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2); |
|
| 2321 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 2322 |
tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32);
|
|
| 1992 | 2323 |
/* abort translation because the addseg value may change or |
| 1993 | 2324 |
because ss32 may change. For R_SS, translation must always |
| 1994 | 2325 |
stop as a special handling must be done to disable hardware |
| ... | ... | |
| 2373 | 2704 |
static inline void gen_ldq_env_A0(int idx, int offset) |
| 2374 | 2705 |
{
|
| 2375 | 2706 |
int mem_index = (idx >> 2) - 1; |
| 2376 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, mem_index); |
|
| 2377 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, offset); |
|
| 2707 |
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
|
|
| 2708 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
|
|
| 2378 | 2709 |
} |
| 2379 | 2710 |
|
| 2380 | 2711 |
static inline void gen_stq_env_A0(int idx, int offset) |
| 2381 | 2712 |
{
|
| 2382 | 2713 |
int mem_index = (idx >> 2) - 1; |
| 2383 |
tcg_gen_ld_i64(cpu_tmp1, cpu_env, offset); |
|
| 2384 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, mem_index); |
|
| 2714 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
|
|
| 2715 |
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
|
|
| 2385 | 2716 |
} |
| 2386 | 2717 |
|
| 2387 | 2718 |
static inline void gen_ldo_env_A0(int idx, int offset) |
| 2388 | 2719 |
{
|
| 2389 | 2720 |
int mem_index = (idx >> 2) - 1; |
| 2390 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, mem_index); |
|
| 2391 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
|
| 2721 |
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
|
|
| 2722 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
|
|
| 2392 | 2723 |
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
| 2393 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_tmp0, mem_index); |
|
| 2394 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
|
| 2724 |
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
|
|
| 2725 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
|
|
| 2395 | 2726 |
} |
| 2396 | 2727 |
|
| 2397 | 2728 |
static inline void gen_sto_env_A0(int idx, int offset) |
| 2398 | 2729 |
{
|
| 2399 | 2730 |
int mem_index = (idx >> 2) - 1; |
| 2400 |
tcg_gen_ld_i64(cpu_tmp1, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); |
|
| 2401 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, mem_index); |
|
| 2731 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
|
|
| 2732 |
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
|
|
| 2402 | 2733 |
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); |
| 2403 |
tcg_gen_ld_i64(cpu_tmp1, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); |
|
| 2404 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_tmp0, mem_index); |
|
| 2734 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
|
|
| 2735 |
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
|
|
| 2405 | 2736 |
} |
| 2406 | 2737 |
|
| 2407 | 2738 |
static inline void gen_op_movo(int d_offset, int s_offset) |
| 2408 | 2739 |
{
|
| 2409 |
tcg_gen_ld_i64(cpu_tmp1, cpu_env, s_offset); |
|
| 2410 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, d_offset); |
|
| 2411 |
tcg_gen_ld_i64(cpu_tmp1, cpu_env, s_offset + 8); |
|
| 2412 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, d_offset + 8); |
|
| 2740 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
|
|
| 2741 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
|
|
| 2742 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
|
|
| 2743 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
|
|
| 2413 | 2744 |
} |
| 2414 | 2745 |
|
| 2415 | 2746 |
static inline void gen_op_movq(int d_offset, int s_offset) |
| 2416 | 2747 |
{
|
| 2417 |
tcg_gen_ld_i64(cpu_tmp1, cpu_env, s_offset); |
|
| 2418 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, d_offset); |
|
| 2748 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
|
|
| 2749 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
|
|
| 2419 | 2750 |
} |
| 2420 | 2751 |
|
| 2421 | 2752 |
static inline void gen_op_movl(int d_offset, int s_offset) |
| 2422 | 2753 |
{
|
| 2423 |
tcg_gen_ld_i32(cpu_tmp2, cpu_env, s_offset); |
|
| 2424 |
tcg_gen_st_i32(cpu_tmp2, cpu_env, d_offset); |
|
| 2754 |
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
|
|
| 2755 |
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
|
|
| 2425 | 2756 |
} |
| 2426 | 2757 |
|
| 2427 | 2758 |
static inline void gen_op_movq_env_0(int d_offset) |
| 2428 | 2759 |
{
|
| 2429 |
tcg_gen_movi_i64(cpu_tmp1, 0); |
|
| 2430 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, d_offset); |
|
| 2760 |
tcg_gen_movi_i64(cpu_tmp1_i64, 0);
|
|
| 2761 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
|
|
| 2431 | 2762 |
} |
| 2432 | 2763 |
|
| 2433 | 2764 |
#define SSE_SPECIAL ((void *)1) |
| ... | ... | |
| 2739 | 3070 |
gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); |
| 2740 | 3071 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
| 2741 | 3072 |
offsetof(CPUX86State,xmm_regs[reg])); |
| 2742 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 2743 |
tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2); |
|
| 3073 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 3074 |
tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32);
|
|
| 2744 | 3075 |
} |
| 2745 | 3076 |
break; |
| 2746 | 3077 |
case 0x6f: /* movq mm, ea */ |
| ... | ... | |
| 2749 | 3080 |
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); |
| 2750 | 3081 |
} else {
|
| 2751 | 3082 |
rm = (modrm & 7); |
| 2752 |
tcg_gen_ld_i64(cpu_tmp1, cpu_env, |
|
| 3083 |
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
|
|
| 2753 | 3084 |
offsetof(CPUX86State,fpregs[rm].mmx)); |
| 2754 |
tcg_gen_st_i64(cpu_tmp1, cpu_env, |
|
| 3085 |
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
|
|
| 2755 | 3086 |
offsetof(CPUX86State,fpregs[reg].mmx)); |
| 2756 | 3087 |
} |
| 2757 | 3088 |
break; |
| ... | ... | |
| 3007 | 3338 |
rm = (modrm & 7) | REX_B(s); |
| 3008 | 3339 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
| 3009 | 3340 |
offsetof(CPUX86State,xmm_regs[rm])); |
| 3010 |
tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2, cpu_ptr0); |
|
| 3011 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 3341 |
tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0);
|
|
| 3342 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 3012 | 3343 |
gen_op_mov_reg_T0(OT_LONG, reg); |
| 3013 | 3344 |
break; |
| 3014 | 3345 |
case 0x150: /* movmskpd */ |
| 3015 | 3346 |
rm = (modrm & 7) | REX_B(s); |
| 3016 | 3347 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, |
| 3017 | 3348 |
offsetof(CPUX86State,xmm_regs[rm])); |
| 3018 |
tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2, cpu_ptr0); |
|
| 3019 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 3349 |
tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0);
|
|
| 3350 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 3020 | 3351 |
gen_op_mov_reg_T0(OT_LONG, reg); |
| 3021 | 3352 |
break; |
| 3022 | 3353 |
case 0x02a: /* cvtpi2ps */ |
| ... | ... | |
| 3050 | 3381 |
op1_offset = offsetof(CPUX86State,xmm_regs[reg]); |
| 3051 | 3382 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); |
| 3052 | 3383 |
sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)]; |
| 3053 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 3054 |
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2); |
|
| 3384 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 3385 |
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32);
|
|
| 3055 | 3386 |
break; |
| 3056 | 3387 |
case 0x02c: /* cvttps2pi */ |
| 3057 | 3388 |
case 0x12c: /* cvttpd2pi */ |
| ... | ... | |
| 3106 | 3437 |
(b & 1) * 4]; |
| 3107 | 3438 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); |
| 3108 | 3439 |
if (ot == OT_LONG) {
|
| 3109 |
tcg_gen_helper_1_1(sse_op2, cpu_tmp2, cpu_ptr0); |
|
| 3110 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 3440 |
tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0);
|
|
| 3441 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 3111 | 3442 |
} else {
|
| 3112 | 3443 |
tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0); |
| 3113 | 3444 |
} |
| ... | ... | |
| 3178 | 3509 |
if (b1) {
|
| 3179 | 3510 |
rm = (modrm & 7) | REX_B(s); |
| 3180 | 3511 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); |
| 3181 |
tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2, cpu_ptr0); |
|
| 3512 |
tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0);
|
|
| 3182 | 3513 |
} else {
|
| 3183 | 3514 |
rm = (modrm & 7); |
| 3184 | 3515 |
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); |
| 3185 |
tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2, cpu_ptr0); |
|
| 3516 |
tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0);
|
|
| 3186 | 3517 |
} |
| 3187 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 3518 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 3188 | 3519 |
reg = ((modrm >> 3) & 7) | rex_r; |
| 3189 | 3520 |
gen_op_mov_reg_T0(OT_LONG, reg); |
| 3190 | 3521 |
break; |
| ... | ... | |
| 3590 | 3921 |
s->cc_op = CC_OP_LOGICB + ot; |
| 3591 | 3922 |
break; |
| 3592 | 3923 |
case 2: /* not */ |
| 3593 |
gen_op_notl_T0();
|
|
| 3924 |
tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
|
|
| 3594 | 3925 |
if (mod != 3) {
|
| 3595 | 3926 |
gen_op_st_T0_A0(ot + s->mem_index); |
| 3596 | 3927 |
} else {
|
| ... | ... | |
| 3598 | 3929 |
} |
| 3599 | 3930 |
break; |
| 3600 | 3931 |
case 3: /* neg */ |
| 3601 |
gen_op_negl_T0();
|
|
| 3932 |
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
|
|
| 3602 | 3933 |
if (mod != 3) {
|
| 3603 | 3934 |
gen_op_st_T0_A0(ot + s->mem_index); |
| 3604 | 3935 |
} else {
|
| ... | ... | |
| 3773 | 4104 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 3774 | 4105 |
gen_op_set_cc_op(s->cc_op); |
| 3775 | 4106 |
gen_jmp_im(pc_start - s->cs_base); |
| 3776 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4107 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 3777 | 4108 |
tcg_gen_helper_0_4(helper_lcall_protected, |
| 3778 |
cpu_tmp2, cpu_T[1], |
|
| 4109 |
cpu_tmp2_i32, cpu_T[1],
|
|
| 3779 | 4110 |
tcg_const_i32(dflag), |
| 3780 | 4111 |
tcg_const_i32(s->pc - pc_start)); |
| 3781 | 4112 |
} else {
|
| 3782 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4113 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 3783 | 4114 |
tcg_gen_helper_0_4(helper_lcall_real, |
| 3784 |
cpu_tmp2, cpu_T[1], |
|
| 4115 |
cpu_tmp2_i32, cpu_T[1],
|
|
| 3785 | 4116 |
tcg_const_i32(dflag), |
| 3786 | 4117 |
tcg_const_i32(s->pc - s->cs_base)); |
| 3787 | 4118 |
} |
| ... | ... | |
| 3802 | 4133 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 3803 | 4134 |
gen_op_set_cc_op(s->cc_op); |
| 3804 | 4135 |
gen_jmp_im(pc_start - s->cs_base); |
| 3805 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4136 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 3806 | 4137 |
tcg_gen_helper_0_3(helper_ljmp_protected, |
| 3807 |
cpu_tmp2, |
|
| 4138 |
cpu_tmp2_i32,
|
|
| 3808 | 4139 |
cpu_T[1], |
| 3809 | 4140 |
tcg_const_i32(s->pc - pc_start)); |
| 3810 | 4141 |
} else {
|
| ... | ... | |
| 4474 | 4805 |
mod = (modrm >> 6) & 3; |
| 4475 | 4806 |
rm = (modrm & 7) | REX_B(s); |
| 4476 | 4807 |
reg = ((modrm >> 3) & 7) | rex_r; |
| 4477 |
|
|
| 4478 | 4808 |
if (mod != 3) {
|
| 4479 | 4809 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
| 4480 |
gen_op_ld_T0_A0(ot + s->mem_index);
|
|
| 4810 |
opreg = OR_TMP0;
|
|
| 4481 | 4811 |
} else {
|
| 4482 |
gen_op_mov_TN_reg(ot, 0, rm);
|
|
| 4812 |
opreg = rm;
|
|
| 4483 | 4813 |
} |
| 4484 | 4814 |
gen_op_mov_TN_reg(ot, 1, reg); |
| 4485 | 4815 |
|
| 4486 | 4816 |
if (shift) {
|
| 4487 | 4817 |
val = ldub_code(s->pc++); |
| 4488 |
if (ot == OT_QUAD) |
|
| 4489 |
val &= 0x3f; |
|
| 4490 |
else |
|
| 4491 |
val &= 0x1f; |
|
| 4492 |
if (val) {
|
|
| 4493 |
if (mod == 3) |
|
| 4494 |
gen_op_shiftd_T0_T1_im_cc[ot][op](val); |
|
| 4495 |
else |
|
| 4496 |
gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val); |
|
| 4497 |
if (op == 0 && ot != OT_WORD) |
|
| 4498 |
s->cc_op = CC_OP_SHLB + ot; |
|
| 4499 |
else |
|
| 4500 |
s->cc_op = CC_OP_SARB + ot; |
|
| 4501 |
} |
|
| 4818 |
tcg_gen_movi_tl(cpu_T3, val); |
|
| 4502 | 4819 |
} else {
|
| 4503 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
| 4504 |
gen_op_set_cc_op(s->cc_op); |
|
| 4505 |
if (mod == 3) |
|
| 4506 |
gen_op_shiftd_T0_T1_ECX_cc[ot][op](); |
|
| 4507 |
else |
|
| 4508 |
gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op](); |
|
| 4509 |
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
|
| 4510 |
} |
|
| 4511 |
if (mod == 3) {
|
|
| 4512 |
gen_op_mov_reg_T0(ot, rm); |
|
| 4820 |
tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX])); |
|
| 4513 | 4821 |
} |
| 4822 |
gen_shiftd_rm_T1_T3(s, ot, opreg, op); |
|
| 4514 | 4823 |
break; |
| 4515 | 4824 |
|
| 4516 | 4825 |
/************************/ |
| ... | ... | |
| 4541 | 4850 |
switch(op >> 4) {
|
| 4542 | 4851 |
case 0: |
| 4543 | 4852 |
gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
| 4544 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4545 |
tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2); |
|
| 4853 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 4854 |
tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32);
|
|
| 4546 | 4855 |
break; |
| 4547 | 4856 |
case 1: |
| 4548 | 4857 |
gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
| 4549 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4550 |
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2); |
|
| 4858 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 4859 |
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
|
|
| 4551 | 4860 |
break; |
| 4552 | 4861 |
case 2: |
| 4553 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, |
|
| 4862 |
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
|
|
| 4554 | 4863 |
(s->mem_index >> 2) - 1); |
| 4555 |
tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1); |
|
| 4864 |
tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64);
|
|
| 4556 | 4865 |
break; |
| 4557 | 4866 |
case 3: |
| 4558 | 4867 |
default: |
| 4559 | 4868 |
gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
| 4560 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4561 |
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2); |
|
| 4869 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 4870 |
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
|
|
| 4562 | 4871 |
break; |
| 4563 | 4872 |
} |
| 4564 | 4873 |
|
| ... | ... | |
| 4580 | 4889 |
switch(op >> 4) {
|
| 4581 | 4890 |
case 0: |
| 4582 | 4891 |
gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
| 4583 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4584 |
tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2); |
|
| 4892 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 4893 |
tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32);
|
|
| 4585 | 4894 |
break; |
| 4586 | 4895 |
case 1: |
| 4587 | 4896 |
gen_op_ld_T0_A0(OT_LONG + s->mem_index); |
| 4588 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4589 |
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2); |
|
| 4897 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 4898 |
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
|
|
| 4590 | 4899 |
break; |
| 4591 | 4900 |
case 2: |
| 4592 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, |
|
| 4901 |
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
|
|
| 4593 | 4902 |
(s->mem_index >> 2) - 1); |
| 4594 |
tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1); |
|
| 4903 |
tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64);
|
|
| 4595 | 4904 |
break; |
| 4596 | 4905 |
case 3: |
| 4597 | 4906 |
default: |
| 4598 | 4907 |
gen_op_lds_T0_A0(OT_WORD + s->mem_index); |
| 4599 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4600 |
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2); |
|
| 4908 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 4909 |
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
|
|
| 4601 | 4910 |
break; |
| 4602 | 4911 |
} |
| 4603 | 4912 |
break; |
| ... | ... | |
| 4605 | 4914 |
/* XXX: the corresponding CPUID bit must be tested ! */ |
| 4606 | 4915 |
switch(op >> 4) {
|
| 4607 | 4916 |
case 1: |
| 4608 |
tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2); |
|
| 4609 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4917 |
tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32);
|
|
| 4918 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4610 | 4919 |
gen_op_st_T0_A0(OT_LONG + s->mem_index); |
| 4611 | 4920 |
break; |
| 4612 | 4921 |
case 2: |
| 4613 |
tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1); |
|
| 4614 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, |
|
| 4922 |
tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64);
|
|
| 4923 |
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
|
|
| 4615 | 4924 |
(s->mem_index >> 2) - 1); |
| 4616 | 4925 |
break; |
| 4617 | 4926 |
case 3: |
| 4618 | 4927 |
default: |
| 4619 |
tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2); |
|
| 4620 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4928 |
tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32);
|
|
| 4929 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4621 | 4930 |
gen_op_st_T0_A0(OT_WORD + s->mem_index); |
| 4622 | 4931 |
break; |
| 4623 | 4932 |
} |
| ... | ... | |
| 4626 | 4935 |
default: |
| 4627 | 4936 |
switch(op >> 4) {
|
| 4628 | 4937 |
case 0: |
| 4629 |
tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2); |
|
| 4630 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4938 |
tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32);
|
|
| 4939 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4631 | 4940 |
gen_op_st_T0_A0(OT_LONG + s->mem_index); |
| 4632 | 4941 |
break; |
| 4633 | 4942 |
case 1: |
| 4634 |
tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2); |
|
| 4635 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4943 |
tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32);
|
|
| 4944 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4636 | 4945 |
gen_op_st_T0_A0(OT_LONG + s->mem_index); |
| 4637 | 4946 |
break; |
| 4638 | 4947 |
case 2: |
| 4639 |
tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1); |
|
| 4640 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, |
|
| 4948 |
tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64);
|
|
| 4949 |
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
|
|
| 4641 | 4950 |
(s->mem_index >> 2) - 1); |
| 4642 | 4951 |
break; |
| 4643 | 4952 |
case 3: |
| 4644 | 4953 |
default: |
| 4645 |
tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2); |
|
| 4646 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4954 |
tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32);
|
|
| 4955 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4647 | 4956 |
gen_op_st_T0_A0(OT_WORD + s->mem_index); |
| 4648 | 4957 |
break; |
| 4649 | 4958 |
} |
| ... | ... | |
| 4661 | 4970 |
break; |
| 4662 | 4971 |
case 0x0d: /* fldcw mem */ |
| 4663 | 4972 |
gen_op_ld_T0_A0(OT_WORD + s->mem_index); |
| 4664 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 4665 |
tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2); |
|
| 4973 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 4974 |
tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32);
|
|
| 4666 | 4975 |
break; |
| 4667 | 4976 |
case 0x0e: /* fnstenv mem */ |
| 4668 | 4977 |
if (s->cc_op != CC_OP_DYNAMIC) |
| ... | ... | |
| 4672 | 4981 |
cpu_A0, tcg_const_i32(s->dflag)); |
| 4673 | 4982 |
break; |
| 4674 | 4983 |
case 0x0f: /* fnstcw mem */ |
| 4675 |
tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2); |
|
| 4676 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 4984 |
tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32);
|
|
| 4985 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4677 | 4986 |
gen_op_st_T0_A0(OT_WORD + s->mem_index); |
| 4678 | 4987 |
break; |
| 4679 | 4988 |
case 0x1d: /* fldt mem */ |
| ... | ... | |
| 4704 | 5013 |
cpu_A0, tcg_const_i32(s->dflag)); |
| 4705 | 5014 |
break; |
| 4706 | 5015 |
case 0x2f: /* fnstsw mem */ |
| 4707 |
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2); |
|
| 4708 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 5016 |
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
|
|
| 5017 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4709 | 5018 |
gen_op_st_T0_A0(OT_WORD + s->mem_index); |
| 4710 | 5019 |
break; |
| 4711 | 5020 |
case 0x3c: /* fbld */ |
| ... | ... | |
| 4722 | 5031 |
tcg_gen_helper_0_0(helper_fpop); |
| 4723 | 5032 |
break; |
| 4724 | 5033 |
case 0x3d: /* fildll */ |
| 4725 |
tcg_gen_qemu_ld64(cpu_tmp1, cpu_A0, |
|
| 5034 |
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
|
|
| 4726 | 5035 |
(s->mem_index >> 2) - 1); |
| 4727 |
tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1); |
|
| 5036 |
tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64);
|
|
| 4728 | 5037 |
break; |
| 4729 | 5038 |
case 0x3f: /* fistpll */ |
| 4730 |
tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1); |
|
| 4731 |
tcg_gen_qemu_st64(cpu_tmp1, cpu_A0, |
|
| 5039 |
tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64);
|
|
| 5040 |
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
|
|
| 4732 | 5041 |
(s->mem_index >> 2) - 1); |
| 4733 | 5042 |
tcg_gen_helper_0_0(helper_fpop); |
| 4734 | 5043 |
break; |
| ... | ... | |
| 4991 | 5300 |
case 0x3c: /* df/4 */ |
| 4992 | 5301 |
switch(rm) {
|
| 4993 | 5302 |
case 0: |
| 4994 |
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2); |
|
| 4995 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2); |
|
| 5303 |
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
|
|
| 5304 |
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
|
|
| 4996 | 5305 |
gen_op_mov_reg_T0(OT_WORD, R_EAX); |
| 4997 | 5306 |
break; |
| 4998 | 5307 |
default: |
| ... | ... | |
| 5159 | 5468 |
gen_op_movl_T0_im(val); |
| 5160 | 5469 |
gen_check_io(s, ot, pc_start - s->cs_base, |
| 5161 | 5470 |
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); |
| 5162 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5163 |
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2); |
|
| 5471 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 5472 |
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
|
|
| 5164 | 5473 |
gen_op_mov_reg_T1(ot, R_EAX); |
| 5165 | 5474 |
break; |
| 5166 | 5475 |
case 0xe6: |
| ... | ... | |
| 5175 | 5484 |
svm_is_rep(prefixes)); |
| 5176 | 5485 |
gen_op_mov_TN_reg(ot, 1, R_EAX); |
| 5177 | 5486 |
|
| 5178 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5179 |
tcg_gen_andi_i32(cpu_tmp2, cpu_tmp2, 0xffff);
|
|
| 5180 |
tcg_gen_trunc_tl_i32(cpu_tmp3, cpu_T[1]); |
|
| 5181 |
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2, cpu_tmp3);
|
|
| 5487 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 5488 |
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
|
| 5489 |
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
|
|
| 5490 |
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
|
|
| 5182 | 5491 |
break; |
| 5183 | 5492 |
case 0xec: |
| 5184 | 5493 |
case 0xed: |
| ... | ... | |
| 5190 | 5499 |
gen_op_andl_T0_ffff(); |
| 5191 | 5500 |
gen_check_io(s, ot, pc_start - s->cs_base, |
| 5192 | 5501 |
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); |
| 5193 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5194 |
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2); |
|
| 5502 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 5503 |
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
|
|
| 5195 | 5504 |
gen_op_mov_reg_T1(ot, R_EAX); |
| 5196 | 5505 |
break; |
| 5197 | 5506 |
case 0xee: |
| ... | ... | |
| 5206 | 5515 |
svm_is_rep(prefixes)); |
| 5207 | 5516 |
gen_op_mov_TN_reg(ot, 1, R_EAX); |
| 5208 | 5517 |
|
| 5209 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5210 |
tcg_gen_andi_i32(cpu_tmp2, cpu_tmp2, 0xffff);
|
|
| 5211 |
tcg_gen_trunc_tl_i32(cpu_tmp3, cpu_T[1]); |
|
| 5212 |
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2, cpu_tmp3);
|
|
| 5518 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 5519 |
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
|
|
| 5520 |
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
|
|
| 5521 |
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
|
|
| 5213 | 5522 |
break; |
| 5214 | 5523 |
|
| 5215 | 5524 |
/************************/ |
| ... | ... | |
| 5474 | 5783 |
s->cc_op = CC_OP_EFLAGS; |
| 5475 | 5784 |
break; |
| 5476 | 5785 |
case 0xfc: /* cld */ |
| 5477 |
tcg_gen_movi_i32(cpu_tmp2, 1); |
|
| 5478 |
tcg_gen_st_i32(cpu_tmp2, cpu_env, offsetof(CPUState, df)); |
|
| 5786 |
tcg_gen_movi_i32(cpu_tmp2_i32, 1);
|
|
| 5787 |
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
|
|
| 5479 | 5788 |
break; |
| 5480 | 5789 |
case 0xfd: /* std */ |
| 5481 |
tcg_gen_movi_i32(cpu_tmp2, -1); |
|
| 5482 |
tcg_gen_st_i32(cpu_tmp2, cpu_env, offsetof(CPUState, df)); |
|
| 5790 |
tcg_gen_movi_i32(cpu_tmp2_i32, -1);
|
|
| 5791 |
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
|
|
| 5483 | 5792 |
break; |
| 5484 | 5793 |
|
| 5485 | 5794 |
/************************/ |
| ... | ... | |
| 5723 | 6032 |
gen_op_mov_TN_reg(ot, 0, reg); |
| 5724 | 6033 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
| 5725 | 6034 |
gen_jmp_im(pc_start - s->cs_base); |
| 5726 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 6035 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 5727 | 6036 |
if (ot == OT_WORD) |
| 5728 |
tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2); |
|
| 6037 |
tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32);
|
|
| 5729 | 6038 |
else |
| 5730 |
tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2); |
|
| 6039 |
tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32);
|
|
| 5731 | 6040 |
break; |
| 5732 | 6041 |
case 0x1c8 ... 0x1cf: /* bswap reg */ |
| 5733 | 6042 |
reg = (b & 7) | REX_B(s); |
| ... | ... | |
| 5927 | 6236 |
break; |
| 5928 | 6237 |
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
| 5929 | 6238 |
gen_jmp_im(pc_start - s->cs_base); |
| 5930 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5931 |
tcg_gen_helper_0_1(helper_lldt, cpu_tmp2); |
|
| 6239 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 6240 |
tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32);
|
|
| 5932 | 6241 |
} |
| 5933 | 6242 |
break; |
| 5934 | 6243 |
case 1: /* str */ |
| ... | ... | |
| 5952 | 6261 |
break; |
| 5953 | 6262 |
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
| 5954 | 6263 |
gen_jmp_im(pc_start - s->cs_base); |
| 5955 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5956 |
tcg_gen_helper_0_1(helper_ltr, cpu_tmp2); |
|
| 6264 |
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
|
|
| 6265 |
tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32);
|
|
| 5957 | 6266 |
} |
| 5958 | 6267 |
break; |
| 5959 | 6268 |
case 4: /* verr */ |
| ... | ... | |
| 6499 | 6808 |
return s->pc; |
| 6500 | 6809 |
} |
| 6501 | 6810 |
|
| 6502 |
#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C) |
|
| 6503 |
#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P) |
|
| 6504 |
|
|
| 6505 |
/* flags read by an operation */ |
|
| 6506 |
static uint16_t opc_read_flags[NB_OPS] = {
|
|
| 6507 |
[INDEX_op_aas] = CC_A, |
|
| 6508 |
[INDEX_op_aaa] = CC_A, |
|
| 6509 |
[INDEX_op_das] = CC_A | CC_C, |
|
| 6510 |
[INDEX_op_daa] = CC_A | CC_C, |
|
| 6511 |
|
|
| 6512 |
/* subtle: due to the incl/decl implementation, C is used */ |
|
| 6513 |
[INDEX_op_update_inc_cc] = CC_C, |
|
| 6514 |
|
|
| 6515 |
[INDEX_op_into] = CC_O, |
|
| 6516 |
|
|
| 6517 |
[INDEX_op_jb_subb] = CC_C, |
|
| 6518 |
[INDEX_op_jb_subw] = CC_C, |
|
| 6519 |
[INDEX_op_jb_subl] = CC_C, |
|
| 6520 |
|
|
| 6521 |
[INDEX_op_jz_subb] = CC_Z, |
|
| 6522 |
[INDEX_op_jz_subw] = CC_Z, |
|
| 6523 |
[INDEX_op_jz_subl] = CC_Z, |
|
| 6524 |
|
|
| 6525 |
[INDEX_op_jbe_subb] = CC_Z | CC_C, |
|
| 6526 |
[INDEX_op_jbe_subw] = CC_Z | CC_C, |
|
| 6527 |
[INDEX_op_jbe_subl] = CC_Z | CC_C, |
|
| 6528 |
|
|
| 6529 |
[INDEX_op_js_subb] = CC_S, |
|
| 6530 |
[INDEX_op_js_subw] = CC_S, |
|
| 6531 |
[INDEX_op_js_subl] = CC_S, |
|
| 6532 |
|
|
| 6533 |
[INDEX_op_jl_subb] = CC_O | CC_S, |
|
| 6534 |
[INDEX_op_jl_subw] = CC_O | CC_S, |
|
| 6535 |
[INDEX_op_jl_subl] = CC_O | CC_S, |
|
| 6536 |
|
|
| 6537 |
[INDEX_op_jle_subb] = CC_O | CC_S | CC_Z, |
|
| 6538 |
[INDEX_op_jle_subw] = CC_O | CC_S | CC_Z, |
|
| 6539 |
[INDEX_op_jle_subl] = CC_O | CC_S | CC_Z, |
|
| 6540 |
|
|
| 6541 |
[INDEX_op_loopnzw] = CC_Z, |
|
| 6542 |
[INDEX_op_loopnzl] = CC_Z, |
|
| 6543 |
[INDEX_op_loopzw] = CC_Z, |
|
| 6544 |
[INDEX_op_loopzl] = CC_Z, |
|
| 6545 |
|
|
| 6546 |
[INDEX_op_seto_T0_cc] = CC_O, |
|
| 6547 |
[INDEX_op_setb_T0_cc] = CC_C, |
|
| 6548 |
[INDEX_op_setz_T0_cc] = CC_Z, |
|
| 6549 |
[INDEX_op_setbe_T0_cc] = CC_Z | CC_C, |
|
| 6550 |
[INDEX_op_sets_T0_cc] = CC_S, |
|
| 6551 |
[INDEX_op_setp_T0_cc] = CC_P, |
|
| 6552 |
[INDEX_op_setl_T0_cc] = CC_O | CC_S, |
|
| 6553 |
[INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z, |
|
| 6554 |
|
|
| 6555 |
[INDEX_op_setb_T0_subb] = CC_C, |
|
| 6556 |
[INDEX_op_setb_T0_subw] = CC_C, |
|
| 6557 |
[INDEX_op_setb_T0_subl] = CC_C, |
|
| 6558 |
|
|
| 6559 |
[INDEX_op_setz_T0_subb] = CC_Z, |
|
| 6560 |
[INDEX_op_setz_T0_subw] = CC_Z, |
|
| 6561 |
[INDEX_op_setz_T0_subl] = CC_Z, |
|
| 6562 |
|
|
| 6563 |
[INDEX_op_setbe_T0_subb] = CC_Z | CC_C, |
|
| 6564 |
[INDEX_op_setbe_T0_subw] = CC_Z | CC_C, |
|
| 6565 |
[INDEX_op_setbe_T0_subl] = CC_Z | CC_C, |
|
| 6566 |
|
|
| 6567 |
[INDEX_op_sets_T0_subb] = CC_S, |
|
| 6568 |
[INDEX_op_sets_T0_subw] = CC_S, |
|
| 6569 |
[INDEX_op_sets_T0_subl] = CC_S, |
|
| 6570 |
|
|
| 6571 |
[INDEX_op_setl_T0_subb] = CC_O | CC_S, |
|
| 6572 |
[INDEX_op_setl_T0_subw] = CC_O | CC_S, |
|
| 6573 |
[INDEX_op_setl_T0_subl] = CC_O | CC_S, |
|
| 6574 |
|
|
| 6575 |
[INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z, |
|
| 6576 |
[INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z, |
|
| 6577 |
[INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z, |
|
| 6578 |
|
|
| 6579 |
[INDEX_op_movl_T0_eflags] = CC_OSZAPC, |
|
| 6580 |
[INDEX_op_cmc] = CC_C, |
|
| 6581 |
[INDEX_op_salc] = CC_C, |
|
| 6582 |
|
|
| 6583 |
/* needed for correct flag optimisation before string ops */ |
|
| 6584 |
[INDEX_op_jnz_ecxw] = CC_OSZAPC, |
|
| 6585 |
[INDEX_op_jnz_ecxl] = CC_OSZAPC, |
|
| 6586 |
[INDEX_op_jz_ecxw] = CC_OSZAPC, |
|
| 6587 |
[INDEX_op_jz_ecxl] = CC_OSZAPC, |
|
| 6588 |
|
|
| 6589 |
#ifdef TARGET_X86_64 |
|
| 6590 |
[INDEX_op_jb_subq] = CC_C, |
|
| 6591 |
[INDEX_op_jz_subq] = CC_Z, |
|
| 6592 |
[INDEX_op_jbe_subq] = CC_Z | CC_C, |
|
| 6593 |
[INDEX_op_js_subq] = CC_S, |
|
| 6594 |
[INDEX_op_jl_subq] = CC_O | CC_S, |
|
| 6595 |
[INDEX_op_jle_subq] = CC_O | CC_S | CC_Z, |
|
| 6596 |
|
|
| 6597 |
[INDEX_op_loopnzq] = CC_Z, |
|
| 6598 |
[INDEX_op_loopzq] = CC_Z, |
|
| 6599 |
|
|
| 6600 |
[INDEX_op_setb_T0_subq] = CC_C, |
|
| 6601 |
[INDEX_op_setz_T0_subq] = CC_Z, |
|
| 6602 |
[INDEX_op_setbe_T0_subq] = CC_Z | CC_C, |
|
| 6603 |
[INDEX_op_sets_T0_subq] = CC_S, |
|
| 6604 |
[INDEX_op_setl_T0_subq] = CC_O | CC_S, |
|
| 6605 |
[INDEX_op_setle_T0_subq] = CC_O | CC_S | CC_Z, |
|
| 6606 |
|
|
| 6607 |
[INDEX_op_jnz_ecxq] = CC_OSZAPC, |
|
| 6608 |
[INDEX_op_jz_ecxq] = CC_OSZAPC, |
|
| 6609 |
#endif |
|
| 6610 |
|
|
| 6611 |
#define DEF_READF(SUFFIX)\ |
|
| 6612 |
[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6613 |
[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6614 |
[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6615 |
X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_C,)\ |
|
| 6616 |
[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6617 |
[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6618 |
[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6619 |
X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_C,)\ |
|
| 6620 |
\ |
|
| 6621 |
[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6622 |
[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6623 |
[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6624 |
X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_C,)\ |
|
| 6625 |
[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6626 |
[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6627 |
[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,\ |
|
| 6628 |
X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_C,) |
|
| 6629 |
|
|
| 6630 |
DEF_READF( ) |
|
| 6631 |
DEF_READF(_raw) |
|
| 6632 |
#ifndef CONFIG_USER_ONLY |
|
| 6633 |
DEF_READF(_kernel) |
|
| 6634 |
DEF_READF(_user) |
|
| 6635 |
#endif |
|
| 6636 |
}; |
|
| 6637 |
|
|
| 6638 |
/* flags written by an operation */ |
|
| 6639 |
static uint16_t opc_write_flags[NB_OPS] = {
|
|
| 6640 |
[INDEX_op_update2_cc] = CC_OSZAPC, |
|
| 6641 |
[INDEX_op_update1_cc] = CC_OSZAPC, |
|
| 6642 |
[INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC, |
|
| 6643 |
[INDEX_op_update_neg_cc] = CC_OSZAPC, |
|
| 6644 |
/* subtle: due to the incl/decl implementation, C is used */ |
|
| 6645 |
[INDEX_op_update_inc_cc] = CC_OSZAPC, |
|
| 6646 |
[INDEX_op_testl_T0_T1_cc] = CC_OSZAPC, |
|
| 6647 |
|
|
| 6648 |
[INDEX_op_mulb_AL_T0] = CC_OSZAPC, |
|
| 6649 |
[INDEX_op_mulw_AX_T0] = CC_OSZAPC, |
|
| 6650 |
[INDEX_op_mull_EAX_T0] = CC_OSZAPC, |
|
| 6651 |
X86_64_DEF([INDEX_op_mulq_EAX_T0] = CC_OSZAPC,) |
|
| 6652 |
[INDEX_op_imulb_AL_T0] = CC_OSZAPC, |
|
| 6653 |
[INDEX_op_imulw_AX_T0] = CC_OSZAPC, |
|
| 6654 |
[INDEX_op_imull_EAX_T0] = CC_OSZAPC, |
|
| 6655 |
X86_64_DEF([INDEX_op_imulq_EAX_T0] = CC_OSZAPC,) |
|
| 6656 |
[INDEX_op_imulw_T0_T1] = CC_OSZAPC, |
|
| 6657 |
[INDEX_op_imull_T0_T1] = CC_OSZAPC, |
|
| 6658 |
X86_64_DEF([INDEX_op_imulq_T0_T1] = CC_OSZAPC,) |
|
| 6659 |
|
|
| 6660 |
/* sse */ |
|
| 6661 |
[INDEX_op_com_dummy] = CC_OSZAPC, |
|
| 6662 |
[INDEX_op_com_dummy] = CC_OSZAPC, |
|
| 6663 |
[INDEX_op_com_dummy] = CC_OSZAPC, |
|
| 6664 |
[INDEX_op_com_dummy] = CC_OSZAPC, |
|
| 6665 |
|
|
| 6666 |
/* bcd */ |
|
| 6667 |
[INDEX_op_aam] = CC_OSZAPC, |
|
| 6668 |
[INDEX_op_aad] = CC_OSZAPC, |
|
| 6669 |
[INDEX_op_aas] = CC_OSZAPC, |
|
| 6670 |
[INDEX_op_aaa] = CC_OSZAPC, |
|
| 6671 |
[INDEX_op_das] = CC_OSZAPC, |
|
| 6672 |
[INDEX_op_daa] = CC_OSZAPC, |
|
| 6673 |
|
|
| 6674 |
[INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C, |
|
| 6675 |
[INDEX_op_movw_eflags_T0] = CC_OSZAPC, |
|
| 6676 |
[INDEX_op_movl_eflags_T0] = CC_OSZAPC, |
|
| 6677 |
[INDEX_op_movw_eflags_T0_io] = CC_OSZAPC, |
|
| 6678 |
[INDEX_op_movl_eflags_T0_io] = CC_OSZAPC, |
|
| 6679 |
[INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC, |
|
| 6680 |
[INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC, |
|
| 6681 |
[INDEX_op_clc] = CC_C, |
|
| 6682 |
[INDEX_op_stc] = CC_C, |
|
| 6683 |
[INDEX_op_cmc] = CC_C, |
|
| 6684 |
|
|
| 6685 |
[INDEX_op_btw_T0_T1_cc] = CC_OSZAPC, |
|
| 6686 |
[INDEX_op_btl_T0_T1_cc] = CC_OSZAPC, |
|
| 6687 |
X86_64_DEF([INDEX_op_btq_T0_T1_cc] = CC_OSZAPC,) |
|
| 6688 |
[INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC, |
|
| 6689 |
[INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC, |
|
| 6690 |
X86_64_DEF([INDEX_op_btsq_T0_T1_cc] = CC_OSZAPC,) |
|
| 6691 |
[INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC, |
|
| 6692 |
[INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC, |
|
| 6693 |
X86_64_DEF([INDEX_op_btrq_T0_T1_cc] = CC_OSZAPC,) |
|
| 6694 |
[INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC, |
|
| 6695 |
[INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC, |
|
| 6696 |
X86_64_DEF([INDEX_op_btcq_T0_T1_cc] = CC_OSZAPC,) |
|
| 6697 |
|
|
| 6698 |
[INDEX_op_bsfw_T0_cc] = CC_OSZAPC, |
|
| 6699 |
[INDEX_op_bsfl_T0_cc] = CC_OSZAPC, |
|
| 6700 |
X86_64_DEF([INDEX_op_bsfq_T0_cc] = CC_OSZAPC,) |
|
| 6701 |
[INDEX_op_bsrw_T0_cc] = CC_OSZAPC, |
|
| 6702 |
[INDEX_op_bsrl_T0_cc] = CC_OSZAPC, |
|
| 6703 |
X86_64_DEF([INDEX_op_bsrq_T0_cc] = CC_OSZAPC,) |
|
| 6704 |
|
|
| 6705 |
[INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC, |
|
| 6706 |
[INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC, |
|
| 6707 |
[INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC, |
|
| 6708 |
X86_64_DEF([INDEX_op_cmpxchgq_T0_T1_EAX_cc] = CC_OSZAPC,) |
|
| 6709 |
|
|
| 6710 |
[INDEX_op_cmpxchg8b] = CC_Z, |
|
| 6711 |
[INDEX_op_lar] = CC_Z, |
|
| 6712 |
[INDEX_op_lsl] = CC_Z, |
|
| 6713 |
[INDEX_op_verr] = CC_Z, |
|
| 6714 |
[INDEX_op_verw] = CC_Z, |
|
| 6715 |
[INDEX_op_fcomi_dummy] = CC_Z | CC_P | CC_C, |
|
| 6716 |
[INDEX_op_fcomi_dummy] = CC_Z | CC_P | CC_C, |
|
| 6717 |
|
|
| 6718 |
#define DEF_WRITEF(SUFFIX)\ |
|
| 6719 |
[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\ |
|
| 6720 |
[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\ |
|
| 6721 |
[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\ |
|
| 6722 |
X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\ |
|
| 6723 |
[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\ |
|
| 6724 |
[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\ |
|
| 6725 |
[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\ |
|
| 6726 |
X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\ |
|
| 6727 |
\ |
|
| 6728 |
[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6729 |
[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6730 |
[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6731 |
X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\ |
|
| 6732 |
[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6733 |
[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6734 |
[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6735 |
X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\ |
|
| 6736 |
\ |
|
| 6737 |
[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6738 |
[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6739 |
[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\ |
|
| 6740 |
X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\ |
|
Also available in: Unified diff