Revision b6b8bd18

b/hw/ppc_chrp.c
26 26
#define BIOS_FILENAME "ppc_rom.bin"
27 27
#define NVRAM_SIZE        0x2000
28 28

  
29
#define KERNEL_LOAD_ADDR 0x01000000
30
#define INITRD_LOAD_ADDR 0x01800000
31

  
29 32
/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
30 33
   NVRAM (not implemented).  */
31 34

  
32 35
static int dbdma_mem_index;
33 36
static int cuda_mem_index;
37
static int ide0_mem_index;
38
static int ide1_mem_index;
34 39

  
35 40
/* DBDMA: currently no op - should suffice right now */
36 41

  
37 42
static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
38 43
{
44
    printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
39 45
}
40 46

  
41 47
static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
......
48 54

  
49 55
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
50 56
{
57
    printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
51 58
    return 0;
52 59
}
53 60

  
......
78 85
{
79 86
    cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
80 87
    cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
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    cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
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    cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
81 90
}
82 91

  
83 92
static void macio_init(void)
......
91 100
       in PearPC */
92 101
    d->config[0x00] = 0x6b; // vendor_id
93 102
    d->config[0x01] = 0x10;
94
    d->config[0x02] = 0x17;
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    d->config[0x02] = 0x22;
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    d->config[0x03] = 0x00;
96 105

  
97 106
    d->config[0x0a] = 0x00; // class_sub = pci2pci
......
113 122
		   const char *initrd_filename)
114 123
{
115 124
    char buf[1024];
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    openpic_t *openpic;
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    m48t59_t *nvram;
117 127
    int PPC_io_memory;
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    int ret, linux_boot, i, fd;
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    unsigned long bios_offset;
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    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
120 131
    
121 132
    linux_boot = (kernel_filename != NULL);
122 133

  
......
135 146
                                 BIOS_SIZE, bios_offset | IO_MEM_ROM);
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    cpu_single_env->nip = 0xfffffffc;
137 148

  
149
    if (linux_boot) {
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        kernel_base = KERNEL_LOAD_ADDR;
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        /* now we can load the kernel */
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        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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        if (kernel_size < 0) {
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            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
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                    kernel_filename);
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            exit(1);
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        }
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        /* load initrd */
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        if (initrd_filename) {
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            initrd_base = INITRD_LOAD_ADDR;
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            initrd_size = load_image(initrd_filename,
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                                     phys_ram_base + initrd_base);
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            if (initrd_size < 0) {
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                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
165
                        initrd_filename);
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                exit(1);
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            }
168
        } else {
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            initrd_base = 0;
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            initrd_size = 0;
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        }
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        boot_device = 'm';
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    } else {
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        kernel_base = 0;
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        kernel_size = 0;
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        initrd_base = 0;
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        initrd_size = 0;
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    }
138 179
    /* Register CPU as a 74x/75x */
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    cpu_ppc_register(cpu_single_env, 0x00080000);
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    /* Set time-base frequency to 100 Mhz */
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    cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
142 183

  
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    isa_mem_base = 0xc0000000;
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    isa_mem_base = 0x80000000;
144 185
    pci_pmac_init();
145 186

  
146
    /* Register 64 KB of ISA IO space */
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    /* Register 8 MB of ISA IO space */
147 188
    PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
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    cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory);
149
    //    cpu_register_physical_memory(0xfe000000, 0xfe010000, PPC_io_memory);
189
    cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
150 190

  
151 191
    /* init basic PC hardware */
152 192
    vga_initialize(ds, phys_ram_base + ram_size, ram_size, 
153 193
                   vga_ram_size, 1);
154
    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
155
    //    pic_init(openpic);
194
    openpic = openpic_init(0x00000000, 0xF0000000, 1);
195

  
196
    /* XXX: suppress that */
156 197
    pic_init();
157
    //    pit = pit_init(0x40, 0);
158 198

  
159 199
    /* XXX: use Mac Serial port */
160 200
    fd = serial_open_device();
......
164 204
        pci_ne2000_init(&nd_table[i]);
165 205
    }
166 206

  
167
    pci_ide_init(bs_table);
207
    ide0_mem_index = pmac_ide_init(&bs_table[0], openpic, 0x13);
208
    ide1_mem_index = pmac_ide_init(&bs_table[2], openpic, 0x13);
168 209

  
169 210
    /* cuda also initialize ADB */
170
    cuda_mem_index = cuda_init();
211
    cuda_mem_index = cuda_init(openpic, 0x19);
171 212

  
172 213
    adb_kbd_init(&adb_bus);
173 214
    adb_mouse_init(&adb_bus);
174 215
    
175 216
    macio_init();
176 217

  
177
    nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
218
    nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
219
    
220
    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
221
        graphic_depth = 15;
178 222

  
179
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
180
                         0, 0,
181
                         0,
182
                         0,
183
                         0, 0,
223
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "CHRP", ram_size, boot_device,
224
                         kernel_base, kernel_size,
225
                         kernel_cmdline,
226
                         initrd_base, initrd_size,
184 227
                         /* XXX: need an option to load a NVRAM image */
185
                         0
186
                         );
187

  
188
    /* Special port to get debug messages from Open-Firmware */
189
    register_ioport_write(0xFF00, 0x04, 1, &PREP_debug_write, NULL);
190
    register_ioport_write(0xFF00, 0x04, 2, &PREP_debug_write, NULL);
191
    
192
    pci_ppc_bios_init();
228
                         0,
229
                         graphic_width, graphic_height, graphic_depth);
230
    /* No PCI init: the BIOS will do it */
193 231
}
b/hw/ppc_prep.c
26 26
//#define HARD_DEBUG_PPC_IO
27 27
//#define DEBUG_PPC_IO
28 28

  
29
#define KERNEL_LOAD_ADDR 0x01000000;
30
#define INITRD_LOAD_ADDR 0x01800000;
29
#define BIOS_FILENAME "ppc_rom.bin"
30
#define KERNEL_LOAD_ADDR 0x01000000
31
#define INITRD_LOAD_ADDR 0x01800000
31 32

  
32 33
extern int loglevel;
33 34
extern FILE *logfile;
......
39 40
#if defined (HARD_DEBUG_PPC_IO)
40 41
#define PPC_IO_DPRINTF(fmt, args...)                     \
41 42
do {                                                     \
42
    if (loglevel > 0) {                                  \
43
    if (loglevel & CPU_LOG_IOPORT) {                     \
43 44
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
44 45
    } else {                                             \
45 46
        printf("%s : " fmt, __func__ , ##args);          \
......
48 49
#elif defined (DEBUG_PPC_IO)
49 50
#define PPC_IO_DPRINTF(fmt, args...)                     \
50 51
do {                                                     \
51
    if (loglevel > 0) {                                  \
52
    if (loglevel & CPU_LOG_IOPORT) {                     \
52 53
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
53 54
    }                                                    \
54 55
} while (0)
......
56 57
#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
57 58
#endif
58 59

  
59
#define BIOS_FILENAME "ppc_rom.bin"
60 60
/* Constants for devices init */
61 61
static const int ide_iobase[2] = { 0x1f0, 0x170 };
62 62
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
......
175 175
    uint32_t eemck1;
176 176
    /* Error diagnostic */
177 177
} XCSR;
178
#endif
179 178

  
180 179
static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
181 180
{
......
242 241
    &PPC_XCSR_readw,
243 242
    &PPC_XCSR_readl,
244 243
};
244
#endif
245 245

  
246 246
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
247 247
typedef struct sysctrl_t {
......
413 413
		   const char *initrd_filename)
414 414
{
415 415
    char buf[1024];
416
    //    void *openpic;
417 416
    m48t59_t *nvram;
418 417
    int PPC_io_memory;
419 418
    int ret, linux_boot, i, nb_nics1, fd;
......
506 505
                     bs_table[2 * i], bs_table[2 * i + 1]);
507 506
    }
508 507
    kbd_init();
509
    DMA_init();
508
    DMA_init(1);
510 509
    //    AUD_init();
511 510
    //    SB16_init();
512 511

  
......
528 527
                                           PPC_intack_write, NULL);
529 528
    cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
530 529
    /* PowerPC control and status register group */
530
#if 0
531 531
    PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
532 532
    cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
533
#endif
533 534

  
534
    nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
535
    nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE);
535 536
    if (nvram == NULL)
536 537
        return;
537 538
    sysctrl->nvram = nvram;
......
539 540
    /* Initialise NVRAM */
540 541
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
541 542
                         kernel_base, kernel_size,
542
                         (uint32_t)(long)kernel_cmdline,
543
                         strlen(kernel_cmdline),
543
                         kernel_cmdline,
544 544
                         initrd_base, initrd_size,
545 545
                         /* XXX: need an option to load a NVRAM image */
546
                         0
547
                         );
548

  
549
    /* Special port to get debug messages from Open-Firmware */
550
    register_ioport_write(0xFF00, 0x04, 1, &PREP_debug_write, NULL);
551
    register_ioport_write(0xFF00, 0x04, 2, &PREP_debug_write, NULL);
546
                         0,
547
                         graphic_width, graphic_height, graphic_depth);
552 548

  
553 549
    pci_ppc_bios_init();
554 550
}

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