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target-alpha: Merge HW_REI and HW_RET implementations.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-alpha: Rationalize internal processor registers.
Delete all the code that tried to emulate the real IPRs of someunnamed CPU. Replace those with just 3 slots that we can use tocommunicate trap information between the helper functions thatsignal exceptions and the OS trap handler....
target-alpha: Fix translation of PALmode memory insns.
All of the "raw" memory accesses should be "phys" instead. Fixsome confusion about argument ordering of the store routines.Fix the implementation of store-conditional.
Delete the "alt-mode" helpers. Because we only implement two...
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
target-alpha: use new float64_unordered_quiet() function
Use float64_unordered_quiet() in helper_cmptun() instead of doing thethe comparison manually.
According to the "Alpha Compiler Writer's Guide", we should use the_quiet version here, as CMPTUN and CMPTEQ should generate InvalidOp...
softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparisonfunctions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
Note that it is purely mechanical, and the behaviour should be unchanged....
softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()
The softfloat functions float*_is_nan() were badly misnamed,because they return true only for quiet NaNs, not for all NaNs.Rename them to float*_is_quiet_nan() to more accurately reflect...
target-alpha: Implement RPCC.
A minimal implementation that more or less corresponds to theuser-level version used by target-i386. More hoops will wantto be jumped through when alpha gets system-level emulation.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
target-alpha: Implement cpys{, n, e} inline.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-alpha: Implement rs/rc properly.
This is a per-cpu flag; there's no need for a spinlock of any kind.
We were also failing to manipulate the flag with $31 as a target regand failing to clear the flag on execution of a return-from-interruptinstruction....
target-alpha: Implement cvtlq inline.
It's a simple shift and mask sequence.
target-alpha: Fix load-locked/store-conditional.
Use an exception plus start_exclusive to implement the compare-and-swap.This follows the example set by the MIPS and PPC ports.
target-alpha: Implement cvtql inline.
It's a simple mask and shift sequence.Also, fix a typo in the actual masks used.
target-alpha: Implement IEEE FP qualifiers.
IEEE FP instructions are split up so that the rounding modecoming from the instruction and exceptions (both masking anddelivery) are handled external to the base FP operation.FP exceptions are properly raised for non-finite inputs to...
target-alpha: Clean up arithmetic traps.
Replace the EXCP_ARITH_OVERFLOW placeholder with the completeset of bits from the EXC_SUM IPR. Use them in the existingplaces where we raise arithmetic exceptions.
target-alpha: Mark helper_excp as NORETURN.
target-alpha: Fix cvtlq.
We were missing the 0xc0000000 mask, leading to incorrect results.
target-alpha: Fix float32_to_s vs zero exponent.
There was a bug in float32_to_s that incorrectly mapped a zero exponentto 0x38. This meant 0.0f != 0. At the same time, fix a generic typepunning bug in helper_memory_to_s and helper_s_to_memory.
target-alpha: Implement fp branch/cmov inline.
The old fcmov implementation had a typo:- tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);which moved the condition, not the second source, to the destination.
But it's also easy to implement the simplified fp comparison inline....
target-alpha: Expand ins*l inline.
Similar in difficulty to ext*l, already expanded.
target-alpha: Expand msk*l inline.
target-alpha: Expand msk*h inline.
target-alpha: Expand ins*h inline.
target-alpha: Implement missing MVI instructions.
target-alpha: Remove bogus DO_TB_FLUSH code from translator.
target-alpha: Fixes for alpha-linux syscalls.
1. Add correct definitions of error numbers.2. Implement SYS_osf_sigprocmask3. Implement SYS_osf_get/setsysinfo for IEEE_FP_CONTROL.
This last requires exposing the FPCR value to do_syscall.Since this value is actually split up into the float_status,...
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Add 'static' to please Sparse
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace always_inline with inline
We define inline as always_inline.
Update to a hopefully more future proof FSF address
target-alpha: remove amask helper
The direct use of helper_amask in translate.c was bogus (as env is notassigned). Directly code amask in tcg and remove the helper.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: remove helper_load_implver
There is no need to use an helper. Directly load the value with tcg code.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7074 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: overflow condition for sublv and subqv
The conditions to detect overflow in sub operations was wrong.
This patch is necessary to boot Tru64.
target-alpha: tb_flush helper should flush the tb (and not the tlb).
Looks to be a typo fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6926 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: use CPU_Float/CPU_Double instead of ugly casts
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5771 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix cmpbge instruction
The cmpbge instruction should compare all 8 bytes of one 64-bit value withanother. However, we were looping with a < 7 condition which was skippingthe top byte. So if we were doing a compare where the top byte was...
target-alpha: convert palcode ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert FP ops to TCG
- Convert FP ops to TCG- Fix S format- Implement F and G formats (untested)- Fix MF_FPCR an MT_FPCR- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT- Fix CPYSN, CPYSE
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert remaining arith3 functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: switch a few helpers to TCG
Switch a few helpers to TCG and implement RC and RS instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert byte manipulation instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert arith2 instructions to TCG
Replace gen_arith2 generic macro and dyngon ops by instruction specificoptimized TCG code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc host compile problem reported by Shaddy Baddah
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3750 c046a42c-6fe2-441c-8c8c-71466251a162
fixed invalid type
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
Adjust s390 addresses (the MSB is defined as "to be ignored").
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
Make Alpha and PowerPC targets use shared helpers for clz, clo, ctz, cto and ctpop.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3466 c046a42c-6fe2-441c-8c8c-71466251a162
Alpha coding style and inlining fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3462 c046a42c-6fe2-441c-8c8c-71466251a162
Use host-utils for Alpha 64x64 bits multiplications.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3443 c046a42c-6fe2-441c-8c8c-71466251a162
Generate micro-ops for Alpha executive and supervisor modes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3385 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Alpha architecture emulation core.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2597 c046a42c-6fe2-441c-8c8c-71466251a162