root / hw / sh_intc.c @ b79e1752
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1 | 80f515e6 | balrog | /*
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2 | 80f515e6 | balrog | * SuperH interrupt controller module
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3 | 80f515e6 | balrog | *
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4 | 80f515e6 | balrog | * Copyright (c) 2007 Magnus Damm
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5 | 80f515e6 | balrog | * Based on sh_timer.c and arm_timer.c by Paul Brook
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6 | 80f515e6 | balrog | * Copyright (c) 2005-2006 CodeSourcery.
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7 | 80f515e6 | balrog | *
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8 | 80f515e6 | balrog | * This code is licenced under the GPL.
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9 | 80f515e6 | balrog | */
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10 | 80f515e6 | balrog | |
11 | 80f515e6 | balrog | #include <assert.h> |
12 | 80f515e6 | balrog | #include "sh_intc.h" |
13 | 87ecb68b | pbrook | #include "hw.h" |
14 | 87ecb68b | pbrook | #include "sh.h" |
15 | 80f515e6 | balrog | |
16 | 80f515e6 | balrog | //#define DEBUG_INTC
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17 | e96e2044 | ths | //#define DEBUG_INTC_SOURCES
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18 | 80f515e6 | balrog | |
19 | 80f515e6 | balrog | #define INTC_A7(x) ((x) & 0x1fffffff) |
20 | 80f515e6 | balrog | #define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0])) |
21 | 80f515e6 | balrog | |
22 | e96e2044 | ths | void sh_intc_toggle_source(struct intc_source *source, |
23 | e96e2044 | ths | int enable_adj, int assert_adj) |
24 | e96e2044 | ths | { |
25 | e96e2044 | ths | int enable_changed = 0; |
26 | e96e2044 | ths | int pending_changed = 0; |
27 | e96e2044 | ths | int old_pending;
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28 | e96e2044 | ths | |
29 | e96e2044 | ths | if ((source->enable_count == source->enable_max) && (enable_adj == -1)) |
30 | e96e2044 | ths | enable_changed = -1;
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31 | e96e2044 | ths | |
32 | e96e2044 | ths | source->enable_count += enable_adj; |
33 | e96e2044 | ths | |
34 | e96e2044 | ths | if (source->enable_count == source->enable_max)
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35 | e96e2044 | ths | enable_changed = 1;
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36 | e96e2044 | ths | |
37 | e96e2044 | ths | source->asserted += assert_adj; |
38 | e96e2044 | ths | |
39 | e96e2044 | ths | old_pending = source->pending; |
40 | e96e2044 | ths | source->pending = source->asserted && |
41 | e96e2044 | ths | (source->enable_count == source->enable_max); |
42 | e96e2044 | ths | |
43 | e96e2044 | ths | if (old_pending != source->pending)
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44 | e96e2044 | ths | pending_changed = 1;
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45 | e96e2044 | ths | |
46 | e96e2044 | ths | if (pending_changed) {
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47 | e96e2044 | ths | if (source->pending) {
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48 | e96e2044 | ths | source->parent->pending++; |
49 | e96e2044 | ths | if (source->parent->pending == 1) |
50 | e96e2044 | ths | cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
51 | e96e2044 | ths | } |
52 | e96e2044 | ths | else {
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53 | e96e2044 | ths | source->parent->pending--; |
54 | e96e2044 | ths | if (source->parent->pending == 0) |
55 | e96e2044 | ths | cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
56 | e96e2044 | ths | } |
57 | e96e2044 | ths | } |
58 | e96e2044 | ths | |
59 | e96e2044 | ths | if (enable_changed || assert_adj || pending_changed) {
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60 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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61 | e96e2044 | ths | printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
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62 | e96e2044 | ths | source->parent->pending, |
63 | e96e2044 | ths | source->asserted, |
64 | e96e2044 | ths | source->enable_count, |
65 | e96e2044 | ths | source->enable_max, |
66 | e96e2044 | ths | source->vect, |
67 | e96e2044 | ths | source->asserted ? "asserted " :
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68 | e96e2044 | ths | assert_adj ? "deasserted" : "", |
69 | e96e2044 | ths | enable_changed == 1 ? "enabled " : |
70 | e96e2044 | ths | enable_changed == -1 ? "disabled " : "", |
71 | e96e2044 | ths | source->pending ? "pending" : ""); |
72 | e96e2044 | ths | #endif
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73 | e96e2044 | ths | } |
74 | e96e2044 | ths | } |
75 | e96e2044 | ths | |
76 | b79e1752 | aurel32 | static void sh_intc_set_irq (void *opaque, int n, int level) |
77 | 96e2fc41 | aurel32 | { |
78 | 96e2fc41 | aurel32 | struct intc_desc *desc = opaque;
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79 | 96e2fc41 | aurel32 | struct intc_source *source = &(desc->sources[n]);
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80 | 96e2fc41 | aurel32 | |
81 | 4e7ed2d1 | aurel32 | if (level && !source->asserted)
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82 | 4e7ed2d1 | aurel32 | sh_intc_toggle_source(source, 0, 1); |
83 | 4e7ed2d1 | aurel32 | else if (!level && source->asserted) |
84 | 4e7ed2d1 | aurel32 | sh_intc_toggle_source(source, 0, -1); |
85 | 96e2fc41 | aurel32 | } |
86 | 96e2fc41 | aurel32 | |
87 | e96e2044 | ths | int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) |
88 | e96e2044 | ths | { |
89 | e96e2044 | ths | unsigned int i; |
90 | e96e2044 | ths | |
91 | e96e2044 | ths | /* slow: use a linked lists of pending sources instead */
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92 | e96e2044 | ths | /* wrong: take interrupt priority into account (one list per priority) */
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93 | e96e2044 | ths | |
94 | e96e2044 | ths | if (imask == 0x0f) { |
95 | e96e2044 | ths | return -1; /* FIXME, update code to include priority per source */ |
96 | e96e2044 | ths | } |
97 | e96e2044 | ths | |
98 | e96e2044 | ths | for (i = 0; i < desc->nr_sources; i++) { |
99 | e96e2044 | ths | struct intc_source *source = desc->sources + i;
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100 | e96e2044 | ths | |
101 | e96e2044 | ths | if (source->pending) {
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102 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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103 | e96e2044 | ths | printf("sh_intc: (%d) returning interrupt source 0x%x\n",
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104 | e96e2044 | ths | desc->pending, source->vect); |
105 | e96e2044 | ths | #endif
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106 | e96e2044 | ths | return source->vect;
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107 | e96e2044 | ths | } |
108 | e96e2044 | ths | } |
109 | e96e2044 | ths | |
110 | e96e2044 | ths | assert(0);
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111 | e96e2044 | ths | } |
112 | e96e2044 | ths | |
113 | 80f515e6 | balrog | #define INTC_MODE_NONE 0 |
114 | 80f515e6 | balrog | #define INTC_MODE_DUAL_SET 1 |
115 | 80f515e6 | balrog | #define INTC_MODE_DUAL_CLR 2 |
116 | 80f515e6 | balrog | #define INTC_MODE_ENABLE_REG 3 |
117 | 80f515e6 | balrog | #define INTC_MODE_MASK_REG 4 |
118 | 80f515e6 | balrog | #define INTC_MODE_IS_PRIO 8 |
119 | 80f515e6 | balrog | |
120 | 80f515e6 | balrog | static unsigned int sh_intc_mode(unsigned long address, |
121 | 80f515e6 | balrog | unsigned long set_reg, unsigned long clr_reg) |
122 | 80f515e6 | balrog | { |
123 | 80f515e6 | balrog | if ((address != INTC_A7(set_reg)) &&
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124 | 80f515e6 | balrog | (address != INTC_A7(clr_reg))) |
125 | 80f515e6 | balrog | return INTC_MODE_NONE;
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126 | 80f515e6 | balrog | |
127 | 80f515e6 | balrog | if (set_reg && clr_reg) {
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128 | 80f515e6 | balrog | if (address == INTC_A7(set_reg))
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129 | 80f515e6 | balrog | return INTC_MODE_DUAL_SET;
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130 | 80f515e6 | balrog | else
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131 | 80f515e6 | balrog | return INTC_MODE_DUAL_CLR;
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132 | 80f515e6 | balrog | } |
133 | 80f515e6 | balrog | |
134 | 80f515e6 | balrog | if (set_reg)
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135 | 80f515e6 | balrog | return INTC_MODE_ENABLE_REG;
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136 | 80f515e6 | balrog | else
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137 | 80f515e6 | balrog | return INTC_MODE_MASK_REG;
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138 | 80f515e6 | balrog | } |
139 | 80f515e6 | balrog | |
140 | 80f515e6 | balrog | static void sh_intc_locate(struct intc_desc *desc, |
141 | 80f515e6 | balrog | unsigned long address, |
142 | 80f515e6 | balrog | unsigned long **datap, |
143 | 80f515e6 | balrog | intc_enum **enums, |
144 | 80f515e6 | balrog | unsigned int *first, |
145 | 80f515e6 | balrog | unsigned int *width, |
146 | 80f515e6 | balrog | unsigned int *modep) |
147 | 80f515e6 | balrog | { |
148 | 80f515e6 | balrog | unsigned int i, mode; |
149 | 80f515e6 | balrog | |
150 | 80f515e6 | balrog | /* this is slow but works for now */
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151 | 80f515e6 | balrog | |
152 | 80f515e6 | balrog | if (desc->mask_regs) {
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153 | 80f515e6 | balrog | for (i = 0; i < desc->nr_mask_regs; i++) { |
154 | 80f515e6 | balrog | struct intc_mask_reg *mr = desc->mask_regs + i;
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155 | 80f515e6 | balrog | |
156 | 80f515e6 | balrog | mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg); |
157 | 80f515e6 | balrog | if (mode == INTC_MODE_NONE)
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158 | 80f515e6 | balrog | continue;
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159 | 80f515e6 | balrog | |
160 | 80f515e6 | balrog | *modep = mode; |
161 | 80f515e6 | balrog | *datap = &mr->value; |
162 | 80f515e6 | balrog | *enums = mr->enum_ids; |
163 | 80f515e6 | balrog | *first = mr->reg_width - 1;
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164 | 80f515e6 | balrog | *width = 1;
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165 | 80f515e6 | balrog | return;
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166 | 80f515e6 | balrog | } |
167 | 80f515e6 | balrog | } |
168 | 80f515e6 | balrog | |
169 | 80f515e6 | balrog | if (desc->prio_regs) {
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170 | 80f515e6 | balrog | for (i = 0; i < desc->nr_prio_regs; i++) { |
171 | 80f515e6 | balrog | struct intc_prio_reg *pr = desc->prio_regs + i;
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172 | 80f515e6 | balrog | |
173 | 80f515e6 | balrog | mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg); |
174 | 80f515e6 | balrog | if (mode == INTC_MODE_NONE)
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175 | 80f515e6 | balrog | continue;
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176 | 80f515e6 | balrog | |
177 | 80f515e6 | balrog | *modep = mode | INTC_MODE_IS_PRIO; |
178 | 80f515e6 | balrog | *datap = &pr->value; |
179 | 80f515e6 | balrog | *enums = pr->enum_ids; |
180 | 80f515e6 | balrog | *first = (pr->reg_width / pr->field_width) - 1;
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181 | 80f515e6 | balrog | *width = pr->field_width; |
182 | 80f515e6 | balrog | return;
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183 | 80f515e6 | balrog | } |
184 | 80f515e6 | balrog | } |
185 | 80f515e6 | balrog | |
186 | 80f515e6 | balrog | assert(0);
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187 | 80f515e6 | balrog | } |
188 | 80f515e6 | balrog | |
189 | e96e2044 | ths | static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, |
190 | e96e2044 | ths | int enable, int is_group) |
191 | 80f515e6 | balrog | { |
192 | 80f515e6 | balrog | struct intc_source *source = desc->sources + id;
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193 | 80f515e6 | balrog | |
194 | 80f515e6 | balrog | if (!id)
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195 | 80f515e6 | balrog | return;
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196 | 80f515e6 | balrog | |
197 | 80f515e6 | balrog | if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
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198 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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199 | 80f515e6 | balrog | printf("sh_intc: reserved interrupt source %d modified\n", id);
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200 | 80f515e6 | balrog | #endif
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201 | 80f515e6 | balrog | return;
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202 | 80f515e6 | balrog | } |
203 | 80f515e6 | balrog | |
204 | e96e2044 | ths | if (source->vect)
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205 | e96e2044 | ths | sh_intc_toggle_source(source, enable ? 1 : -1, 0); |
206 | 80f515e6 | balrog | |
207 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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208 | 80f515e6 | balrog | else {
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209 | 80f515e6 | balrog | printf("setting interrupt group %d to %d\n", id, !!enable);
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210 | 80f515e6 | balrog | } |
211 | 80f515e6 | balrog | #endif
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212 | 80f515e6 | balrog | |
213 | 80f515e6 | balrog | if ((is_group || !source->vect) && source->next_enum_id) {
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214 | e96e2044 | ths | sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
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215 | 80f515e6 | balrog | } |
216 | 80f515e6 | balrog | |
217 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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218 | 80f515e6 | balrog | if (!source->vect) {
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219 | 80f515e6 | balrog | printf("setting interrupt group %d to %d - done\n", id, !!enable);
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220 | 80f515e6 | balrog | } |
221 | 80f515e6 | balrog | #endif
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222 | 80f515e6 | balrog | } |
223 | 80f515e6 | balrog | |
224 | 80f515e6 | balrog | static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset) |
225 | 80f515e6 | balrog | { |
226 | 80f515e6 | balrog | struct intc_desc *desc = opaque;
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227 | 80f515e6 | balrog | intc_enum *enum_ids = NULL;
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228 | 80f515e6 | balrog | unsigned int first = 0; |
229 | 80f515e6 | balrog | unsigned int width = 0; |
230 | 80f515e6 | balrog | unsigned int mode = 0; |
231 | 80f515e6 | balrog | unsigned long *valuep; |
232 | 80f515e6 | balrog | |
233 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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234 | 80f515e6 | balrog | printf("sh_intc_read 0x%lx\n", (unsigned long) offset); |
235 | 80f515e6 | balrog | #endif
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236 | 80f515e6 | balrog | |
237 | 80f515e6 | balrog | sh_intc_locate(desc, (unsigned long)offset, &valuep, |
238 | 80f515e6 | balrog | &enum_ids, &first, &width, &mode); |
239 | 80f515e6 | balrog | return *valuep;
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240 | 80f515e6 | balrog | } |
241 | 80f515e6 | balrog | |
242 | 80f515e6 | balrog | static void sh_intc_write(void *opaque, target_phys_addr_t offset, |
243 | 80f515e6 | balrog | uint32_t value) |
244 | 80f515e6 | balrog | { |
245 | 80f515e6 | balrog | struct intc_desc *desc = opaque;
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246 | 80f515e6 | balrog | intc_enum *enum_ids = NULL;
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247 | 80f515e6 | balrog | unsigned int first = 0; |
248 | 80f515e6 | balrog | unsigned int width = 0; |
249 | 80f515e6 | balrog | unsigned int mode = 0; |
250 | 80f515e6 | balrog | unsigned int k; |
251 | 80f515e6 | balrog | unsigned long *valuep; |
252 | 80f515e6 | balrog | unsigned long mask; |
253 | 80f515e6 | balrog | |
254 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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255 | 80f515e6 | balrog | printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value); |
256 | 80f515e6 | balrog | #endif
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257 | 80f515e6 | balrog | |
258 | 80f515e6 | balrog | sh_intc_locate(desc, (unsigned long)offset, &valuep, |
259 | 80f515e6 | balrog | &enum_ids, &first, &width, &mode); |
260 | 80f515e6 | balrog | |
261 | 80f515e6 | balrog | switch (mode) {
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262 | 80f515e6 | balrog | case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; |
263 | 80f515e6 | balrog | case INTC_MODE_DUAL_SET: value |= *valuep; break; |
264 | 80f515e6 | balrog | case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break; |
265 | 80f515e6 | balrog | default: assert(0); |
266 | 80f515e6 | balrog | } |
267 | 80f515e6 | balrog | |
268 | 80f515e6 | balrog | for (k = 0; k <= first; k++) { |
269 | 80f515e6 | balrog | mask = ((1 << width) - 1) << ((first - k) * width); |
270 | 80f515e6 | balrog | |
271 | 80f515e6 | balrog | if ((*valuep & mask) == (value & mask))
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272 | 80f515e6 | balrog | continue;
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273 | 80f515e6 | balrog | #if 0
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274 | 80f515e6 | balrog | printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
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275 | 80f515e6 | balrog | k, first, enum_ids[k], (unsigned int)mask);
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276 | 80f515e6 | balrog | #endif
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277 | e96e2044 | ths | sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
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278 | 80f515e6 | balrog | } |
279 | 80f515e6 | balrog | |
280 | 80f515e6 | balrog | *valuep = value; |
281 | 80f515e6 | balrog | |
282 | 80f515e6 | balrog | #ifdef DEBUG_INTC
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283 | 80f515e6 | balrog | printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value); |
284 | 80f515e6 | balrog | #endif
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285 | 80f515e6 | balrog | } |
286 | 80f515e6 | balrog | |
287 | 80f515e6 | balrog | static CPUReadMemoryFunc *sh_intc_readfn[] = {
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288 | 80f515e6 | balrog | sh_intc_read, |
289 | 80f515e6 | balrog | sh_intc_read, |
290 | 80f515e6 | balrog | sh_intc_read |
291 | 80f515e6 | balrog | }; |
292 | 80f515e6 | balrog | |
293 | 80f515e6 | balrog | static CPUWriteMemoryFunc *sh_intc_writefn[] = {
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294 | 80f515e6 | balrog | sh_intc_write, |
295 | 80f515e6 | balrog | sh_intc_write, |
296 | 80f515e6 | balrog | sh_intc_write |
297 | 80f515e6 | balrog | }; |
298 | 80f515e6 | balrog | |
299 | 80f515e6 | balrog | struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id) |
300 | 80f515e6 | balrog | { |
301 | 80f515e6 | balrog | if (id)
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302 | 80f515e6 | balrog | return desc->sources + id;
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303 | 80f515e6 | balrog | |
304 | 80f515e6 | balrog | return NULL; |
305 | 80f515e6 | balrog | } |
306 | 80f515e6 | balrog | |
307 | 80f515e6 | balrog | static void sh_intc_register(struct intc_desc *desc, |
308 | 80f515e6 | balrog | unsigned long address) |
309 | 80f515e6 | balrog | { |
310 | 5c16736a | balrog | if (address) {
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311 | 5c16736a | balrog | cpu_register_physical_memory_offset(P4ADDR(address), 4,
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312 | 8da3ff18 | pbrook | desc->iomemtype, INTC_A7(address)); |
313 | 5c16736a | balrog | cpu_register_physical_memory_offset(A7ADDR(address), 4,
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314 | 5c16736a | balrog | desc->iomemtype, INTC_A7(address)); |
315 | 5c16736a | balrog | } |
316 | 80f515e6 | balrog | } |
317 | 80f515e6 | balrog | |
318 | 80f515e6 | balrog | static void sh_intc_register_source(struct intc_desc *desc, |
319 | 80f515e6 | balrog | intc_enum source, |
320 | 80f515e6 | balrog | struct intc_group *groups,
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321 | 80f515e6 | balrog | int nr_groups)
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322 | 80f515e6 | balrog | { |
323 | 80f515e6 | balrog | unsigned int i, k; |
324 | 80f515e6 | balrog | struct intc_source *s;
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325 | 80f515e6 | balrog | |
326 | 80f515e6 | balrog | if (desc->mask_regs) {
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327 | 80f515e6 | balrog | for (i = 0; i < desc->nr_mask_regs; i++) { |
328 | 80f515e6 | balrog | struct intc_mask_reg *mr = desc->mask_regs + i;
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329 | 80f515e6 | balrog | |
330 | 80f515e6 | balrog | for (k = 0; k < INTC_ARRAY(mr->enum_ids); k++) { |
331 | 80f515e6 | balrog | if (mr->enum_ids[k] != source)
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332 | 80f515e6 | balrog | continue;
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333 | 80f515e6 | balrog | |
334 | 80f515e6 | balrog | s = sh_intc_source(desc, mr->enum_ids[k]); |
335 | 80f515e6 | balrog | if (s)
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336 | 80f515e6 | balrog | s->enable_max++; |
337 | 80f515e6 | balrog | } |
338 | 80f515e6 | balrog | } |
339 | 80f515e6 | balrog | } |
340 | 80f515e6 | balrog | |
341 | 80f515e6 | balrog | if (desc->prio_regs) {
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342 | 80f515e6 | balrog | for (i = 0; i < desc->nr_prio_regs; i++) { |
343 | 80f515e6 | balrog | struct intc_prio_reg *pr = desc->prio_regs + i;
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344 | 80f515e6 | balrog | |
345 | 80f515e6 | balrog | for (k = 0; k < INTC_ARRAY(pr->enum_ids); k++) { |
346 | 80f515e6 | balrog | if (pr->enum_ids[k] != source)
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347 | 80f515e6 | balrog | continue;
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348 | 80f515e6 | balrog | |
349 | 80f515e6 | balrog | s = sh_intc_source(desc, pr->enum_ids[k]); |
350 | 80f515e6 | balrog | if (s)
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351 | 80f515e6 | balrog | s->enable_max++; |
352 | 80f515e6 | balrog | } |
353 | 80f515e6 | balrog | } |
354 | 80f515e6 | balrog | } |
355 | 80f515e6 | balrog | |
356 | 80f515e6 | balrog | if (groups) {
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357 | 80f515e6 | balrog | for (i = 0; i < nr_groups; i++) { |
358 | 80f515e6 | balrog | struct intc_group *gr = groups + i;
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359 | 80f515e6 | balrog | |
360 | 80f515e6 | balrog | for (k = 0; k < INTC_ARRAY(gr->enum_ids); k++) { |
361 | 80f515e6 | balrog | if (gr->enum_ids[k] != source)
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362 | 80f515e6 | balrog | continue;
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363 | 80f515e6 | balrog | |
364 | 80f515e6 | balrog | s = sh_intc_source(desc, gr->enum_ids[k]); |
365 | 80f515e6 | balrog | if (s)
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366 | 80f515e6 | balrog | s->enable_max++; |
367 | 80f515e6 | balrog | } |
368 | 80f515e6 | balrog | } |
369 | 80f515e6 | balrog | } |
370 | 80f515e6 | balrog | |
371 | 80f515e6 | balrog | } |
372 | 80f515e6 | balrog | |
373 | 80f515e6 | balrog | void sh_intc_register_sources(struct intc_desc *desc, |
374 | 80f515e6 | balrog | struct intc_vect *vectors,
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375 | 80f515e6 | balrog | int nr_vectors,
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376 | 80f515e6 | balrog | struct intc_group *groups,
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377 | 80f515e6 | balrog | int nr_groups)
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378 | 80f515e6 | balrog | { |
379 | 80f515e6 | balrog | unsigned int i, k; |
380 | 80f515e6 | balrog | struct intc_source *s;
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381 | 80f515e6 | balrog | |
382 | 80f515e6 | balrog | for (i = 0; i < nr_vectors; i++) { |
383 | 80f515e6 | balrog | struct intc_vect *vect = vectors + i;
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384 | 80f515e6 | balrog | |
385 | 80f515e6 | balrog | sh_intc_register_source(desc, vect->enum_id, groups, nr_groups); |
386 | 80f515e6 | balrog | s = sh_intc_source(desc, vect->enum_id); |
387 | 80f515e6 | balrog | if (s)
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388 | 80f515e6 | balrog | s->vect = vect->vect; |
389 | 80f515e6 | balrog | |
390 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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391 | 80f515e6 | balrog | printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
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392 | 80f515e6 | balrog | vect->enum_id, s->vect, s->enable_count, s->enable_max); |
393 | 80f515e6 | balrog | #endif
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394 | 80f515e6 | balrog | } |
395 | 80f515e6 | balrog | |
396 | 80f515e6 | balrog | if (groups) {
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397 | 80f515e6 | balrog | for (i = 0; i < nr_groups; i++) { |
398 | 80f515e6 | balrog | struct intc_group *gr = groups + i;
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399 | 80f515e6 | balrog | |
400 | 80f515e6 | balrog | s = sh_intc_source(desc, gr->enum_id); |
401 | 80f515e6 | balrog | s->next_enum_id = gr->enum_ids[0];
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402 | 80f515e6 | balrog | |
403 | 80f515e6 | balrog | for (k = 1; k < INTC_ARRAY(gr->enum_ids); k++) { |
404 | 80f515e6 | balrog | if (!gr->enum_ids[k])
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405 | 80f515e6 | balrog | continue;
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406 | 80f515e6 | balrog | |
407 | 80f515e6 | balrog | s = sh_intc_source(desc, gr->enum_ids[k - 1]);
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408 | 80f515e6 | balrog | s->next_enum_id = gr->enum_ids[k]; |
409 | 80f515e6 | balrog | } |
410 | 80f515e6 | balrog | |
411 | e96e2044 | ths | #ifdef DEBUG_INTC_SOURCES
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412 | 80f515e6 | balrog | printf("sh_intc: registered group %d (%d/%d)\n",
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413 | 80f515e6 | balrog | gr->enum_id, s->enable_count, s->enable_max); |
414 | 80f515e6 | balrog | #endif
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415 | 80f515e6 | balrog | } |
416 | 80f515e6 | balrog | } |
417 | 80f515e6 | balrog | } |
418 | 80f515e6 | balrog | |
419 | 80f515e6 | balrog | int sh_intc_init(struct intc_desc *desc, |
420 | 80f515e6 | balrog | int nr_sources,
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421 | 80f515e6 | balrog | struct intc_mask_reg *mask_regs,
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422 | 80f515e6 | balrog | int nr_mask_regs,
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423 | 80f515e6 | balrog | struct intc_prio_reg *prio_regs,
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424 | 80f515e6 | balrog | int nr_prio_regs)
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425 | 80f515e6 | balrog | { |
426 | 80f515e6 | balrog | unsigned int i; |
427 | 80f515e6 | balrog | |
428 | e96e2044 | ths | desc->pending = 0;
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429 | 80f515e6 | balrog | desc->nr_sources = nr_sources; |
430 | 80f515e6 | balrog | desc->mask_regs = mask_regs; |
431 | 80f515e6 | balrog | desc->nr_mask_regs = nr_mask_regs; |
432 | 80f515e6 | balrog | desc->prio_regs = prio_regs; |
433 | 80f515e6 | balrog | desc->nr_prio_regs = nr_prio_regs; |
434 | 80f515e6 | balrog | |
435 | 80f515e6 | balrog | i = sizeof(struct intc_source) * nr_sources; |
436 | 80f515e6 | balrog | desc->sources = malloc(i); |
437 | 80f515e6 | balrog | if (!desc->sources)
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438 | 80f515e6 | balrog | return -1; |
439 | 80f515e6 | balrog | |
440 | 80f515e6 | balrog | memset(desc->sources, 0, i);
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441 | e96e2044 | ths | for (i = 0; i < desc->nr_sources; i++) { |
442 | e96e2044 | ths | struct intc_source *source = desc->sources + i;
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443 | e96e2044 | ths | |
444 | e96e2044 | ths | source->parent = desc; |
445 | e96e2044 | ths | } |
446 | 96e2fc41 | aurel32 | |
447 | 96e2fc41 | aurel32 | desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources); |
448 | 80f515e6 | balrog | |
449 | 80f515e6 | balrog | desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
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450 | 80f515e6 | balrog | sh_intc_writefn, desc); |
451 | 80f515e6 | balrog | if (desc->mask_regs) {
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452 | 80f515e6 | balrog | for (i = 0; i < desc->nr_mask_regs; i++) { |
453 | 80f515e6 | balrog | struct intc_mask_reg *mr = desc->mask_regs + i;
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454 | 80f515e6 | balrog | |
455 | 80f515e6 | balrog | sh_intc_register(desc, mr->set_reg); |
456 | 80f515e6 | balrog | sh_intc_register(desc, mr->clr_reg); |
457 | 80f515e6 | balrog | } |
458 | 80f515e6 | balrog | } |
459 | 80f515e6 | balrog | |
460 | 80f515e6 | balrog | if (desc->prio_regs) {
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461 | 80f515e6 | balrog | for (i = 0; i < desc->nr_prio_regs; i++) { |
462 | 80f515e6 | balrog | struct intc_prio_reg *pr = desc->prio_regs + i;
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463 | 80f515e6 | balrog | |
464 | 80f515e6 | balrog | sh_intc_register(desc, pr->set_reg); |
465 | 80f515e6 | balrog | sh_intc_register(desc, pr->clr_reg); |
466 | 80f515e6 | balrog | } |
467 | 80f515e6 | balrog | } |
468 | 80f515e6 | balrog | |
469 | 80f515e6 | balrog | return 0; |
470 | 80f515e6 | balrog | } |
471 | c6d86a33 | balrog | |
472 | c6d86a33 | balrog | /* Assert level <n> IRL interrupt.
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473 | c6d86a33 | balrog | 0:deassert. 1:lowest priority,... 15:highest priority. */
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474 | c6d86a33 | balrog | void sh_intc_set_irl(void *opaque, int n, int level) |
475 | c6d86a33 | balrog | { |
476 | c6d86a33 | balrog | struct intc_source *s = opaque;
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477 | c6d86a33 | balrog | int i, irl = level ^ 15; |
478 | c6d86a33 | balrog | for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { |
479 | c6d86a33 | balrog | if (i == irl)
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480 | c6d86a33 | balrog | sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1); |
481 | c6d86a33 | balrog | else
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482 | c6d86a33 | balrog | if (s->asserted)
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483 | c6d86a33 | balrog | sh_intc_toggle_source(s, 0, -1); |
484 | c6d86a33 | balrog | } |
485 | c6d86a33 | balrog | } |