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/*
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 * ARM virtual CPU header
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_ARM_H
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#define CPU_ARM_H
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#define TARGET_LONG_BITS 32
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#include "cpu-defs.h"
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#define EXCP_UDEF            1   /* undefined instruction */
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#define EXCP_SWI             2   /* software interrupt */
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#define EXCP_PREFETCH_ABORT  3
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#define EXCP_DATA_ABORT      4
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/* We currently assume float and double are IEEE single and double
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   precision respectively.
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   Doing runtime conversions is tricky because VFP registers may contain
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   integer values (eg. as the result of a FTOSI instruction).
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   A double precision register load/store must also load/store the
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   corresponding single precision pair, although it is undefined how
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   these overlap.  */
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typedef struct CPUARMState {
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    uint32_t regs[16];
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    uint32_t cpsr;
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    /* cpsr flag cache for faster execution */
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    uint32_t CF; /* 0 or 1 */
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    uint32_t VF; /* V is the bit 31. All other bits are undefined */
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    uint32_t NZF; /* N is bit 31. Z is computed from NZF */
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    uint32_t QF; /* 0 or 1 */
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    int thumb; /* 0 = arm mode, 1 = thumb mode */
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    /* coprocessor 15 (MMU) status */
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    uint32_t cp15_6;
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    /* exception/interrupt handling */
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    jmp_buf jmp_env;
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    int exception_index;
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    int interrupt_request;
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    struct TranslationBlock *current_tb;
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    int user_mode_only;
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    uint32_t address;
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* VFP coprocessor state.  */
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    struct {
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        union {
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            float s[32];
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            double d[16];
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        } regs;
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        /* We store these fpcsr fields separately for convenience.  */
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        int vec_len;
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        int vec_stride;
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        uint32_t fpscr;
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        /* Temporary variables if we don't have spare fp regs.  */
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        float tmp0s, tmp1s;
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        double tmp0d, tmp1d;
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    } vfp;
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    /* user data */
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    void *opaque;
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} CPUARMState;
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CPUARMState *cpu_arm_init(void);
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int cpu_arm_exec(CPUARMState *s);
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void cpu_arm_close(CPUARMState *s);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
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   is returned if the signal was handled by the virtual CPU.  */
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struct siginfo;
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int cpu_arm_signal_handler(int host_signum, struct siginfo *info, 
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                           void *puc);
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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#endif