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/*
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* ARM micro operations
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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#define REGNAME r0
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#define REG (env->regs[0]) |
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#include "op_template.h" |
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#define REGNAME r1
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#define REG (env->regs[1]) |
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#include "op_template.h" |
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#define REGNAME r2
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#define REG (env->regs[2]) |
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#include "op_template.h" |
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#define REGNAME r3
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#define REG (env->regs[3]) |
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#include "op_template.h" |
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#define REGNAME r4
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#define REG (env->regs[4]) |
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#include "op_template.h" |
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#define REGNAME r5
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#define REG (env->regs[5]) |
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#include "op_template.h" |
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#define REGNAME r6
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#define REG (env->regs[6]) |
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#include "op_template.h" |
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#define REGNAME r7
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#define REG (env->regs[7]) |
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#include "op_template.h" |
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#define REGNAME r8
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#define REG (env->regs[8]) |
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#include "op_template.h" |
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#define REGNAME r9
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#define REG (env->regs[9]) |
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#include "op_template.h" |
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#define REGNAME r10
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#define REG (env->regs[10]) |
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#include "op_template.h" |
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#define REGNAME r11
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#define REG (env->regs[11]) |
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#include "op_template.h" |
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#define REGNAME r12
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#define REG (env->regs[12]) |
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#include "op_template.h" |
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#define REGNAME r13
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#define REG (env->regs[13]) |
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#include "op_template.h" |
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#define REGNAME r14
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#define REG (env->regs[14]) |
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#include "op_template.h" |
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#define REGNAME r15
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#define REG (env->regs[15]) |
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#define SET_REG(x) REG = x & ~(uint32_t)1 |
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#include "op_template.h" |
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void OPPROTO op_bx_T0(void) |
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{ |
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env->regs[15] = T0 & ~(uint32_t)1; |
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env->thumb = (T0 & 1) != 0; |
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} |
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void OPPROTO op_movl_T0_0(void) |
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{ |
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T0 = 0;
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} |
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void OPPROTO op_movl_T0_im(void) |
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{ |
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T0 = PARAM1; |
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} |
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void OPPROTO op_movl_T1_im(void) |
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{ |
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T1 = PARAM1; |
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} |
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void OPPROTO op_mov_CF_T1(void) |
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{ |
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env->CF = ((uint32_t)T1) >> 31;
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} |
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void OPPROTO op_movl_T2_im(void) |
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{ |
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T2 = PARAM1; |
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} |
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void OPPROTO op_addl_T1_im(void) |
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{ |
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T1 += PARAM1; |
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} |
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void OPPROTO op_addl_T1_T2(void) |
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{ |
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T1 += T2; |
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} |
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void OPPROTO op_subl_T1_T2(void) |
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{ |
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T1 -= T2; |
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} |
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void OPPROTO op_addl_T0_T1(void) |
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{ |
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T0 += T1; |
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} |
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void OPPROTO op_addl_T0_T1_cc(void) |
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{ |
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unsigned int src1; |
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src1 = T0; |
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T0 += T1; |
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env->NZF = T0; |
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env->CF = T0 < src1; |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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} |
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void OPPROTO op_adcl_T0_T1(void) |
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{ |
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T0 += T1 + env->CF; |
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} |
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void OPPROTO op_adcl_T0_T1_cc(void) |
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{ |
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unsigned int src1; |
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src1 = T0; |
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if (!env->CF) {
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T0 += T1; |
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env->CF = T0 < src1; |
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} else {
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T0 += T1 + 1;
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env->CF = T0 <= src1; |
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} |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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env->NZF = T0; |
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FORCE_RET(); |
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} |
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#define OPSUB(sub, sbc, res, T0, T1) \
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1(void) \ |
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{ \ |
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res = T0 - T1; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \ |
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{ \ |
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unsigned int src1; \ |
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src1 = T0; \ |
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T0 -= T1; \ |
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env->NZF = T0; \ |
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env->CF = src1 >= T1; \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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res = T0; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1(void) \ |
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{ \ |
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res = T0 - T1 + env->CF - 1; \
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \ |
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{ \ |
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unsigned int src1; \ |
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src1 = T0; \ |
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if (!env->CF) { \
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T0 = T0 - T1 - 1; \
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env->CF = src1 > T1; \ |
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} else { \
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T0 = T0 - T1; \ |
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env->CF = src1 >= T1; \ |
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} \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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env->NZF = T0; \ |
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res = T0; \ |
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FORCE_RET(); \ |
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} |
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OPSUB(sub, sbc, T0, T0, T1) |
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OPSUB(rsb, rsc, T0, T1, T0) |
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void OPPROTO op_andl_T0_T1(void) |
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{ |
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T0 &= T1; |
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} |
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void OPPROTO op_xorl_T0_T1(void) |
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{ |
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T0 ^= T1; |
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} |
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void OPPROTO op_orl_T0_T1(void) |
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{ |
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T0 |= T1; |
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} |
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void OPPROTO op_bicl_T0_T1(void) |
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{ |
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T0 &= ~T1; |
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} |
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void OPPROTO op_notl_T1(void) |
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{ |
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T1 = ~T1; |
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} |
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void OPPROTO op_logic_T0_cc(void) |
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{ |
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env->NZF = T0; |
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} |
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void OPPROTO op_logic_T1_cc(void) |
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{ |
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env->NZF = T1; |
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} |
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#define EIP (env->regs[15]) |
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void OPPROTO op_test_eq(void) |
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{ |
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if (env->NZF == 0) |
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JUMP_TB(op_test_eq, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ne(void) |
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{ |
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if (env->NZF != 0) |
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JUMP_TB(op_test_ne, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_cs(void) |
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{ |
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if (env->CF != 0) |
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JUMP_TB(op_test_cs, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_cc(void) |
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{ |
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if (env->CF == 0) |
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JUMP_TB(op_test_cc, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_mi(void) |
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{ |
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if ((env->NZF & 0x80000000) != 0) |
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JUMP_TB(op_test_mi, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_pl(void) |
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{ |
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if ((env->NZF & 0x80000000) == 0) |
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JUMP_TB(op_test_pl, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_vs(void) |
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{ |
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if ((env->VF & 0x80000000) != 0) |
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JUMP_TB(op_test_vs, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_vc(void) |
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{ |
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if ((env->VF & 0x80000000) == 0) |
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JUMP_TB(op_test_vc, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_hi(void) |
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{ |
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if (env->CF != 0 && env->NZF != 0) |
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JUMP_TB(op_test_hi, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ls(void) |
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{ |
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if (env->CF == 0 || env->NZF == 0) |
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JUMP_TB(op_test_ls, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ge(void) |
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{ |
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if (((env->VF ^ env->NZF) & 0x80000000) == 0) |
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JUMP_TB(op_test_ge, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_lt(void) |
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{ |
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if (((env->VF ^ env->NZF) & 0x80000000) != 0) |
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JUMP_TB(op_test_lt, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_gt(void) |
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{ |
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if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0) |
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JUMP_TB(op_test_gt, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_le(void) |
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{ |
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if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0) |
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JUMP_TB(op_test_le, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_jmp(void) |
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{ |
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JUMP_TB(op_jmp, PARAM1, 1, PARAM2);
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} |
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void OPPROTO op_exit_tb(void) |
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{ |
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EXIT_TB(); |
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} |
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void OPPROTO op_movl_T0_psr(void) |
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{ |
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T0 = compute_cpsr(); |
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} |
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/* NOTE: N = 1 and Z = 1 cannot be stored currently */
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void OPPROTO op_movl_psr_T0(void) |
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{ |
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unsigned int psr; |
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psr = T0; |
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env->CF = (psr >> 29) & 1; |
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env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
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env->VF = (psr << 3) & 0x80000000; |
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/* for user mode we do not update other state info */
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} |
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void OPPROTO op_mul_T0_T1(void) |
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{ |
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T0 = T0 * T1; |
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} |
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/* 64 bit unsigned mul */
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void OPPROTO op_mull_T0_T1(void) |
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{ |
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uint64_t res; |
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res = (uint64_t)T0 * (uint64_t)T1; |
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T1 = res >> 32;
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T0 = res; |
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} |
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/* 64 bit signed mul */
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void OPPROTO op_imull_T0_T1(void) |
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{ |
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uint64_t res; |
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res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
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T1 = res >> 32;
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T0 = res; |
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} |
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/* 48 bit signed mul, top 32 bits */
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void OPPROTO op_imulw_T0_T1(void) |
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{ |
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uint64_t res; |
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res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
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T0 = res >> 16;
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} |
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void OPPROTO op_addq_T0_T1(void) |
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{ |
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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T1 = res >> 32;
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T0 = res; |
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} |
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void OPPROTO op_addq_lo_T0_T1(void) |
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{ |
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += (uint64_t)(env->regs[PARAM1]); |
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T1 = res >> 32;
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T0 = res; |
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} |
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void OPPROTO op_logicq_cc(void) |
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{ |
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env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0); |
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} |
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/* memory access */
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void OPPROTO op_ldub_T0_T1(void) |
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{ |
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T0 = ldub((void *)T1);
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} |
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void OPPROTO op_ldsb_T0_T1(void) |
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{ |
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T0 = ldsb((void *)T1);
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} |
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void OPPROTO op_lduw_T0_T1(void) |
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{ |
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T0 = lduw((void *)T1);
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} |
445 |
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void OPPROTO op_ldsw_T0_T1(void) |
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{ |
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T0 = ldsw((void *)T1);
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} |
450 |
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void OPPROTO op_ldl_T0_T1(void) |
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{ |
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T0 = ldl((void *)T1);
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} |
455 |
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void OPPROTO op_stb_T0_T1(void) |
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{ |
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stb((void *)T1, T0);
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} |
460 |
|
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void OPPROTO op_stw_T0_T1(void) |
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{ |
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stw((void *)T1, T0);
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} |
465 |
|
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void OPPROTO op_stl_T0_T1(void) |
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{ |
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stl((void *)T1, T0);
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} |
470 |
|
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void OPPROTO op_swpb_T0_T1(void) |
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{ |
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int tmp;
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|
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cpu_lock(); |
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tmp = ldub((void *)T1);
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stb((void *)T1, T0);
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T0 = tmp; |
479 |
cpu_unlock(); |
480 |
} |
481 |
|
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void OPPROTO op_swpl_T0_T1(void) |
483 |
{ |
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int tmp;
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|
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cpu_lock(); |
487 |
tmp = ldl((void *)T1);
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stl((void *)T1, T0);
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T0 = tmp; |
490 |
cpu_unlock(); |
491 |
} |
492 |
|
493 |
/* shifts */
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494 |
|
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/* T1 based */
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|
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void OPPROTO op_shll_T1_im(void) |
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{ |
499 |
T1 = T1 << PARAM1; |
500 |
} |
501 |
|
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void OPPROTO op_shrl_T1_im(void) |
503 |
{ |
504 |
T1 = (uint32_t)T1 >> PARAM1; |
505 |
} |
506 |
|
507 |
void OPPROTO op_shrl_T1_0(void) |
508 |
{ |
509 |
T1 = 0;
|
510 |
} |
511 |
|
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void OPPROTO op_sarl_T1_im(void) |
513 |
{ |
514 |
T1 = (int32_t)T1 >> PARAM1; |
515 |
} |
516 |
|
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void OPPROTO op_sarl_T1_0(void) |
518 |
{ |
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T1 = (int32_t)T1 >> 31;
|
520 |
} |
521 |
|
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void OPPROTO op_rorl_T1_im(void) |
523 |
{ |
524 |
int shift;
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shift = PARAM1; |
526 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
527 |
} |
528 |
|
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void OPPROTO op_rrxl_T1(void) |
530 |
{ |
531 |
T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
532 |
} |
533 |
|
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/* T1 based, set C flag */
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void OPPROTO op_shll_T1_im_cc(void) |
536 |
{ |
537 |
env->CF = (T1 >> (32 - PARAM1)) & 1; |
538 |
T1 = T1 << PARAM1; |
539 |
} |
540 |
|
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void OPPROTO op_shrl_T1_im_cc(void) |
542 |
{ |
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env->CF = (T1 >> (PARAM1 - 1)) & 1; |
544 |
T1 = (uint32_t)T1 >> PARAM1; |
545 |
} |
546 |
|
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void OPPROTO op_shrl_T1_0_cc(void) |
548 |
{ |
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env->CF = (T1 >> 31) & 1; |
550 |
T1 = 0;
|
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} |
552 |
|
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void OPPROTO op_sarl_T1_im_cc(void) |
554 |
{ |
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env->CF = (T1 >> (PARAM1 - 1)) & 1; |
556 |
T1 = (int32_t)T1 >> PARAM1; |
557 |
} |
558 |
|
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void OPPROTO op_sarl_T1_0_cc(void) |
560 |
{ |
561 |
env->CF = (T1 >> 31) & 1; |
562 |
T1 = (int32_t)T1 >> 31;
|
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} |
564 |
|
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void OPPROTO op_rorl_T1_im_cc(void) |
566 |
{ |
567 |
int shift;
|
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shift = PARAM1; |
569 |
env->CF = (T1 >> (shift - 1)) & 1; |
570 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
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} |
572 |
|
573 |
void OPPROTO op_rrxl_T1_cc(void) |
574 |
{ |
575 |
uint32_t c; |
576 |
c = T1 & 1;
|
577 |
T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
578 |
env->CF = c; |
579 |
} |
580 |
|
581 |
/* T2 based */
|
582 |
void OPPROTO op_shll_T2_im(void) |
583 |
{ |
584 |
T2 = T2 << PARAM1; |
585 |
} |
586 |
|
587 |
void OPPROTO op_shrl_T2_im(void) |
588 |
{ |
589 |
T2 = (uint32_t)T2 >> PARAM1; |
590 |
} |
591 |
|
592 |
void OPPROTO op_shrl_T2_0(void) |
593 |
{ |
594 |
T2 = 0;
|
595 |
} |
596 |
|
597 |
void OPPROTO op_sarl_T2_im(void) |
598 |
{ |
599 |
T2 = (int32_t)T2 >> PARAM1; |
600 |
} |
601 |
|
602 |
void OPPROTO op_sarl_T2_0(void) |
603 |
{ |
604 |
T2 = (int32_t)T2 >> 31;
|
605 |
} |
606 |
|
607 |
void OPPROTO op_rorl_T2_im(void) |
608 |
{ |
609 |
int shift;
|
610 |
shift = PARAM1; |
611 |
T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
|
612 |
} |
613 |
|
614 |
void OPPROTO op_rrxl_T2(void) |
615 |
{ |
616 |
T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31); |
617 |
} |
618 |
|
619 |
/* T1 based, use T0 as shift count */
|
620 |
|
621 |
void OPPROTO op_shll_T1_T0(void) |
622 |
{ |
623 |
int shift;
|
624 |
shift = T0 & 0xff;
|
625 |
if (shift >= 32) |
626 |
T1 = 0;
|
627 |
else
|
628 |
T1 = T1 << shift; |
629 |
FORCE_RET(); |
630 |
} |
631 |
|
632 |
void OPPROTO op_shrl_T1_T0(void) |
633 |
{ |
634 |
int shift;
|
635 |
shift = T0 & 0xff;
|
636 |
if (shift >= 32) |
637 |
T1 = 0;
|
638 |
else
|
639 |
T1 = (uint32_t)T1 >> shift; |
640 |
FORCE_RET(); |
641 |
} |
642 |
|
643 |
void OPPROTO op_sarl_T1_T0(void) |
644 |
{ |
645 |
int shift;
|
646 |
shift = T0 & 0xff;
|
647 |
if (shift >= 32) |
648 |
shift = 31;
|
649 |
T1 = (int32_t)T1 >> shift; |
650 |
} |
651 |
|
652 |
void OPPROTO op_rorl_T1_T0(void) |
653 |
{ |
654 |
int shift;
|
655 |
shift = T0 & 0x1f;
|
656 |
if (shift) {
|
657 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
658 |
} |
659 |
FORCE_RET(); |
660 |
} |
661 |
|
662 |
/* T1 based, use T0 as shift count and compute CF */
|
663 |
|
664 |
void OPPROTO op_shll_T1_T0_cc(void) |
665 |
{ |
666 |
int shift;
|
667 |
shift = T0 & 0xff;
|
668 |
if (shift >= 32) { |
669 |
if (shift == 32) |
670 |
env->CF = T1 & 1;
|
671 |
else
|
672 |
env->CF = 0;
|
673 |
T1 = 0;
|
674 |
} else if (shift != 0) { |
675 |
env->CF = (T1 >> (32 - shift)) & 1; |
676 |
T1 = T1 << shift; |
677 |
} |
678 |
FORCE_RET(); |
679 |
} |
680 |
|
681 |
void OPPROTO op_shrl_T1_T0_cc(void) |
682 |
{ |
683 |
int shift;
|
684 |
shift = T0 & 0xff;
|
685 |
if (shift >= 32) { |
686 |
if (shift == 32) |
687 |
env->CF = (T1 >> 31) & 1; |
688 |
else
|
689 |
env->CF = 0;
|
690 |
T1 = 0;
|
691 |
} else if (shift != 0) { |
692 |
env->CF = (T1 >> (shift - 1)) & 1; |
693 |
T1 = (uint32_t)T1 >> shift; |
694 |
} |
695 |
FORCE_RET(); |
696 |
} |
697 |
|
698 |
void OPPROTO op_sarl_T1_T0_cc(void) |
699 |
{ |
700 |
int shift;
|
701 |
shift = T0 & 0xff;
|
702 |
if (shift >= 32) { |
703 |
env->CF = (T1 >> 31) & 1; |
704 |
T1 = (int32_t)T1 >> 31;
|
705 |
} else {
|
706 |
env->CF = (T1 >> (shift - 1)) & 1; |
707 |
T1 = (int32_t)T1 >> shift; |
708 |
} |
709 |
FORCE_RET(); |
710 |
} |
711 |
|
712 |
void OPPROTO op_rorl_T1_T0_cc(void) |
713 |
{ |
714 |
int shift1, shift;
|
715 |
shift1 = T0 & 0xff;
|
716 |
shift = shift1 & 0x1f;
|
717 |
if (shift == 0) { |
718 |
if (shift1 != 0) |
719 |
env->CF = (T1 >> 31) & 1; |
720 |
} else {
|
721 |
env->CF = (T1 >> (shift - 1)) & 1; |
722 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
723 |
} |
724 |
FORCE_RET(); |
725 |
} |
726 |
|
727 |
/* misc */
|
728 |
void OPPROTO op_clz_T0(void) |
729 |
{ |
730 |
int count;
|
731 |
for (count = 32; T0 > 0; count--) |
732 |
T0 = T0 >> 1;
|
733 |
T0 = count; |
734 |
FORCE_RET(); |
735 |
} |
736 |
|
737 |
void OPPROTO op_sarl_T0_im(void) |
738 |
{ |
739 |
T0 = (int32_t)T0 >> PARAM1; |
740 |
} |
741 |
|
742 |
/* 16->32 Sign extend */
|
743 |
void OPPROTO op_sxl_T0(void) |
744 |
{ |
745 |
T0 = (int16_t)T0; |
746 |
} |
747 |
|
748 |
void OPPROTO op_sxl_T1(void) |
749 |
{ |
750 |
T1 = (int16_t)T1; |
751 |
} |
752 |
|
753 |
#define SIGNBIT (uint32_t)0x80000000 |
754 |
/* saturating arithmetic */
|
755 |
void OPPROTO op_addl_T0_T1_setq(void) |
756 |
{ |
757 |
uint32_t res; |
758 |
|
759 |
res = T0 + T1; |
760 |
if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT))
|
761 |
env->QF = 1;
|
762 |
|
763 |
T0 = res; |
764 |
FORCE_RET(); |
765 |
} |
766 |
|
767 |
void OPPROTO op_addl_T0_T1_saturate(void) |
768 |
{ |
769 |
uint32_t res; |
770 |
|
771 |
res = T0 + T1; |
772 |
if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT)) {
|
773 |
env->QF = 1;
|
774 |
if (T0 & SIGNBIT)
|
775 |
T0 = 0x80000000;
|
776 |
else
|
777 |
T0 = 0x7fffffff;
|
778 |
} |
779 |
else
|
780 |
T0 = res; |
781 |
|
782 |
FORCE_RET(); |
783 |
} |
784 |
|
785 |
void OPPROTO op_subl_T0_T1_saturate(void) |
786 |
{ |
787 |
uint32_t res; |
788 |
|
789 |
res = T0 - T1; |
790 |
if (((res ^ T0) & SIGNBIT) && ((T0 ^ T1) & SIGNBIT)) {
|
791 |
env->QF = 1;
|
792 |
if (T0 & SIGNBIT)
|
793 |
T0 = 0x8000000;
|
794 |
else
|
795 |
T0 = 0x7fffffff;
|
796 |
} |
797 |
else
|
798 |
T0 = res; |
799 |
|
800 |
FORCE_RET(); |
801 |
} |
802 |
|
803 |
/* thumb shift by immediate */
|
804 |
void OPPROTO op_shll_T0_im_thumb(void) |
805 |
{ |
806 |
int shift;
|
807 |
shift = PARAM1; |
808 |
if (shift != 0) { |
809 |
env->CF = (T1 >> (32 - shift)) & 1; |
810 |
T0 = T0 << shift; |
811 |
} |
812 |
env->NZF = T0; |
813 |
FORCE_RET(); |
814 |
} |
815 |
|
816 |
void OPPROTO op_shrl_T0_im_thumb(void) |
817 |
{ |
818 |
int shift;
|
819 |
|
820 |
shift = PARAM1; |
821 |
if (shift == 0) { |
822 |
env->CF = 0;
|
823 |
T0 = 0;
|
824 |
} else {
|
825 |
env->CF = (T0 >> (shift - 1)) & 1; |
826 |
T0 = T0 >> shift; |
827 |
} |
828 |
FORCE_RET(); |
829 |
} |
830 |
|
831 |
void OPPROTO op_sarl_T0_im_thumb(void) |
832 |
{ |
833 |
int shift;
|
834 |
|
835 |
shift = PARAM1; |
836 |
if (shift == 0) { |
837 |
T0 = ((int32_t)T0) >> 31;
|
838 |
env->CF = T0 & 1;
|
839 |
} else {
|
840 |
env->CF = (T0 >> (shift - 1)) & 1; |
841 |
T0 = ((int32_t)T0) >> shift; |
842 |
} |
843 |
env->NZF = T0; |
844 |
FORCE_RET(); |
845 |
} |
846 |
|
847 |
/* exceptions */
|
848 |
|
849 |
void OPPROTO op_swi(void) |
850 |
{ |
851 |
env->exception_index = EXCP_SWI; |
852 |
cpu_loop_exit(); |
853 |
} |
854 |
|
855 |
void OPPROTO op_undef_insn(void) |
856 |
{ |
857 |
env->exception_index = EXCP_UDEF; |
858 |
cpu_loop_exit(); |
859 |
} |
860 |
|
861 |
/* VFP support. We follow the convention used for VFP instrunctions:
|
862 |
Single precition routines have a "s" suffix, double precision a
|
863 |
"d" suffix. */
|
864 |
|
865 |
#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void) |
866 |
|
867 |
#define VFP_BINOP(name, op) \
|
868 |
VFP_OP(name, s) \ |
869 |
{ \ |
870 |
FT0s = FT0s op FT1s; \ |
871 |
} \ |
872 |
VFP_OP(name, d) \ |
873 |
{ \ |
874 |
FT0d = FT0d op FT1d; \ |
875 |
} |
876 |
VFP_BINOP(add, +) |
877 |
VFP_BINOP(sub, -) |
878 |
VFP_BINOP(mul, *) |
879 |
VFP_BINOP(div, /) |
880 |
#undef VFP_BINOP
|
881 |
|
882 |
#define VFP_HELPER(name) \
|
883 |
VFP_OP(name, s) \ |
884 |
{ \ |
885 |
do_vfp_##name##s(); \ |
886 |
} \ |
887 |
VFP_OP(name, d) \ |
888 |
{ \ |
889 |
do_vfp_##name##d(); \ |
890 |
} |
891 |
VFP_HELPER(abs) |
892 |
VFP_HELPER(sqrt) |
893 |
VFP_HELPER(cmp) |
894 |
VFP_HELPER(cmpe) |
895 |
#undef VFP_HELPER
|
896 |
|
897 |
/* XXX: Will this do the right thing for NANs. Should invert the signbit
|
898 |
without looking at the rest of the value. */
|
899 |
VFP_OP(neg, s) |
900 |
{ |
901 |
FT0s = -FT0s; |
902 |
} |
903 |
|
904 |
VFP_OP(neg, d) |
905 |
{ |
906 |
FT0d = -FT0d; |
907 |
} |
908 |
|
909 |
VFP_OP(F1_ld0, s) |
910 |
{ |
911 |
FT1s = 0.0f; |
912 |
} |
913 |
|
914 |
VFP_OP(F1_ld0, d) |
915 |
{ |
916 |
FT1d = 0.0; |
917 |
} |
918 |
|
919 |
/* Helper routines to perform bitwise copies between float and int. */
|
920 |
static inline float vfp_itos(uint32_t i) |
921 |
{ |
922 |
union {
|
923 |
uint32_t i; |
924 |
float s;
|
925 |
} v; |
926 |
|
927 |
v.i = i; |
928 |
return v.s;
|
929 |
} |
930 |
|
931 |
static inline uint32_t vfp_stoi(float s) |
932 |
{ |
933 |
union {
|
934 |
uint32_t i; |
935 |
float s;
|
936 |
} v; |
937 |
|
938 |
v.s = s; |
939 |
return v.i;
|
940 |
} |
941 |
|
942 |
/* Integer to float conversion. */
|
943 |
VFP_OP(uito, s) |
944 |
{ |
945 |
FT0s = (float)(uint32_t)vfp_stoi(FT0s);
|
946 |
} |
947 |
|
948 |
VFP_OP(uito, d) |
949 |
{ |
950 |
FT0d = (double)(uint32_t)vfp_stoi(FT0s);
|
951 |
} |
952 |
|
953 |
VFP_OP(sito, s) |
954 |
{ |
955 |
FT0s = (float)(int32_t)vfp_stoi(FT0s);
|
956 |
} |
957 |
|
958 |
VFP_OP(sito, d) |
959 |
{ |
960 |
FT0d = (double)(int32_t)vfp_stoi(FT0s);
|
961 |
} |
962 |
|
963 |
/* Float to integer conversion. */
|
964 |
VFP_OP(toui, s) |
965 |
{ |
966 |
FT0s = vfp_itos((uint32_t)FT0s); |
967 |
} |
968 |
|
969 |
VFP_OP(toui, d) |
970 |
{ |
971 |
FT0s = vfp_itos((uint32_t)FT0d); |
972 |
} |
973 |
|
974 |
VFP_OP(tosi, s) |
975 |
{ |
976 |
FT0s = vfp_itos((int32_t)FT0s); |
977 |
} |
978 |
|
979 |
VFP_OP(tosi, d) |
980 |
{ |
981 |
FT0s = vfp_itos((int32_t)FT0d); |
982 |
} |
983 |
|
984 |
/* TODO: Set rounding mode properly. */
|
985 |
VFP_OP(touiz, s) |
986 |
{ |
987 |
FT0s = vfp_itos((uint32_t)FT0s); |
988 |
} |
989 |
|
990 |
VFP_OP(touiz, d) |
991 |
{ |
992 |
FT0s = vfp_itos((uint32_t)FT0d); |
993 |
} |
994 |
|
995 |
VFP_OP(tosiz, s) |
996 |
{ |
997 |
FT0s = vfp_itos((int32_t)FT0s); |
998 |
} |
999 |
|
1000 |
VFP_OP(tosiz, d) |
1001 |
{ |
1002 |
FT0s = vfp_itos((int32_t)FT0d); |
1003 |
} |
1004 |
|
1005 |
/* floating point conversion */
|
1006 |
VFP_OP(fcvtd, s) |
1007 |
{ |
1008 |
FT0d = (double)FT0s;
|
1009 |
} |
1010 |
|
1011 |
VFP_OP(fcvts, d) |
1012 |
{ |
1013 |
FT0s = (float)FT0d;
|
1014 |
} |
1015 |
|
1016 |
/* Get and Put values from registers. */
|
1017 |
VFP_OP(getreg_F0, d) |
1018 |
{ |
1019 |
FT0d = *(double *)((char *) env + PARAM1); |
1020 |
} |
1021 |
|
1022 |
VFP_OP(getreg_F0, s) |
1023 |
{ |
1024 |
FT0s = *(float *)((char *) env + PARAM1); |
1025 |
} |
1026 |
|
1027 |
VFP_OP(getreg_F1, d) |
1028 |
{ |
1029 |
FT1d = *(double *)((char *) env + PARAM1); |
1030 |
} |
1031 |
|
1032 |
VFP_OP(getreg_F1, s) |
1033 |
{ |
1034 |
FT1s = *(float *)((char *) env + PARAM1); |
1035 |
} |
1036 |
|
1037 |
VFP_OP(setreg_F0, d) |
1038 |
{ |
1039 |
*(double *)((char *) env + PARAM1) = FT0d; |
1040 |
} |
1041 |
|
1042 |
VFP_OP(setreg_F0, s) |
1043 |
{ |
1044 |
*(float *)((char *) env + PARAM1) = FT0s; |
1045 |
} |
1046 |
|
1047 |
VFP_OP(foobar, d) |
1048 |
{ |
1049 |
FT0d = env->vfp.regs.s[3];
|
1050 |
} |
1051 |
|
1052 |
void OPPROTO op_vfp_movl_T0_fpscr(void) |
1053 |
{ |
1054 |
do_vfp_get_fpscr (); |
1055 |
} |
1056 |
|
1057 |
void OPPROTO op_vfp_movl_T0_fpscr_flags(void) |
1058 |
{ |
1059 |
T0 = env->vfp.fpscr & (0xf << 28); |
1060 |
} |
1061 |
|
1062 |
void OPPROTO op_vfp_movl_fpscr_T0(void) |
1063 |
{ |
1064 |
do_vfp_set_fpscr(); |
1065 |
} |
1066 |
|
1067 |
/* Move between FT0s to T0 */
|
1068 |
void OPPROTO op_vfp_mrs(void) |
1069 |
{ |
1070 |
T0 = vfp_stoi(FT0s); |
1071 |
} |
1072 |
|
1073 |
void OPPROTO op_vfp_msr(void) |
1074 |
{ |
1075 |
FT0s = vfp_itos(T0); |
1076 |
} |
1077 |
|
1078 |
/* Move between FT0d and {T0,T1} */
|
1079 |
void OPPROTO op_vfp_mrrd(void) |
1080 |
{ |
1081 |
CPU_DoubleU u; |
1082 |
|
1083 |
u.d = FT0d; |
1084 |
T0 = u.l.lower; |
1085 |
T1 = u.l.upper; |
1086 |
} |
1087 |
|
1088 |
void OPPROTO op_vfp_mdrr(void) |
1089 |
{ |
1090 |
CPU_DoubleU u; |
1091 |
|
1092 |
u.l.lower = T0; |
1093 |
u.l.upper = T1; |
1094 |
FT0d = u.d; |
1095 |
} |
1096 |
|
1097 |
/* Floating point load/store. Address is in T1 */
|
1098 |
void OPPROTO op_vfp_lds(void) |
1099 |
{ |
1100 |
FT0s = ldfl((void *)T1);
|
1101 |
} |
1102 |
|
1103 |
void OPPROTO op_vfp_ldd(void) |
1104 |
{ |
1105 |
FT0d = ldfq((void *)T1);
|
1106 |
} |
1107 |
|
1108 |
void OPPROTO op_vfp_sts(void) |
1109 |
{ |
1110 |
stfl((void *)T1, FT0s);
|
1111 |
} |
1112 |
|
1113 |
void OPPROTO op_vfp_std(void) |
1114 |
{ |
1115 |
stfq((void *)T1, FT0d);
|
1116 |
} |